1 /* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */
2
3 /*-
4 * Copyright (c) 1994-1998 Mark Brinicombe.
5 * Copyright (c) 1994 Brini.
6 * All rights reserved.
7 *
8 * This code is derived from software written for Brini by Mark Brinicombe
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Brini.
21 * 4. The name of the company nor the name of the author may be used to
22 * endorse or promote products derived from this software without specific
23 * prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * RiscBSD kernel project
38 *
39 * machdep.c
40 *
41 * Machine dependant functions for kernel setup
42 *
43 * This file needs a lot of work.
44 *
45 * Created : 17/09/94
46 */
47
48 #include <sys/cdefs.h>
49 __FBSDID("$FreeBSD: releng/9.2/sys/arm/xscale/ixp425/avila_machdep.c 218666 2011-02-13 20:02:46Z cognet $");
50
51 #define _ARM32_BUS_DMA_PRIVATE
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysproto.h>
55 #include <sys/signalvar.h>
56 #include <sys/imgact.h>
57 #include <sys/kernel.h>
58 #include <sys/ktr.h>
59 #include <sys/linker.h>
60 #include <sys/lock.h>
61 #include <sys/malloc.h>
62 #include <sys/mutex.h>
63 #include <sys/pcpu.h>
64 #include <sys/proc.h>
65 #include <sys/ptrace.h>
66 #include <sys/cons.h>
67 #include <sys/bio.h>
68 #include <sys/bus.h>
69 #include <sys/buf.h>
70 #include <sys/exec.h>
71 #include <sys/kdb.h>
72 #include <sys/msgbuf.h>
73 #include <machine/reg.h>
74 #include <machine/cpu.h>
75
76 #include <vm/vm.h>
77 #include <vm/pmap.h>
78 #include <vm/vm_object.h>
79 #include <vm/vm_page.h>
80 #include <vm/vm_pager.h>
81 #include <vm/vm_map.h>
82 #include <vm/vnode_pager.h>
83 #include <machine/pmap.h>
84 #include <machine/vmparam.h>
85 #include <machine/pcb.h>
86 #include <machine/undefined.h>
87 #include <machine/machdep.h>
88 #include <machine/metadata.h>
89 #include <machine/armreg.h>
90 #include <machine/bus.h>
91 #include <sys/reboot.h>
92
93 #include <arm/xscale/ixp425/ixp425reg.h>
94 #include <arm/xscale/ixp425/ixp425var.h>
95
96 /* kernel text starts where we were loaded at boot */
97 #define KERNEL_TEXT_OFF (KERNPHYSADDR - PHYSADDR)
98 #define KERNEL_TEXT_BASE (KERNBASE + KERNEL_TEXT_OFF)
99 #define KERNEL_TEXT_PHYS (PHYSADDR + KERNEL_TEXT_OFF)
100
101 #define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
102 #define KERNEL_PT_IO 1
103 #define KERNEL_PT_IO_NUM 3
104 #define KERNEL_PT_BEFOREKERN KERNEL_PT_IO + KERNEL_PT_IO_NUM
105 #define KERNEL_PT_AFKERNEL KERNEL_PT_BEFOREKERN + 1 /* L2 table for mapping after kernel */
106 #define KERNEL_PT_AFKERNEL_NUM 9
107
108 /* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
109 #define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
110
111 /* Define various stack sizes in pages */
112 #define IRQ_STACK_SIZE 1
113 #define ABT_STACK_SIZE 1
114 #define UND_STACK_SIZE 1
115
116 extern u_int data_abort_handler_address;
117 extern u_int prefetch_abort_handler_address;
118 extern u_int undefined_handler_address;
119
120 struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
121
122 extern void *_end;
123
124 extern int *end;
125
126 struct pcpu __pcpu;
127 struct pcpu *pcpup = &__pcpu;
128
129 /* Physical and virtual addresses for some global pages */
130
131 vm_paddr_t phys_avail[10];
132 vm_paddr_t dump_avail[4];
133 vm_offset_t physical_pages;
134
135 struct pv_addr systempage;
136 struct pv_addr msgbufpv;
137 struct pv_addr irqstack;
138 struct pv_addr undstack;
139 struct pv_addr abtstack;
140 struct pv_addr kernelstack;
141 struct pv_addr minidataclean;
142
143 static struct trapframe proc0_tf;
144
145 /* Static device mappings. */
146 static const struct pmap_devmap ixp425_devmap[] = {
147 /* Physical/Virtual address for I/O space */
148 { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE,
149 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
150
151 /* Expansion Bus */
152 { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
153 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
154
155 /* CFI Flash on the Expansion Bus */
156 { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE,
157 IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
158
159 /* IXP425 PCI Configuration */
160 { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
161 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
162
163 /* SDRAM Controller */
164 { IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE,
165 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
166
167 /* PCI Memory Space */
168 { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE,
169 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
170
171 /* Q-Mgr Memory Space */
172 { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE,
173 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
174
175 { 0 },
176 };
177
178 /* Static device mappings. */
179 static const struct pmap_devmap ixp435_devmap[] = {
180 /* Physical/Virtual address for I/O space */
181 { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE,
182 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
183
184 { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
185 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
186
187 /* IXP425 PCI Configuration */
188 { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
189 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
190
191 /* DDRII Controller NB: mapped same place as IXP425 */
192 { IXP425_MCU_VBASE, IXP435_MCU_HWBASE, IXP425_MCU_SIZE,
193 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
194
195 /* PCI Memory Space */
196 { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE,
197 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
198
199 /* Q-Mgr Memory Space */
200 { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE,
201 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
202
203 /* CFI Flash on the Expansion Bus */
204 { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE,
205 IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
206
207 /* USB1 Memory Space */
208 { IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE,
209 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
210 /* USB2 Memory Space */
211 { IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE,
212 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
213
214 /* GPS Memory Space */
215 { CAMBRIA_GPS_VBASE, CAMBRIA_GPS_HWBASE, CAMBRIA_GPS_SIZE,
216 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
217
218 /* RS485 Memory Space */
219 { CAMBRIA_RS485_VBASE, CAMBRIA_RS485_HWBASE, CAMBRIA_RS485_SIZE,
220 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
221
222 { 0 }
223 };
224
225 extern vm_offset_t xscale_cache_clean_addr;
226
227 void *
228 initarm(void *arg, void *arg2)
229 {
230 #define next_chunk2(a,b) (((a) + (b)) &~ ((b)-1))
231 #define next_page(a) next_chunk2(a,PAGE_SIZE)
232 struct pv_addr kernel_l1pt;
233 struct pv_addr dpcpu;
234 int loop, i;
235 u_int l1pagetable;
236 vm_offset_t freemempos;
237 vm_offset_t freemem_pt;
238 vm_offset_t afterkern;
239 vm_offset_t freemem_after;
240 vm_offset_t lastaddr;
241 uint32_t memsize;
242
243 set_cpufuncs(); /* NB: sets cputype */
244 lastaddr = fake_preload_metadata();
245 pcpu_init(pcpup, 0, sizeof(struct pcpu));
246 PCPU_SET(curthread, &thread0);
247
248 /* Do basic tuning, hz etc */
249 init_param1();
250
251 /*
252 * We allocate memory downwards from where we were loaded
253 * by RedBoot; first the L1 page table, then NUM_KERNEL_PTS
254 * entries in the L2 page table. Past that we re-align the
255 * allocation boundary so later data structures (stacks, etc)
256 * can be mapped with different attributes (write-back vs
257 * write-through). Note this leaves a gap for expansion
258 * (or might be repurposed).
259 */
260 freemempos = KERNPHYSADDR;
261
262 /* macros to simplify initial memory allocation */
263 #define alloc_pages(var, np) do { \
264 freemempos -= (np * PAGE_SIZE); \
265 (var) = freemempos; \
266 /* NB: this works because locore maps PA=VA */ \
267 memset((char *)(var), 0, ((np) * PAGE_SIZE)); \
268 } while (0)
269 #define valloc_pages(var, np) do { \
270 alloc_pages((var).pv_pa, (np)); \
271 (var).pv_va = (var).pv_pa + (KERNVIRTADDR - KERNPHYSADDR); \
272 } while (0)
273
274 /* force L1 page table alignment */
275 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
276 freemempos -= PAGE_SIZE;
277 /* allocate contiguous L1 page table */
278 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
279 /* now allocate L2 page tables; they are linked to L1 below */
280 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
281 if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
282 valloc_pages(kernel_pt_table[loop],
283 L2_TABLE_SIZE / PAGE_SIZE);
284 } else {
285 kernel_pt_table[loop].pv_pa = freemempos +
286 (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
287 L2_TABLE_SIZE_REAL;
288 kernel_pt_table[loop].pv_va =
289 kernel_pt_table[loop].pv_pa +
290 (KERNVIRTADDR - KERNPHYSADDR);
291 }
292 }
293 freemem_pt = freemempos; /* base of allocated pt's */
294
295 /*
296 * Re-align allocation boundary so we can map the area
297 * write-back instead of write-through for the stacks and
298 * related structures allocated below.
299 */
300 freemempos = PHYSADDR + 0x100000;
301 /*
302 * Allocate a page for the system page mapped to V0x00000000
303 * This page will just contain the system vectors and can be
304 * shared by all processes.
305 */
306 valloc_pages(systempage, 1);
307
308 /* Allocate dynamic per-cpu area. */
309 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
310 dpcpu_init((void *)dpcpu.pv_va, 0);
311
312 /* Allocate stacks for all modes */
313 valloc_pages(irqstack, IRQ_STACK_SIZE);
314 valloc_pages(abtstack, ABT_STACK_SIZE);
315 valloc_pages(undstack, UND_STACK_SIZE);
316 valloc_pages(kernelstack, KSTACK_PAGES);
317 alloc_pages(minidataclean.pv_pa, 1);
318 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
319 #ifdef ARM_USE_SMALL_ALLOC
320 freemempos -= PAGE_SIZE;
321 freemem_pt = trunc_page(freemem_pt);
322 freemem_after = freemempos - ((freemem_pt - (PHYSADDR + 0x100000)) /
323 PAGE_SIZE) * sizeof(struct arm_small_page);
324 arm_add_smallalloc_pages(
325 (void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)),
326 (void *)0xc0100000,
327 freemem_pt - (PHYSADDR + 0x100000), 1);
328 freemem_after -= ((freemem_after - (PHYSADDR + 0x1000)) / PAGE_SIZE) *
329 sizeof(struct arm_small_page);
330 arm_add_smallalloc_pages(
331 (void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)),
332 (void *)0xc0001000,
333 trunc_page(freemem_after) - (PHYSADDR + 0x1000), 0);
334 freemempos = trunc_page(freemem_after);
335 freemempos -= PAGE_SIZE;
336 #endif
337
338 /*
339 * Now construct the L1 page table. First map the L2
340 * page tables into the L1 so we can replace L1 mappings
341 * later on if necessary
342 */
343 l1pagetable = kernel_l1pt.pv_va;
344
345 /* Map the L2 pages tables in the L1 page table */
346 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
347 &kernel_pt_table[KERNEL_PT_SYS]);
348 pmap_link_l2pt(l1pagetable, IXP425_IO_VBASE,
349 &kernel_pt_table[KERNEL_PT_IO]);
350 pmap_link_l2pt(l1pagetable, IXP425_MCU_VBASE,
351 &kernel_pt_table[KERNEL_PT_IO + 1]);
352 pmap_link_l2pt(l1pagetable, IXP425_PCI_MEM_VBASE,
353 &kernel_pt_table[KERNEL_PT_IO + 2]);
354 pmap_link_l2pt(l1pagetable, KERNBASE,
355 &kernel_pt_table[KERNEL_PT_BEFOREKERN]);
356 pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR, 0x100000,
357 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
358 pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, PHYSADDR + 0x100000,
359 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
360 pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE, KERNEL_TEXT_PHYS,
361 next_chunk2(((uint32_t)lastaddr) - KERNEL_TEXT_BASE, L1_S_SIZE),
362 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
363 freemem_after = next_page((int)lastaddr);
364 afterkern = round_page(next_chunk2((vm_offset_t)lastaddr, L1_S_SIZE));
365 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
366 pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
367 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
368 }
369 pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
370 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
371
372 #ifdef ARM_USE_SMALL_ALLOC
373 if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) {
374 arm_add_smallalloc_pages((void *)(freemem_after),
375 (void*)(freemem_after + PAGE_SIZE),
376 afterkern - (freemem_after + PAGE_SIZE), 0);
377
378 }
379 #endif
380
381 /* Map the Mini-Data cache clean area. */
382 xscale_setup_minidata(l1pagetable, afterkern,
383 minidataclean.pv_pa);
384
385 /* Map the vector page. */
386 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
387 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
388 if (cpu_is_ixp43x())
389 pmap_devmap_bootstrap(l1pagetable, ixp435_devmap);
390 else
391 pmap_devmap_bootstrap(l1pagetable, ixp425_devmap);
392 /*
393 * Give the XScale global cache clean code an appropriately
394 * sized chunk of unmapped VA space starting at 0xff000000
395 * (our device mappings end before this address).
396 */
397 xscale_cache_clean_addr = 0xff000000U;
398
399 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
400 setttb(kernel_l1pt.pv_pa);
401 cpu_tlb_flushID();
402 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
403
404 /*
405 * Pages were allocated during the secondary bootstrap for the
406 * stacks for different CPU modes.
407 * We must now set the r13 registers in the different CPU modes to
408 * point to these stacks.
409 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
410 * of the stack memory.
411 */
412 set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + IRQ_STACK_SIZE*PAGE_SIZE);
413 set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + ABT_STACK_SIZE*PAGE_SIZE);
414 set_stackptr(PSR_UND32_MODE, undstack.pv_va + UND_STACK_SIZE*PAGE_SIZE);
415
416 /*
417 * We must now clean the cache again....
418 * Cleaning may be done by reading new data to displace any
419 * dirty data in the cache. This will have happened in setttb()
420 * but since we are boot strapping the addresses used for the read
421 * may have just been remapped and thus the cache could be out
422 * of sync. A re-clean after the switch will cure this.
423 * After booting there are no gross relocations of the kernel thus
424 * this problem will not occur after initarm().
425 */
426 cpu_idcache_wbinv_all();
427 /* ready to setup the console (XXX move earlier if possible) */
428 cninit();
429 /*
430 * Fetch the RAM size from the MCU registers. The
431 * expansion bus was mapped above so we can now read 'em.
432 */
433 if (cpu_is_ixp43x())
434 memsize = ixp435_ddram_size();
435 else
436 memsize = ixp425_sdram_size();
437 physmem = memsize / PAGE_SIZE;
438
439 /* Set stack for exception handlers */
440
441 data_abort_handler_address = (u_int)data_abort_handler;
442 prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
443 undefined_handler_address = (u_int)undefinedinstruction_bounce;
444 undefined_init();
445
446 proc_linkup0(&proc0, &thread0);
447 thread0.td_kstack = kernelstack.pv_va;
448 thread0.td_pcb = (struct pcb *)
449 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
450 thread0.td_pcb->pcb_flags = 0;
451 thread0.td_frame = &proc0_tf;
452 pcpup->pc_curpcb = thread0.td_pcb;
453
454 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
455
456 pmap_curmaxkvaddr = afterkern + PAGE_SIZE;
457 dump_avail[0] = PHYSADDR;
458 dump_avail[1] = PHYSADDR + memsize;
459 dump_avail[2] = 0;
460 dump_avail[3] = 0;
461
462 pmap_bootstrap(pmap_curmaxkvaddr, 0xd0000000, &kernel_l1pt);
463 msgbufp = (void*)msgbufpv.pv_va;
464 msgbufinit(msgbufp, msgbufsize);
465 mutex_init();
466
467 i = 0;
468 #ifdef ARM_USE_SMALL_ALLOC
469 phys_avail[i++] = PHYSADDR;
470 phys_avail[i++] = PHYSADDR + PAGE_SIZE; /*
471 *XXX: Gross hack to get our
472 * pages in the vm_page_array.
473 */
474 #endif
475 phys_avail[i++] = round_page(virtual_avail - KERNBASE + PHYSADDR);
476 phys_avail[i++] = trunc_page(PHYSADDR + memsize - 1);
477 phys_avail[i++] = 0;
478 phys_avail[i] = 0;
479
480 init_param2(physmem);
481 kdb_init();
482
483 /* use static kernel environment if so configured */
484 if (envmode == 1)
485 kern_envp = static_env;
486
487 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
488 sizeof(struct pcb)));
489 #undef next_page
490 #undef next_chunk2
491 }
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