Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/arm/xscale/ixp425/ixp425.c
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1 /* $NetBSD: ixp425.c,v 1.10 2005/12/11 12:16:51 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro@ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include "opt_ddb.h" 40 41 #define _ARM32_BUS_DMA_PRIVATE 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/module.h> 47 #include <sys/malloc.h> 48 #include <sys/rman.h> 49 #include <machine/armreg.h> 50 #include <machine/bus.h> 51 #include <machine/intr.h> 52 53 #include <vm/vm.h> 54 #include <vm/pmap.h> 55 #include <arm/xscale/ixp425/ixp425reg.h> 56 #include <arm/xscale/ixp425/ixp425var.h> 57 #include <arm/xscale/ixp425/ixp425_intr.h> 58 59 #include <dev/pci/pcireg.h> 60 61 volatile uint32_t intr_enabled; 62 uint32_t intr_steer = 0; 63 64 /* ixp43x et. al have +32 IRQ's */ 65 volatile uint32_t intr_enabled2; 66 uint32_t intr_steer2 = 0; 67 68 struct ixp425_softc *ixp425_softc = NULL; 69 70 struct mtx ixp425_gpio_mtx; 71 72 static int ixp425_probe(device_t); 73 static void ixp425_identify(driver_t *, device_t); 74 static int ixp425_attach(device_t); 75 76 /* 77 * Return a mask of the "fuse" bits that identify 78 * which h/w features are present. 79 * NB: assumes the expansion bus is mapped. 80 */ 81 uint32_t 82 ixp4xx_read_feature_bits(void) 83 { 84 uint32_t bits = ~IXPREG(IXP425_EXP_VBASE + EXP_FCTRL_OFFSET); 85 bits &= ~EXP_FCTRL_RESVD; 86 if (!cpu_is_ixp46x()) 87 bits &= ~EXP_FCTRL_IXP46X_ONLY; 88 return bits; 89 } 90 91 void 92 ixp4xx_write_feature_bits(uint32_t v) 93 { 94 IXPREG(IXP425_EXP_VBASE + EXP_FCTRL_OFFSET) = ~v; 95 } 96 97 struct arm32_dma_range * 98 bus_dma_get_range(void) 99 { 100 return (NULL); 101 } 102 103 int 104 bus_dma_get_range_nb(void) 105 { 106 return (0); 107 } 108 109 static const uint8_t int2gpio[32] __attribute__ ((aligned(32))) = { 110 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#0 -> INT#5 */ 111 0x00, 0x01, /* GPIO#0 -> GPIO#1 */ 112 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#8 -> INT#13 */ 113 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#14 -> INT#18 */ 114 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* GPIO#2 -> GPIO#7 */ 115 0x08, 0x09, 0x0a, 0x0b, 0x0c, /* GPIO#8 -> GPIO#12 */ 116 0xff, 0xff /* INT#30 -> INT#31 */ 117 }; 118 119 static __inline uint32_t 120 ixp425_irq2gpio_bit(int irq) 121 { 122 return (1U << int2gpio[irq]); 123 } 124 125 #ifdef DDB 126 #include <ddb/ddb.h> 127 128 DB_SHOW_COMMAND(gpio, db_show_gpio) 129 { 130 static const char *itype[8] = { 131 [GPIO_TYPE_ACT_HIGH] = "act-high", 132 [GPIO_TYPE_ACT_LOW] = "act-low", 133 [GPIO_TYPE_EDG_RISING] = "edge-rising", 134 [GPIO_TYPE_EDG_FALLING] = "edge-falling", 135 [GPIO_TYPE_TRANSITIONAL]= "transitional", 136 [5] = "type-5", [6] = "type-6", [7] = "type-7" 137 }; 138 uint32_t gpoutr = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOUTR); 139 uint32_t gpoer = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOER); 140 uint32_t gpinr = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPINR); 141 uint32_t gpit1r = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPIT1R); 142 uint32_t gpit2r = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPIT2R); 143 int i, j; 144 145 db_printf("GPOUTR %08x GPINR %08x GPOER %08x GPISR %08x\n", 146 gpoutr, gpinr, gpoer, 147 GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPISR)); 148 db_printf("GPIT1R %08x GPIT2R %08x GPCLKR %08x\n", 149 gpit1r, gpit2r, GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPCLKR)); 150 for (i = 0; i < 16; i++) { 151 db_printf("[%2d] out %u in %u %-3s", i, 152 (gpoutr>>i)&1, (gpinr>>i)&1, (gpoer>>i)&1 ? "in" : "out"); 153 for (j = 0; j < 32; j++) 154 if (int2gpio[j] == i) { 155 db_printf(" irq %2u %s", j, itype[ 156 (((i & 8) ? gpit2r : gpit1r) >> (3*(i&7))) 157 & 7]); 158 break; 159 } 160 db_printf("\n"); 161 } 162 } 163 #endif 164 165 void 166 ixp425_set_gpio(struct ixp425_softc *sc, int pin, int type) 167 { 168 uint32_t gpiotr = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(pin)); 169 170 IXP4XX_GPIO_LOCK(); 171 /* clear interrupt type */ 172 GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(pin), 173 gpiotr &~ GPIO_TYPE(pin, GPIO_TYPE_MASK)); 174 /* clear any pending interrupt */ 175 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR, (1<<pin)); 176 /* set new interrupt type */ 177 GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(pin), 178 gpiotr | GPIO_TYPE(pin, type)); 179 180 /* configure gpio line as an input */ 181 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, 182 GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER) | (1<<pin)); 183 IXP4XX_GPIO_UNLOCK(); 184 } 185 186 static __inline void 187 ixp425_gpio_ack(int irq) 188 { 189 if (irq < 32 && ((1 << irq) & IXP425_INT_GPIOMASK)) 190 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 191 ixp425_irq2gpio_bit(irq); 192 } 193 194 static void 195 ixp425_post_filter(void *arg) 196 { 197 uintptr_t irq = (uintptr_t) arg; 198 ixp425_gpio_ack(irq); 199 } 200 201 void 202 arm_mask_irq(uintptr_t nb) 203 { 204 int i; 205 206 i = disable_interrupts(PSR_I); 207 if (nb < 32) { 208 intr_enabled &= ~(1 << nb); 209 ixp425_set_intrmask(); 210 } else { 211 intr_enabled2 &= ~(1 << (nb - 32)); 212 ixp435_set_intrmask(); 213 } 214 restore_interrupts(i); 215 /*XXX; If it's a GPIO interrupt, ACK it know. Can it be a problem ?*/ 216 ixp425_gpio_ack(nb); 217 } 218 219 void 220 arm_unmask_irq(uintptr_t nb) 221 { 222 int i; 223 224 i = disable_interrupts(PSR_I); 225 if (nb < 32) { 226 intr_enabled |= (1 << nb); 227 ixp425_set_intrmask(); 228 } else { 229 intr_enabled2 |= (1 << (nb - 32)); 230 ixp435_set_intrmask(); 231 } 232 restore_interrupts(i); 233 } 234 235 static __inline uint32_t 236 ixp425_irq_read(void) 237 { 238 return IXPREG(IXP425_INT_STATUS) & intr_enabled; 239 } 240 241 static __inline uint32_t 242 ixp435_irq_read(void) 243 { 244 return IXPREG(IXP435_INT_STATUS2) & intr_enabled2; 245 } 246 247 int 248 arm_get_next_irq(int last) 249 { 250 uint32_t mask; 251 252 last += 1; /* always advance fwd, NB: handles -1 */ 253 if (last < 32) { 254 mask = ixp425_irq_read() >> last; 255 for (; mask != 0; mask >>= 1, last++) { 256 if (mask & 1) 257 return last; 258 } 259 last = 32; 260 } 261 if (cpu_is_ixp43x()) { 262 mask = ixp435_irq_read() >> (32-last); 263 for (; mask != 0; mask >>= 1, last++) { 264 if (mask & 1) 265 return last; 266 } 267 } 268 return -1; 269 } 270 271 void 272 cpu_reset(void) 273 { 274 275 bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, 276 IXP425_OST_WDOG_KEY, OST_WDOG_KEY_MAJICK); 277 bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, 278 IXP425_OST_WDOG, 0); 279 bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, 280 IXP425_OST_WDOG_ENAB, OST_WDOG_ENAB_RST_ENA | 281 OST_WDOG_ENAB_CNT_ENA); 282 printf("Reset failed!\n"); 283 for(;;); 284 } 285 286 static void 287 ixp425_identify(driver_t *driver, device_t parent) 288 { 289 BUS_ADD_CHILD(parent, 0, "ixp", 0); 290 } 291 292 static int 293 ixp425_probe(device_t dev) 294 { 295 device_set_desc(dev, "Intel IXP4XX"); 296 return (0); 297 } 298 299 static int 300 ixp425_attach(device_t dev) 301 { 302 struct ixp425_softc *sc; 303 304 device_printf(dev, "%b\n", ixp4xx_read_feature_bits(), EXP_FCTRL_BITS); 305 306 sc = device_get_softc(dev); 307 sc->sc_iot = &ixp425_bs_tag; 308 KASSERT(ixp425_softc == NULL, ("%s called twice?", __func__)); 309 ixp425_softc = sc; 310 311 intr_enabled = 0; 312 ixp425_set_intrmask(); 313 ixp425_set_intrsteer(); 314 if (cpu_is_ixp43x()) { 315 intr_enabled2 = 0; 316 ixp435_set_intrmask(); 317 ixp435_set_intrsteer(); 318 } 319 arm_post_filter = ixp425_post_filter; 320 321 mtx_init(&ixp425_gpio_mtx, "gpio", NULL, MTX_DEF); 322 if (bus_space_map(sc->sc_iot, IXP425_GPIO_HWBASE, IXP425_GPIO_SIZE, 323 0, &sc->sc_gpio_ioh)) 324 panic("%s: unable to map GPIO registers", __func__); 325 if (bus_space_map(sc->sc_iot, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, 326 0, &sc->sc_exp_ioh)) 327 panic("%s: unable to map Expansion Bus registers", __func__); 328 329 /* XXX belongs in platform init */ 330 if (cpu_is_ixp43x()) 331 cambria_exp_bus_init(sc); 332 333 if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 334 BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0, 335 NULL, NULL, &sc->sc_dmat)) 336 panic("%s: failed to create dma tag", __func__); 337 338 sc->sc_irq_rman.rm_type = RMAN_ARRAY; 339 sc->sc_irq_rman.rm_descr = "IXP4XX IRQs"; 340 if (rman_init(&sc->sc_irq_rman) != 0 || 341 rman_manage_region(&sc->sc_irq_rman, 0, cpu_is_ixp43x() ? 63 : 31) != 0) 342 panic("%s: failed to set up IRQ rman", __func__); 343 344 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 345 sc->sc_mem_rman.rm_descr = "IXP4XX Memory"; 346 if (rman_init(&sc->sc_mem_rman) != 0 || 347 rman_manage_region(&sc->sc_mem_rman, 0, ~0) != 0) 348 panic("%s: failed to set up memory rman", __func__); 349 350 BUS_ADD_CHILD(dev, 0, "pcib", 0); 351 BUS_ADD_CHILD(dev, 0, "ixpclk", 0); 352 BUS_ADD_CHILD(dev, 0, "ixpiic", 0); 353 /* XXX move to hints? */ 354 BUS_ADD_CHILD(dev, 0, "ixpwdog", 0); 355 356 /* attach wired devices via hints */ 357 bus_enumerate_hinted_children(dev); 358 359 bus_generic_probe(dev); 360 bus_generic_attach(dev); 361 362 return (0); 363 } 364 365 static void 366 ixp425_hinted_child(device_t bus, const char *dname, int dunit) 367 { 368 device_t child; 369 struct ixp425_ivar *ivar; 370 371 child = BUS_ADD_CHILD(bus, 0, dname, dunit); 372 ivar = IXP425_IVAR(child); 373 resource_int_value(dname, dunit, "addr", &ivar->addr); 374 resource_int_value(dname, dunit, "irq", &ivar->irq); 375 } 376 377 static device_t 378 ixp425_add_child(device_t dev, u_int order, const char *name, int unit) 379 { 380 device_t child; 381 struct ixp425_ivar *ivar; 382 383 child = device_add_child_ordered(dev, order, name, unit); 384 if (child == NULL) 385 return NULL; 386 ivar = malloc(sizeof(struct ixp425_ivar), M_DEVBUF, M_NOWAIT); 387 if (ivar == NULL) { 388 device_delete_child(dev, child); 389 return NULL; 390 } 391 ivar->addr = 0; 392 ivar->irq = -1; 393 device_set_ivars(child, ivar); 394 return child; 395 } 396 397 static int 398 ixp425_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 399 { 400 struct ixp425_ivar *ivar = IXP425_IVAR(child); 401 402 switch (which) { 403 case IXP425_IVAR_ADDR: 404 if (ivar->addr != 0) { 405 *(uint32_t *)result = ivar->addr; 406 return 0; 407 } 408 break; 409 case IXP425_IVAR_IRQ: 410 if (ivar->irq != -1) { 411 *(int *)result = ivar->irq; 412 return 0; 413 } 414 break; 415 } 416 return EINVAL; 417 } 418 419 /* 420 * NB: This table handles P->V translations for regions setup with 421 * static mappings in initarm. This is used solely for calls to 422 * bus_alloc_resource_any; anything done with bus_space_map is 423 * handled elsewhere and does not require an entry here. 424 * 425 * XXX this table is also used by uart_cpu_getdev via getvbase 426 * (hence the public api) 427 */ 428 struct hwvtrans { 429 uint32_t hwbase; 430 uint32_t size; 431 uint32_t vbase; 432 int isa4x; /* XXX needs special bus space tag */ 433 int isslow; /* XXX needs special bus space tag */ 434 }; 435 436 static const struct hwvtrans * 437 gethwvtrans(uint32_t hwbase, uint32_t size) 438 { 439 static const struct hwvtrans hwvtrans[] = { 440 /* NB: needed only for uart_cpu_getdev */ 441 { .hwbase = IXP425_UART0_HWBASE, 442 .size = IXP425_REG_SIZE, 443 .vbase = IXP425_UART0_VBASE, 444 .isa4x = 1 }, 445 { .hwbase = IXP425_UART1_HWBASE, 446 .size = IXP425_REG_SIZE, 447 .vbase = IXP425_UART1_VBASE, 448 .isa4x = 1 }, 449 { .hwbase = IXP425_PCI_HWBASE, 450 .size = IXP425_PCI_SIZE, 451 .vbase = IXP425_PCI_VBASE }, 452 { .hwbase = IXP425_PCI_MEM_HWBASE, 453 .size = IXP425_PCI_MEM_SIZE, 454 .vbase = IXP425_PCI_MEM_VBASE }, 455 { .hwbase = IXP425_EXP_BUS_CS0_HWBASE, 456 .size = IXP425_EXP_BUS_CS0_SIZE, 457 .vbase = IXP425_EXP_BUS_CS0_VBASE }, 458 /* NB: needed for ixp435 ehci controllers */ 459 { .hwbase = IXP435_USB1_HWBASE, 460 .size = IXP435_USB1_SIZE, 461 .vbase = IXP435_USB1_VBASE }, 462 { .hwbase = IXP435_USB2_HWBASE, 463 .size = IXP435_USB2_SIZE, 464 .vbase = IXP435_USB2_VBASE }, 465 { .hwbase = CAMBRIA_GPS_HWBASE, 466 .size = CAMBRIA_GPS_SIZE, 467 .vbase = CAMBRIA_GPS_VBASE, 468 .isslow = 1 }, 469 { .hwbase = CAMBRIA_RS485_HWBASE, 470 .size = CAMBRIA_RS485_SIZE, 471 .vbase = CAMBRIA_RS485_VBASE, 472 .isslow = 1 }, 473 }; 474 int i; 475 476 for (i = 0; i < nitems(hwvtrans); i++) { 477 if (hwbase >= hwvtrans[i].hwbase && 478 hwbase + size <= hwvtrans[i].hwbase + hwvtrans[i].size) 479 return &hwvtrans[i]; 480 } 481 return NULL; 482 } 483 484 /* XXX for uart_cpu_getdev */ 485 int 486 getvbase(uint32_t hwbase, uint32_t size, uint32_t *vbase) 487 { 488 const struct hwvtrans *hw; 489 490 hw = gethwvtrans(hwbase, size); 491 if (hw == NULL) 492 return (ENOENT); 493 *vbase = hwbase - hw->hwbase + hw->vbase; 494 return (0); 495 } 496 497 static struct resource * 498 ixp425_alloc_resource(device_t dev, device_t child, int type, int *rid, 499 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 500 { 501 struct ixp425_softc *sc = device_get_softc(dev); 502 const struct hwvtrans *vtrans; 503 struct resource *rv; 504 uint32_t addr; 505 int needactivate = flags & RF_ACTIVE; 506 int irq; 507 508 flags &= ~RF_ACTIVE; 509 switch (type) { 510 case SYS_RES_IRQ: 511 /* override per hints */ 512 if (BUS_READ_IVAR(dev, child, IXP425_IVAR_IRQ, &irq) == 0) 513 start = end = irq; 514 rv = rman_reserve_resource(&sc->sc_irq_rman, start, end, count, 515 flags, child); 516 if (rv != NULL) 517 rman_set_rid(rv, *rid); 518 break; 519 520 case SYS_RES_MEMORY: 521 /* override per hints */ 522 if (BUS_READ_IVAR(dev, child, IXP425_IVAR_ADDR, &addr) == 0) { 523 start = addr; 524 /* XXX use nominal window to check for mapping */ 525 vtrans = gethwvtrans(start, 0x1000); 526 if (vtrans != NULL) { 527 /* 528 * Assign the entire mapped region; this may 529 * not be correct but without more info from 530 * the caller we cannot tell. 531 */ 532 end = start + vtrans->size - 533 (start - vtrans->hwbase); 534 if (bootverbose) 535 device_printf(child, 536 "%s: assign 0x%jx:0x%jx%s\n", 537 __func__, start, end - start, 538 vtrans->isa4x ? " A4X" : 539 vtrans->isslow ? " SLOW" : ""); 540 } 541 } else 542 vtrans = gethwvtrans(start, end - start); 543 if (vtrans == NULL) { 544 /* likely means above table needs to be updated */ 545 device_printf(child, "%s: no mapping for 0x%jx:0x%jx\n", 546 __func__, start, end - start); 547 return NULL; 548 } 549 rv = rman_reserve_resource(&sc->sc_mem_rman, start, end, 550 end - start, flags, child); 551 if (rv == NULL) { 552 device_printf(child, "%s: cannot reserve 0x%jx:0x%jx\n", 553 __func__, start, end - start); 554 return NULL; 555 } 556 rman_set_rid(rv, *rid); 557 break; 558 default: 559 rv = NULL; 560 break; 561 } 562 if (rv != NULL && needactivate) { 563 if (bus_activate_resource(child, type, *rid, rv)) { 564 rman_release_resource(rv); 565 return (NULL); 566 } 567 } 568 return (rv); 569 } 570 571 static int 572 ixp425_release_resource(device_t bus, device_t child, int type, int rid, 573 struct resource *r) 574 { 575 /* NB: no private resources, just release */ 576 return rman_release_resource(r); 577 } 578 579 static int 580 ixp425_activate_resource(device_t dev, device_t child, int type, int rid, 581 struct resource *r) 582 { 583 struct ixp425_softc *sc = device_get_softc(dev); 584 const struct hwvtrans *vtrans; 585 586 if (type == SYS_RES_MEMORY) { 587 vtrans = gethwvtrans(rman_get_start(r), rman_get_size(r)); 588 if (vtrans == NULL) { /* NB: should not happen */ 589 device_printf(child, "%s: no mapping for 0x%jx:0x%jx\n", 590 __func__, rman_get_start(r), rman_get_size(r)); 591 return (ENOENT); 592 } 593 if (vtrans->isa4x) 594 rman_set_bustag(r, &ixp425_a4x_bs_tag); 595 else if (vtrans->isslow) 596 rman_set_bustag(r, &cambria_exp_bs_tag); 597 else 598 rman_set_bustag(r, sc->sc_iot); 599 rman_set_bushandle(r, vtrans->vbase); 600 } 601 return (rman_activate_resource(r)); 602 } 603 604 static int 605 ixp425_deactivate_resource(device_t bus, device_t child, int type, int rid, 606 struct resource *r) 607 { 608 /* NB: no private resources, just deactive */ 609 return (rman_deactivate_resource(r)); 610 } 611 612 static __inline void 613 get_masks(struct resource *res, uint32_t *mask, uint32_t *mask2) 614 { 615 int i; 616 617 *mask = 0; 618 for (i = rman_get_start(res); i < 32 && i <= rman_get_end(res); i++) 619 *mask |= 1 << i; 620 *mask2 = 0; 621 for (; i <= rman_get_end(res); i++) 622 *mask2 |= 1 << (i - 32); 623 } 624 625 static __inline void 626 update_masks(uint32_t mask, uint32_t mask2) 627 { 628 629 intr_enabled = mask; 630 ixp425_set_intrmask(); 631 if (cpu_is_ixp43x()) { 632 intr_enabled2 = mask2; 633 ixp435_set_intrmask(); 634 } 635 } 636 637 static int 638 ixp425_setup_intr(device_t dev, device_t child, 639 struct resource *res, int flags, driver_filter_t *filt, 640 driver_intr_t *intr, void *arg, void **cookiep) 641 { 642 uint32_t mask, mask2; 643 int error; 644 645 error = BUS_SETUP_INTR(device_get_parent(dev), child, res, flags, 646 filt, intr, arg, cookiep); 647 if (error) 648 return (error); 649 650 get_masks(res, &mask, &mask2); 651 update_masks(intr_enabled | mask, intr_enabled2 | mask2); 652 653 return (0); 654 } 655 656 static int 657 ixp425_teardown_intr(device_t dev, device_t child, struct resource *res, 658 void *cookie) 659 { 660 uint32_t mask, mask2; 661 662 get_masks(res, &mask, &mask2); 663 update_masks(intr_enabled &~ mask, intr_enabled2 &~ mask2); 664 665 return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); 666 } 667 668 static device_method_t ixp425_methods[] = { 669 /* Device interface */ 670 DEVMETHOD(device_probe, ixp425_probe), 671 DEVMETHOD(device_attach, ixp425_attach), 672 DEVMETHOD(device_identify, ixp425_identify), 673 674 /* Bus interface */ 675 DEVMETHOD(bus_add_child, ixp425_add_child), 676 DEVMETHOD(bus_hinted_child, ixp425_hinted_child), 677 DEVMETHOD(bus_read_ivar, ixp425_read_ivar), 678 679 DEVMETHOD(bus_alloc_resource, ixp425_alloc_resource), 680 DEVMETHOD(bus_release_resource, ixp425_release_resource), 681 DEVMETHOD(bus_activate_resource, ixp425_activate_resource), 682 DEVMETHOD(bus_deactivate_resource, ixp425_deactivate_resource), 683 DEVMETHOD(bus_setup_intr, ixp425_setup_intr), 684 DEVMETHOD(bus_teardown_intr, ixp425_teardown_intr), 685 686 {0, 0}, 687 }; 688 689 static driver_t ixp425_driver = { 690 "ixp", 691 ixp425_methods, 692 sizeof(struct ixp425_softc), 693 }; 694 static devclass_t ixp425_devclass; 695 696 DRIVER_MODULE(ixp, nexus, ixp425_driver, ixp425_devclass, 0, 0);
Cache object: d4c7bc71cd4ad6797e5166ac70991585
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