Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/xscale/ixp425/ixp425.c
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1 /* $NetBSD: ixp425.c,v 1.10 2005/12/11 12:16:51 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro@ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include "opt_ddb.h" 40 41 #define _ARM32_BUS_DMA_PRIVATE 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/module.h> 47 #include <sys/malloc.h> 48 #include <sys/rman.h> 49 #include <machine/bus.h> 50 #include <machine/intr.h> 51 52 #include <vm/vm.h> 53 #include <vm/pmap.h> 54 #include <arm/xscale/ixp425/ixp425reg.h> 55 #include <arm/xscale/ixp425/ixp425var.h> 56 #include <arm/xscale/ixp425/ixp425_intr.h> 57 58 #include <dev/pci/pcireg.h> 59 60 volatile uint32_t intr_enabled; 61 uint32_t intr_steer = 0; 62 63 /* ixp43x et. al have +32 IRQ's */ 64 volatile uint32_t intr_enabled2; 65 uint32_t intr_steer2 = 0; 66 67 struct ixp425_softc *ixp425_softc = NULL; 68 69 static int ixp425_probe(device_t); 70 static void ixp425_identify(driver_t *, device_t); 71 static int ixp425_attach(device_t); 72 73 /* 74 * Return a mask of the "fuse" bits that identify 75 * which h/w features are present. 76 * NB: assumes the expansion bus is mapped. 77 */ 78 uint32_t 79 ixp4xx_read_feature_bits(void) 80 { 81 uint32_t bits = ~IXPREG(IXP425_EXP_VBASE + EXP_FCTRL_OFFSET); 82 bits &= ~EXP_FCTRL_RESVD; 83 if (!cpu_is_ixp46x()) 84 bits &= ~EXP_FCTRL_IXP46X_ONLY; 85 return bits; 86 } 87 88 void 89 ixp4xx_write_feature_bits(uint32_t v) 90 { 91 IXPREG(IXP425_EXP_VBASE + EXP_FCTRL_OFFSET) = ~v; 92 } 93 94 struct arm32_dma_range * 95 bus_dma_get_range(void) 96 { 97 return (NULL); 98 } 99 100 int 101 bus_dma_get_range_nb(void) 102 { 103 return (0); 104 } 105 106 static const uint8_t int2gpio[32] __attribute__ ((aligned(32))) = { 107 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#0 -> INT#5 */ 108 0x00, 0x01, /* GPIO#0 -> GPIO#1 */ 109 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#8 -> INT#13 */ 110 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#14 -> INT#18 */ 111 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* GPIO#2 -> GPIO#7 */ 112 0x08, 0x09, 0x0a, 0x0b, 0x0c, /* GPIO#8 -> GPIO#12 */ 113 0xff, 0xff /* INT#30 -> INT#31 */ 114 }; 115 116 static __inline uint32_t 117 ixp425_irq2gpio_bit(int irq) 118 { 119 return (1U << int2gpio[irq]); 120 } 121 122 #ifdef DDB 123 #include <ddb/ddb.h> 124 125 DB_SHOW_COMMAND(gpio, db_show_gpio) 126 { 127 static const char *itype[8] = { 128 [GPIO_TYPE_ACT_HIGH] = "act-high", 129 [GPIO_TYPE_ACT_LOW] = "act-low", 130 [GPIO_TYPE_EDG_RISING] = "edge-rising", 131 [GPIO_TYPE_EDG_FALLING] = "edge-falling", 132 [GPIO_TYPE_TRANSITIONAL]= "transitional", 133 [5] = "type-5", [6] = "type-6", [7] = "type-7" 134 }; 135 uint32_t gpoutr = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOUTR); 136 uint32_t gpoer = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOER); 137 uint32_t gpinr = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPINR); 138 uint32_t gpit1r = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPIT1R); 139 uint32_t gpit2r = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPIT2R); 140 int i, j; 141 142 db_printf("GPOUTR %08x GPINR %08x GPOER %08x GPISR %08x\n", 143 gpoutr, gpinr, gpoer, 144 GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPISR)); 145 db_printf("GPIT1R %08x GPIT2R %08x GPCLKR %08x\n", 146 gpit1r, gpit2r, GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPCLKR)); 147 for (i = 0; i < 16; i++) { 148 db_printf("[%2d] out %u in %u %-3s", i, 149 (gpoutr>>i)&1, (gpinr>>i)&1, (gpoer>>i)&1 ? "in" : "out"); 150 for (j = 0; j < 32; j++) 151 if (int2gpio[j] == i) { 152 db_printf(" irq %2u %s", j, itype[ 153 (((i & 8) ? gpit2r : gpit1r) >> (3*(i&7))) 154 & 7]); 155 break; 156 } 157 db_printf("\n"); 158 } 159 } 160 #endif 161 162 void 163 ixp425_set_gpio(struct ixp425_softc *sc, int pin, int type) 164 { 165 uint32_t gpiotr = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(pin)); 166 167 /* clear interrupt type */ 168 GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(pin), 169 gpiotr &~ GPIO_TYPE(pin, GPIO_TYPE_MASK)); 170 /* clear any pending interrupt */ 171 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR, (1<<pin)); 172 /* set new interrupt type */ 173 GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(pin), 174 gpiotr | GPIO_TYPE(pin, type)); 175 176 /* configure gpio line as an input */ 177 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, 178 GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER) | (1<<pin)); 179 } 180 181 static __inline void 182 ixp425_gpio_ack(int irq) 183 { 184 if (irq < 32 && ((1 << irq) & IXP425_INT_GPIOMASK)) 185 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = 186 ixp425_irq2gpio_bit(irq); 187 } 188 189 static void 190 ixp425_post_filter(void *arg) 191 { 192 uintptr_t irq = (uintptr_t) arg; 193 ixp425_gpio_ack(irq); 194 } 195 196 void 197 arm_mask_irq(uintptr_t nb) 198 { 199 int i; 200 201 i = disable_interrupts(I32_bit); 202 if (nb < 32) { 203 intr_enabled &= ~(1 << nb); 204 ixp425_set_intrmask(); 205 } else { 206 intr_enabled2 &= ~(1 << (nb - 32)); 207 ixp435_set_intrmask(); 208 } 209 restore_interrupts(i); 210 /*XXX; If it's a GPIO interrupt, ACK it know. Can it be a problem ?*/ 211 ixp425_gpio_ack(nb); 212 } 213 214 void 215 arm_unmask_irq(uintptr_t nb) 216 { 217 int i; 218 219 i = disable_interrupts(I32_bit); 220 if (nb < 32) { 221 intr_enabled |= (1 << nb); 222 ixp425_set_intrmask(); 223 } else { 224 intr_enabled2 |= (1 << (nb - 32)); 225 ixp435_set_intrmask(); 226 } 227 restore_interrupts(i); 228 } 229 230 static __inline uint32_t 231 ixp425_irq_read(void) 232 { 233 return IXPREG(IXP425_INT_STATUS) & intr_enabled; 234 } 235 236 static __inline uint32_t 237 ixp435_irq_read(void) 238 { 239 return IXPREG(IXP435_INT_STATUS2) & intr_enabled2; 240 } 241 242 int 243 arm_get_next_irq(int last) 244 { 245 uint32_t mask; 246 247 last += 1; /* always advance fwd, NB: handles -1 */ 248 if (last < 32) { 249 mask = ixp425_irq_read() >> last; 250 for (; mask != 0; mask >>= 1, last++) { 251 if (mask & 1) 252 return last; 253 } 254 last = 32; 255 } 256 if (cpu_is_ixp43x()) { 257 mask = ixp435_irq_read() >> (32-last); 258 for (; mask != 0; mask >>= 1, last++) { 259 if (mask & 1) 260 return last; 261 } 262 } 263 return -1; 264 } 265 266 void 267 cpu_reset(void) 268 { 269 270 bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, 271 IXP425_OST_WDOG_KEY, OST_WDOG_KEY_MAJICK); 272 bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, 273 IXP425_OST_WDOG, 0); 274 bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, 275 IXP425_OST_WDOG_ENAB, OST_WDOG_ENAB_RST_ENA | 276 OST_WDOG_ENAB_CNT_ENA); 277 printf("Reset failed!\n"); 278 for(;;); 279 } 280 281 static void 282 ixp425_identify(driver_t *driver, device_t parent) 283 { 284 BUS_ADD_CHILD(parent, 0, "ixp", 0); 285 } 286 287 static int 288 ixp425_probe(device_t dev) 289 { 290 device_set_desc(dev, "Intel IXP4XX"); 291 return (0); 292 } 293 294 static int 295 ixp425_attach(device_t dev) 296 { 297 struct ixp425_softc *sc; 298 299 device_printf(dev, "%b\n", ixp4xx_read_feature_bits(), EXP_FCTRL_BITS); 300 301 sc = device_get_softc(dev); 302 sc->sc_iot = &ixp425_bs_tag; 303 KASSERT(ixp425_softc == NULL, ("%s called twice?", __func__)); 304 ixp425_softc = sc; 305 306 intr_enabled = 0; 307 ixp425_set_intrmask(); 308 ixp425_set_intrsteer(); 309 if (cpu_is_ixp43x()) { 310 intr_enabled2 = 0; 311 ixp435_set_intrmask(); 312 ixp435_set_intrsteer(); 313 } 314 arm_post_filter = ixp425_post_filter; 315 316 if (bus_space_map(sc->sc_iot, IXP425_GPIO_HWBASE, IXP425_GPIO_SIZE, 317 0, &sc->sc_gpio_ioh)) 318 panic("%s: unable to map GPIO registers", __func__); 319 if (bus_space_map(sc->sc_iot, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, 320 0, &sc->sc_exp_ioh)) 321 panic("%s: unable to map Expansion Bus registers", __func__); 322 323 /* XXX belongs in platform init */ 324 if (cpu_is_ixp43x()) 325 cambria_exp_bus_init(sc); 326 327 if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 328 BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0, 329 NULL, NULL, &sc->sc_dmat)) 330 panic("%s: failed to create dma tag", __func__); 331 332 sc->sc_irq_rman.rm_type = RMAN_ARRAY; 333 sc->sc_irq_rman.rm_descr = "IXP4XX IRQs"; 334 if (rman_init(&sc->sc_irq_rman) != 0 || 335 rman_manage_region(&sc->sc_irq_rman, 0, cpu_is_ixp43x() ? 63 : 31) != 0) 336 panic("%s: failed to set up IRQ rman", __func__); 337 338 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 339 sc->sc_mem_rman.rm_descr = "IXP4XX Memory"; 340 if (rman_init(&sc->sc_mem_rman) != 0 || 341 rman_manage_region(&sc->sc_mem_rman, 0, ~0) != 0) 342 panic("%s: failed to set up memory rman", __func__); 343 344 BUS_ADD_CHILD(dev, 0, "pcib", 0); 345 BUS_ADD_CHILD(dev, 0, "ixpclk", 0); 346 BUS_ADD_CHILD(dev, 0, "ixpiic", 0); 347 /* XXX move to hints? */ 348 BUS_ADD_CHILD(dev, 0, "ixpwdog", 0); 349 350 /* attach wired devices via hints */ 351 bus_enumerate_hinted_children(dev); 352 353 bus_generic_probe(dev); 354 bus_generic_attach(dev); 355 356 return (0); 357 } 358 359 static void 360 ixp425_hinted_child(device_t bus, const char *dname, int dunit) 361 { 362 device_t child; 363 struct ixp425_ivar *ivar; 364 365 child = BUS_ADD_CHILD(bus, 0, dname, dunit); 366 ivar = IXP425_IVAR(child); 367 resource_int_value(dname, dunit, "addr", &ivar->addr); 368 resource_int_value(dname, dunit, "irq", &ivar->irq); 369 } 370 371 static device_t 372 ixp425_add_child(device_t dev, u_int order, const char *name, int unit) 373 { 374 device_t child; 375 struct ixp425_ivar *ivar; 376 377 child = device_add_child_ordered(dev, order, name, unit); 378 if (child == NULL) 379 return NULL; 380 ivar = malloc(sizeof(struct ixp425_ivar), M_DEVBUF, M_NOWAIT); 381 if (ivar == NULL) { 382 device_delete_child(dev, child); 383 return NULL; 384 } 385 ivar->addr = 0; 386 ivar->irq = -1; 387 device_set_ivars(child, ivar); 388 return child; 389 } 390 391 static int 392 ixp425_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 393 { 394 struct ixp425_ivar *ivar = IXP425_IVAR(child); 395 396 switch (which) { 397 case IXP425_IVAR_ADDR: 398 if (ivar->addr != 0) { 399 *(uint32_t *)result = ivar->addr; 400 return 0; 401 } 402 break; 403 case IXP425_IVAR_IRQ: 404 if (ivar->irq != -1) { 405 *(int *)result = ivar->irq; 406 return 0; 407 } 408 break; 409 } 410 return EINVAL; 411 } 412 413 /* 414 * NB: This table handles P->V translations for regions setup with 415 * static mappings in initarm. This is used solely for calls to 416 * bus_alloc_resource_any; anything done with bus_space_map is 417 * handled elsewhere and does not require an entry here. 418 * 419 * XXX this table is also used by uart_cpu_getdev via getvbase 420 * (hence the public api) 421 */ 422 struct hwvtrans { 423 uint32_t hwbase; 424 uint32_t size; 425 uint32_t vbase; 426 int isa4x; /* XXX needs special bus space tag */ 427 int isslow; /* XXX needs special bus space tag */ 428 }; 429 430 static const struct hwvtrans * 431 gethwvtrans(uint32_t hwbase, uint32_t size) 432 { 433 static const struct hwvtrans hwvtrans[] = { 434 /* NB: needed only for uart_cpu_getdev */ 435 { .hwbase = IXP425_UART0_HWBASE, 436 .size = IXP425_REG_SIZE, 437 .vbase = IXP425_UART0_VBASE, 438 .isa4x = 1 }, 439 { .hwbase = IXP425_UART1_HWBASE, 440 .size = IXP425_REG_SIZE, 441 .vbase = IXP425_UART1_VBASE, 442 .isa4x = 1 }, 443 { .hwbase = IXP425_PCI_HWBASE, 444 .size = IXP425_PCI_SIZE, 445 .vbase = IXP425_PCI_VBASE }, 446 { .hwbase = IXP425_PCI_MEM_HWBASE, 447 .size = IXP425_PCI_MEM_SIZE, 448 .vbase = IXP425_PCI_MEM_VBASE }, 449 { .hwbase = IXP425_EXP_BUS_CS0_HWBASE, 450 .size = IXP425_EXP_BUS_CS0_SIZE, 451 .vbase = IXP425_EXP_BUS_CS0_VBASE }, 452 /* NB: needed for ixp435 ehci controllers */ 453 { .hwbase = IXP435_USB1_HWBASE, 454 .size = IXP435_USB1_SIZE, 455 .vbase = IXP435_USB1_VBASE }, 456 { .hwbase = IXP435_USB2_HWBASE, 457 .size = IXP435_USB2_SIZE, 458 .vbase = IXP435_USB2_VBASE }, 459 { .hwbase = CAMBRIA_GPS_HWBASE, 460 .size = CAMBRIA_GPS_SIZE, 461 .vbase = CAMBRIA_GPS_VBASE, 462 .isslow = 1 }, 463 { .hwbase = CAMBRIA_RS485_HWBASE, 464 .size = CAMBRIA_RS485_SIZE, 465 .vbase = CAMBRIA_RS485_VBASE, 466 .isslow = 1 }, 467 }; 468 int i; 469 470 for (i = 0; i < sizeof hwvtrans / sizeof *hwvtrans; i++) { 471 if (hwbase >= hwvtrans[i].hwbase && 472 hwbase + size <= hwvtrans[i].hwbase + hwvtrans[i].size) 473 return &hwvtrans[i]; 474 } 475 return NULL; 476 } 477 478 /* XXX for uart_cpu_getdev */ 479 int 480 getvbase(uint32_t hwbase, uint32_t size, uint32_t *vbase) 481 { 482 const struct hwvtrans *hw; 483 484 hw = gethwvtrans(hwbase, size); 485 if (hw == NULL) 486 return (ENOENT); 487 *vbase = hwbase - hw->hwbase + hw->vbase; 488 return (0); 489 } 490 491 static struct resource * 492 ixp425_alloc_resource(device_t dev, device_t child, int type, int *rid, 493 u_long start, u_long end, u_long count, u_int flags) 494 { 495 struct ixp425_softc *sc = device_get_softc(dev); 496 const struct hwvtrans *vtrans; 497 struct resource *rv; 498 uint32_t addr; 499 int needactivate = flags & RF_ACTIVE; 500 int irq; 501 502 flags &= ~RF_ACTIVE; 503 switch (type) { 504 case SYS_RES_IRQ: 505 /* override per hints */ 506 if (BUS_READ_IVAR(dev, child, IXP425_IVAR_IRQ, &irq) == 0) 507 start = end = irq; 508 rv = rman_reserve_resource(&sc->sc_irq_rman, start, end, count, 509 flags, child); 510 if (rv != NULL) 511 rman_set_rid(rv, *rid); 512 break; 513 514 case SYS_RES_MEMORY: 515 /* override per hints */ 516 if (BUS_READ_IVAR(dev, child, IXP425_IVAR_ADDR, &addr) == 0) { 517 start = addr; 518 /* XXX use nominal window to check for mapping */ 519 vtrans = gethwvtrans(start, 0x1000); 520 if (vtrans != NULL) { 521 /* 522 * Assign the entire mapped region; this may 523 * not be correct but without more info from 524 * the caller we cannot tell. 525 */ 526 end = start + vtrans->size - 527 (start - vtrans->hwbase); 528 if (bootverbose) 529 device_printf(child, 530 "%s: assign 0x%lx:0x%lx%s\n", 531 __func__, start, end - start, 532 vtrans->isa4x ? " A4X" : 533 vtrans->isslow ? " SLOW" : ""); 534 } 535 } else 536 vtrans = gethwvtrans(start, end - start); 537 if (vtrans == NULL) { 538 /* likely means above table needs to be updated */ 539 device_printf(child, "%s: no mapping for 0x%lx:0x%lx\n", 540 __func__, start, end - start); 541 return NULL; 542 } 543 rv = rman_reserve_resource(&sc->sc_mem_rman, start, end, 544 end - start, flags, child); 545 if (rv == NULL) { 546 device_printf(child, "%s: cannot reserve 0x%lx:0x%lx\n", 547 __func__, start, end - start); 548 return NULL; 549 } 550 rman_set_rid(rv, *rid); 551 break; 552 default: 553 rv = NULL; 554 break; 555 } 556 if (rv != NULL && needactivate) { 557 if (bus_activate_resource(child, type, *rid, rv)) { 558 rman_release_resource(rv); 559 return (NULL); 560 } 561 } 562 return (rv); 563 } 564 565 static int 566 ixp425_release_resource(device_t bus, device_t child, int type, int rid, 567 struct resource *r) 568 { 569 /* NB: no private resources, just release */ 570 return rman_release_resource(r); 571 } 572 573 static int 574 ixp425_activate_resource(device_t dev, device_t child, int type, int rid, 575 struct resource *r) 576 { 577 struct ixp425_softc *sc = device_get_softc(dev); 578 const struct hwvtrans *vtrans; 579 580 if (type == SYS_RES_MEMORY) { 581 vtrans = gethwvtrans(rman_get_start(r), rman_get_size(r)); 582 if (vtrans == NULL) { /* NB: should not happen */ 583 device_printf(child, "%s: no mapping for 0x%lx:0x%lx\n", 584 __func__, rman_get_start(r), rman_get_size(r)); 585 return (ENOENT); 586 } 587 if (vtrans->isa4x) 588 rman_set_bustag(r, &ixp425_a4x_bs_tag); 589 else if (vtrans->isslow) 590 rman_set_bustag(r, &cambria_exp_bs_tag); 591 else 592 rman_set_bustag(r, sc->sc_iot); 593 rman_set_bushandle(r, vtrans->vbase); 594 } 595 return (rman_activate_resource(r)); 596 } 597 598 static int 599 ixp425_deactivate_resource(device_t bus, device_t child, int type, int rid, 600 struct resource *r) 601 { 602 /* NB: no private resources, just deactive */ 603 return (rman_deactivate_resource(r)); 604 } 605 606 static __inline void 607 get_masks(struct resource *res, uint32_t *mask, uint32_t *mask2) 608 { 609 int i; 610 611 *mask = 0; 612 for (i = rman_get_start(res); i < 32 && i <= rman_get_end(res); i++) 613 *mask |= 1 << i; 614 *mask2 = 0; 615 for (; i <= rman_get_end(res); i++) 616 *mask2 |= 1 << (i - 32); 617 } 618 619 static __inline void 620 update_masks(uint32_t mask, uint32_t mask2) 621 { 622 623 intr_enabled = mask; 624 ixp425_set_intrmask(); 625 if (cpu_is_ixp43x()) { 626 intr_enabled2 = mask2; 627 ixp435_set_intrmask(); 628 } 629 } 630 631 static int 632 ixp425_setup_intr(device_t dev, device_t child, 633 struct resource *res, int flags, driver_filter_t *filt, 634 driver_intr_t *intr, void *arg, void **cookiep) 635 { 636 uint32_t mask, mask2; 637 638 BUS_SETUP_INTR(device_get_parent(dev), child, res, flags, filt, intr, 639 arg, cookiep); 640 641 get_masks(res, &mask, &mask2); 642 update_masks(intr_enabled | mask, intr_enabled2 | mask2); 643 644 return (0); 645 } 646 647 static int 648 ixp425_teardown_intr(device_t dev, device_t child, struct resource *res, 649 void *cookie) 650 { 651 uint32_t mask, mask2; 652 653 get_masks(res, &mask, &mask2); 654 update_masks(intr_enabled &~ mask, intr_enabled2 &~ mask2); 655 656 return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); 657 } 658 659 static device_method_t ixp425_methods[] = { 660 /* Device interface */ 661 DEVMETHOD(device_probe, ixp425_probe), 662 DEVMETHOD(device_attach, ixp425_attach), 663 DEVMETHOD(device_identify, ixp425_identify), 664 665 /* Bus interface */ 666 DEVMETHOD(bus_add_child, ixp425_add_child), 667 DEVMETHOD(bus_hinted_child, ixp425_hinted_child), 668 DEVMETHOD(bus_read_ivar, ixp425_read_ivar), 669 670 DEVMETHOD(bus_alloc_resource, ixp425_alloc_resource), 671 DEVMETHOD(bus_release_resource, ixp425_release_resource), 672 DEVMETHOD(bus_activate_resource, ixp425_activate_resource), 673 DEVMETHOD(bus_deactivate_resource, ixp425_deactivate_resource), 674 DEVMETHOD(bus_setup_intr, ixp425_setup_intr), 675 DEVMETHOD(bus_teardown_intr, ixp425_teardown_intr), 676 677 {0, 0}, 678 }; 679 680 static driver_t ixp425_driver = { 681 "ixp", 682 ixp425_methods, 683 sizeof(struct ixp425_softc), 684 }; 685 static devclass_t ixp425_devclass; 686 687 DRIVER_MODULE(ixp, nexus, ixp425_driver, ixp425_devclass, 0, 0);
Cache object: ef1280575696c89d3df9059131598119
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