1 /* $NetBSD: ixp425.c,v 1.10 2005/12/11 12:16:51 christos Exp $ */
2
3 /*
4 * Copyright (c) 2003
5 * Ichiro FUKUHARA <ichiro@ichiro.org>.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Ichiro FUKUHARA.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD: releng/9.1/sys/arm/xscale/ixp425/ixp425.c 215319 2010-11-14 20:41:22Z thompsa $");
38
39 #include "opt_ddb.h"
40
41 #define _ARM32_BUS_DMA_PRIVATE
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/bus.h>
45 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/malloc.h>
48 #include <sys/rman.h>
49 #include <machine/bus.h>
50 #include <machine/intr.h>
51
52 #include <vm/vm.h>
53 #include <vm/pmap.h>
54 #include <arm/xscale/ixp425/ixp425reg.h>
55 #include <arm/xscale/ixp425/ixp425var.h>
56 #include <arm/xscale/ixp425/ixp425_intr.h>
57
58 #include <dev/pci/pcireg.h>
59
60 volatile uint32_t intr_enabled;
61 uint32_t intr_steer = 0;
62
63 /* ixp43x et. al have +32 IRQ's */
64 volatile uint32_t intr_enabled2;
65 uint32_t intr_steer2 = 0;
66
67 struct ixp425_softc *ixp425_softc = NULL;
68
69 struct mtx ixp425_gpio_mtx;
70
71 static int ixp425_probe(device_t);
72 static void ixp425_identify(driver_t *, device_t);
73 static int ixp425_attach(device_t);
74
75 /*
76 * Return a mask of the "fuse" bits that identify
77 * which h/w features are present.
78 * NB: assumes the expansion bus is mapped.
79 */
80 uint32_t
81 ixp4xx_read_feature_bits(void)
82 {
83 uint32_t bits = ~IXPREG(IXP425_EXP_VBASE + EXP_FCTRL_OFFSET);
84 bits &= ~EXP_FCTRL_RESVD;
85 if (!cpu_is_ixp46x())
86 bits &= ~EXP_FCTRL_IXP46X_ONLY;
87 return bits;
88 }
89
90 void
91 ixp4xx_write_feature_bits(uint32_t v)
92 {
93 IXPREG(IXP425_EXP_VBASE + EXP_FCTRL_OFFSET) = ~v;
94 }
95
96 struct arm32_dma_range *
97 bus_dma_get_range(void)
98 {
99 return (NULL);
100 }
101
102 int
103 bus_dma_get_range_nb(void)
104 {
105 return (0);
106 }
107
108 static const uint8_t int2gpio[32] __attribute__ ((aligned(32))) = {
109 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#0 -> INT#5 */
110 0x00, 0x01, /* GPIO#0 -> GPIO#1 */
111 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#8 -> INT#13 */
112 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#14 -> INT#18 */
113 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* GPIO#2 -> GPIO#7 */
114 0x08, 0x09, 0x0a, 0x0b, 0x0c, /* GPIO#8 -> GPIO#12 */
115 0xff, 0xff /* INT#30 -> INT#31 */
116 };
117
118 static __inline uint32_t
119 ixp425_irq2gpio_bit(int irq)
120 {
121 return (1U << int2gpio[irq]);
122 }
123
124 #ifdef DDB
125 #include <ddb/ddb.h>
126
127 DB_SHOW_COMMAND(gpio, db_show_gpio)
128 {
129 static const char *itype[8] = {
130 [GPIO_TYPE_ACT_HIGH] = "act-high",
131 [GPIO_TYPE_ACT_LOW] = "act-low",
132 [GPIO_TYPE_EDG_RISING] = "edge-rising",
133 [GPIO_TYPE_EDG_FALLING] = "edge-falling",
134 [GPIO_TYPE_TRANSITIONAL]= "transitional",
135 [5] = "type-5", [6] = "type-6", [7] = "type-7"
136 };
137 uint32_t gpoutr = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOUTR);
138 uint32_t gpoer = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOER);
139 uint32_t gpinr = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPINR);
140 uint32_t gpit1r = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPIT1R);
141 uint32_t gpit2r = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPIT2R);
142 int i, j;
143
144 db_printf("GPOUTR %08x GPINR %08x GPOER %08x GPISR %08x\n",
145 gpoutr, gpinr, gpoer,
146 GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPISR));
147 db_printf("GPIT1R %08x GPIT2R %08x GPCLKR %08x\n",
148 gpit1r, gpit2r, GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPCLKR));
149 for (i = 0; i < 16; i++) {
150 db_printf("[%2d] out %u in %u %-3s", i,
151 (gpoutr>>i)&1, (gpinr>>i)&1, (gpoer>>i)&1 ? "in" : "out");
152 for (j = 0; j < 32; j++)
153 if (int2gpio[j] == i) {
154 db_printf(" irq %2u %s", j, itype[
155 (((i & 8) ? gpit2r : gpit1r) >> (3*(i&7)))
156 & 7]);
157 break;
158 }
159 db_printf("\n");
160 }
161 }
162 #endif
163
164 void
165 ixp425_set_gpio(struct ixp425_softc *sc, int pin, int type)
166 {
167 uint32_t gpiotr = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(pin));
168
169 IXP4XX_GPIO_LOCK();
170 /* clear interrupt type */
171 GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(pin),
172 gpiotr &~ GPIO_TYPE(pin, GPIO_TYPE_MASK));
173 /* clear any pending interrupt */
174 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR, (1<<pin));
175 /* set new interrupt type */
176 GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(pin),
177 gpiotr | GPIO_TYPE(pin, type));
178
179 /* configure gpio line as an input */
180 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER,
181 GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER) | (1<<pin));
182 IXP4XX_GPIO_UNLOCK();
183 }
184
185 static __inline void
186 ixp425_gpio_ack(int irq)
187 {
188 if (irq < 32 && ((1 << irq) & IXP425_INT_GPIOMASK))
189 IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) =
190 ixp425_irq2gpio_bit(irq);
191 }
192
193 static void
194 ixp425_post_filter(void *arg)
195 {
196 uintptr_t irq = (uintptr_t) arg;
197 ixp425_gpio_ack(irq);
198 }
199
200 void
201 arm_mask_irq(uintptr_t nb)
202 {
203 int i;
204
205 i = disable_interrupts(I32_bit);
206 if (nb < 32) {
207 intr_enabled &= ~(1 << nb);
208 ixp425_set_intrmask();
209 } else {
210 intr_enabled2 &= ~(1 << (nb - 32));
211 ixp435_set_intrmask();
212 }
213 restore_interrupts(i);
214 /*XXX; If it's a GPIO interrupt, ACK it know. Can it be a problem ?*/
215 ixp425_gpio_ack(nb);
216 }
217
218 void
219 arm_unmask_irq(uintptr_t nb)
220 {
221 int i;
222
223 i = disable_interrupts(I32_bit);
224 if (nb < 32) {
225 intr_enabled |= (1 << nb);
226 ixp425_set_intrmask();
227 } else {
228 intr_enabled2 |= (1 << (nb - 32));
229 ixp435_set_intrmask();
230 }
231 restore_interrupts(i);
232 }
233
234 static __inline uint32_t
235 ixp425_irq_read(void)
236 {
237 return IXPREG(IXP425_INT_STATUS) & intr_enabled;
238 }
239
240 static __inline uint32_t
241 ixp435_irq_read(void)
242 {
243 return IXPREG(IXP435_INT_STATUS2) & intr_enabled2;
244 }
245
246 int
247 arm_get_next_irq(int last)
248 {
249 uint32_t mask;
250
251 last += 1; /* always advance fwd, NB: handles -1 */
252 if (last < 32) {
253 mask = ixp425_irq_read() >> last;
254 for (; mask != 0; mask >>= 1, last++) {
255 if (mask & 1)
256 return last;
257 }
258 last = 32;
259 }
260 if (cpu_is_ixp43x()) {
261 mask = ixp435_irq_read() >> (32-last);
262 for (; mask != 0; mask >>= 1, last++) {
263 if (mask & 1)
264 return last;
265 }
266 }
267 return -1;
268 }
269
270 void
271 cpu_reset(void)
272 {
273
274 bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE,
275 IXP425_OST_WDOG_KEY, OST_WDOG_KEY_MAJICK);
276 bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE,
277 IXP425_OST_WDOG, 0);
278 bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE,
279 IXP425_OST_WDOG_ENAB, OST_WDOG_ENAB_RST_ENA |
280 OST_WDOG_ENAB_CNT_ENA);
281 printf("Reset failed!\n");
282 for(;;);
283 }
284
285 static void
286 ixp425_identify(driver_t *driver, device_t parent)
287 {
288 BUS_ADD_CHILD(parent, 0, "ixp", 0);
289 }
290
291 static int
292 ixp425_probe(device_t dev)
293 {
294 device_set_desc(dev, "Intel IXP4XX");
295 return (0);
296 }
297
298 static int
299 ixp425_attach(device_t dev)
300 {
301 struct ixp425_softc *sc;
302
303 device_printf(dev, "%b\n", ixp4xx_read_feature_bits(), EXP_FCTRL_BITS);
304
305 sc = device_get_softc(dev);
306 sc->sc_iot = &ixp425_bs_tag;
307 KASSERT(ixp425_softc == NULL, ("%s called twice?", __func__));
308 ixp425_softc = sc;
309
310 intr_enabled = 0;
311 ixp425_set_intrmask();
312 ixp425_set_intrsteer();
313 if (cpu_is_ixp43x()) {
314 intr_enabled2 = 0;
315 ixp435_set_intrmask();
316 ixp435_set_intrsteer();
317 }
318 arm_post_filter = ixp425_post_filter;
319
320 mtx_init(&ixp425_gpio_mtx, "gpio", NULL, MTX_DEF);
321 if (bus_space_map(sc->sc_iot, IXP425_GPIO_HWBASE, IXP425_GPIO_SIZE,
322 0, &sc->sc_gpio_ioh))
323 panic("%s: unable to map GPIO registers", __func__);
324 if (bus_space_map(sc->sc_iot, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
325 0, &sc->sc_exp_ioh))
326 panic("%s: unable to map Expansion Bus registers", __func__);
327
328 /* XXX belongs in platform init */
329 if (cpu_is_ixp43x())
330 cambria_exp_bus_init(sc);
331
332 if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
333 BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0,
334 NULL, NULL, &sc->sc_dmat))
335 panic("%s: failed to create dma tag", __func__);
336
337 sc->sc_irq_rman.rm_type = RMAN_ARRAY;
338 sc->sc_irq_rman.rm_descr = "IXP4XX IRQs";
339 if (rman_init(&sc->sc_irq_rman) != 0 ||
340 rman_manage_region(&sc->sc_irq_rman, 0, cpu_is_ixp43x() ? 63 : 31) != 0)
341 panic("%s: failed to set up IRQ rman", __func__);
342
343 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
344 sc->sc_mem_rman.rm_descr = "IXP4XX Memory";
345 if (rman_init(&sc->sc_mem_rman) != 0 ||
346 rman_manage_region(&sc->sc_mem_rman, 0, ~0) != 0)
347 panic("%s: failed to set up memory rman", __func__);
348
349 BUS_ADD_CHILD(dev, 0, "pcib", 0);
350 BUS_ADD_CHILD(dev, 0, "ixpclk", 0);
351 BUS_ADD_CHILD(dev, 0, "ixpiic", 0);
352 /* XXX move to hints? */
353 BUS_ADD_CHILD(dev, 0, "ixpwdog", 0);
354
355 /* attach wired devices via hints */
356 bus_enumerate_hinted_children(dev);
357
358 bus_generic_probe(dev);
359 bus_generic_attach(dev);
360
361 return (0);
362 }
363
364 static void
365 ixp425_hinted_child(device_t bus, const char *dname, int dunit)
366 {
367 device_t child;
368 struct ixp425_ivar *ivar;
369
370 child = BUS_ADD_CHILD(bus, 0, dname, dunit);
371 ivar = IXP425_IVAR(child);
372 resource_int_value(dname, dunit, "addr", &ivar->addr);
373 resource_int_value(dname, dunit, "irq", &ivar->irq);
374 }
375
376 static device_t
377 ixp425_add_child(device_t dev, u_int order, const char *name, int unit)
378 {
379 device_t child;
380 struct ixp425_ivar *ivar;
381
382 child = device_add_child_ordered(dev, order, name, unit);
383 if (child == NULL)
384 return NULL;
385 ivar = malloc(sizeof(struct ixp425_ivar), M_DEVBUF, M_NOWAIT);
386 if (ivar == NULL) {
387 device_delete_child(dev, child);
388 return NULL;
389 }
390 ivar->addr = 0;
391 ivar->irq = -1;
392 device_set_ivars(child, ivar);
393 return child;
394 }
395
396 static int
397 ixp425_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
398 {
399 struct ixp425_ivar *ivar = IXP425_IVAR(child);
400
401 switch (which) {
402 case IXP425_IVAR_ADDR:
403 if (ivar->addr != 0) {
404 *(uint32_t *)result = ivar->addr;
405 return 0;
406 }
407 break;
408 case IXP425_IVAR_IRQ:
409 if (ivar->irq != -1) {
410 *(int *)result = ivar->irq;
411 return 0;
412 }
413 break;
414 }
415 return EINVAL;
416 }
417
418 /*
419 * NB: This table handles P->V translations for regions setup with
420 * static mappings in initarm. This is used solely for calls to
421 * bus_alloc_resource_any; anything done with bus_space_map is
422 * handled elsewhere and does not require an entry here.
423 *
424 * XXX this table is also used by uart_cpu_getdev via getvbase
425 * (hence the public api)
426 */
427 struct hwvtrans {
428 uint32_t hwbase;
429 uint32_t size;
430 uint32_t vbase;
431 int isa4x; /* XXX needs special bus space tag */
432 int isslow; /* XXX needs special bus space tag */
433 };
434
435 static const struct hwvtrans *
436 gethwvtrans(uint32_t hwbase, uint32_t size)
437 {
438 static const struct hwvtrans hwvtrans[] = {
439 /* NB: needed only for uart_cpu_getdev */
440 { .hwbase = IXP425_UART0_HWBASE,
441 .size = IXP425_REG_SIZE,
442 .vbase = IXP425_UART0_VBASE,
443 .isa4x = 1 },
444 { .hwbase = IXP425_UART1_HWBASE,
445 .size = IXP425_REG_SIZE,
446 .vbase = IXP425_UART1_VBASE,
447 .isa4x = 1 },
448 { .hwbase = IXP425_PCI_HWBASE,
449 .size = IXP425_PCI_SIZE,
450 .vbase = IXP425_PCI_VBASE },
451 { .hwbase = IXP425_PCI_MEM_HWBASE,
452 .size = IXP425_PCI_MEM_SIZE,
453 .vbase = IXP425_PCI_MEM_VBASE },
454 { .hwbase = IXP425_EXP_BUS_CS0_HWBASE,
455 .size = IXP425_EXP_BUS_CS0_SIZE,
456 .vbase = IXP425_EXP_BUS_CS0_VBASE },
457 /* NB: needed for ixp435 ehci controllers */
458 { .hwbase = IXP435_USB1_HWBASE,
459 .size = IXP435_USB1_SIZE,
460 .vbase = IXP435_USB1_VBASE },
461 { .hwbase = IXP435_USB2_HWBASE,
462 .size = IXP435_USB2_SIZE,
463 .vbase = IXP435_USB2_VBASE },
464 { .hwbase = CAMBRIA_GPS_HWBASE,
465 .size = CAMBRIA_GPS_SIZE,
466 .vbase = CAMBRIA_GPS_VBASE,
467 .isslow = 1 },
468 { .hwbase = CAMBRIA_RS485_HWBASE,
469 .size = CAMBRIA_RS485_SIZE,
470 .vbase = CAMBRIA_RS485_VBASE,
471 .isslow = 1 },
472 };
473 int i;
474
475 for (i = 0; i < sizeof hwvtrans / sizeof *hwvtrans; i++) {
476 if (hwbase >= hwvtrans[i].hwbase &&
477 hwbase + size <= hwvtrans[i].hwbase + hwvtrans[i].size)
478 return &hwvtrans[i];
479 }
480 return NULL;
481 }
482
483 /* XXX for uart_cpu_getdev */
484 int
485 getvbase(uint32_t hwbase, uint32_t size, uint32_t *vbase)
486 {
487 const struct hwvtrans *hw;
488
489 hw = gethwvtrans(hwbase, size);
490 if (hw == NULL)
491 return (ENOENT);
492 *vbase = hwbase - hw->hwbase + hw->vbase;
493 return (0);
494 }
495
496 static struct resource *
497 ixp425_alloc_resource(device_t dev, device_t child, int type, int *rid,
498 u_long start, u_long end, u_long count, u_int flags)
499 {
500 struct ixp425_softc *sc = device_get_softc(dev);
501 const struct hwvtrans *vtrans;
502 struct resource *rv;
503 uint32_t addr;
504 int needactivate = flags & RF_ACTIVE;
505 int irq;
506
507 flags &= ~RF_ACTIVE;
508 switch (type) {
509 case SYS_RES_IRQ:
510 /* override per hints */
511 if (BUS_READ_IVAR(dev, child, IXP425_IVAR_IRQ, &irq) == 0)
512 start = end = irq;
513 rv = rman_reserve_resource(&sc->sc_irq_rman, start, end, count,
514 flags, child);
515 if (rv != NULL)
516 rman_set_rid(rv, *rid);
517 break;
518
519 case SYS_RES_MEMORY:
520 /* override per hints */
521 if (BUS_READ_IVAR(dev, child, IXP425_IVAR_ADDR, &addr) == 0) {
522 start = addr;
523 /* XXX use nominal window to check for mapping */
524 vtrans = gethwvtrans(start, 0x1000);
525 if (vtrans != NULL) {
526 /*
527 * Assign the entire mapped region; this may
528 * not be correct but without more info from
529 * the caller we cannot tell.
530 */
531 end = start + vtrans->size -
532 (start - vtrans->hwbase);
533 if (bootverbose)
534 device_printf(child,
535 "%s: assign 0x%lx:0x%lx%s\n",
536 __func__, start, end - start,
537 vtrans->isa4x ? " A4X" :
538 vtrans->isslow ? " SLOW" : "");
539 }
540 } else
541 vtrans = gethwvtrans(start, end - start);
542 if (vtrans == NULL) {
543 /* likely means above table needs to be updated */
544 device_printf(child, "%s: no mapping for 0x%lx:0x%lx\n",
545 __func__, start, end - start);
546 return NULL;
547 }
548 rv = rman_reserve_resource(&sc->sc_mem_rman, start, end,
549 end - start, flags, child);
550 if (rv == NULL) {
551 device_printf(child, "%s: cannot reserve 0x%lx:0x%lx\n",
552 __func__, start, end - start);
553 return NULL;
554 }
555 rman_set_rid(rv, *rid);
556 break;
557 default:
558 rv = NULL;
559 break;
560 }
561 if (rv != NULL && needactivate) {
562 if (bus_activate_resource(child, type, *rid, rv)) {
563 rman_release_resource(rv);
564 return (NULL);
565 }
566 }
567 return (rv);
568 }
569
570 static int
571 ixp425_release_resource(device_t bus, device_t child, int type, int rid,
572 struct resource *r)
573 {
574 /* NB: no private resources, just release */
575 return rman_release_resource(r);
576 }
577
578 static int
579 ixp425_activate_resource(device_t dev, device_t child, int type, int rid,
580 struct resource *r)
581 {
582 struct ixp425_softc *sc = device_get_softc(dev);
583 const struct hwvtrans *vtrans;
584
585 if (type == SYS_RES_MEMORY) {
586 vtrans = gethwvtrans(rman_get_start(r), rman_get_size(r));
587 if (vtrans == NULL) { /* NB: should not happen */
588 device_printf(child, "%s: no mapping for 0x%lx:0x%lx\n",
589 __func__, rman_get_start(r), rman_get_size(r));
590 return (ENOENT);
591 }
592 if (vtrans->isa4x)
593 rman_set_bustag(r, &ixp425_a4x_bs_tag);
594 else if (vtrans->isslow)
595 rman_set_bustag(r, &cambria_exp_bs_tag);
596 else
597 rman_set_bustag(r, sc->sc_iot);
598 rman_set_bushandle(r, vtrans->vbase);
599 }
600 return (rman_activate_resource(r));
601 }
602
603 static int
604 ixp425_deactivate_resource(device_t bus, device_t child, int type, int rid,
605 struct resource *r)
606 {
607 /* NB: no private resources, just deactive */
608 return (rman_deactivate_resource(r));
609 }
610
611 static __inline void
612 get_masks(struct resource *res, uint32_t *mask, uint32_t *mask2)
613 {
614 int i;
615
616 *mask = 0;
617 for (i = rman_get_start(res); i < 32 && i <= rman_get_end(res); i++)
618 *mask |= 1 << i;
619 *mask2 = 0;
620 for (; i <= rman_get_end(res); i++)
621 *mask2 |= 1 << (i - 32);
622 }
623
624 static __inline void
625 update_masks(uint32_t mask, uint32_t mask2)
626 {
627
628 intr_enabled = mask;
629 ixp425_set_intrmask();
630 if (cpu_is_ixp43x()) {
631 intr_enabled2 = mask2;
632 ixp435_set_intrmask();
633 }
634 }
635
636 static int
637 ixp425_setup_intr(device_t dev, device_t child,
638 struct resource *res, int flags, driver_filter_t *filt,
639 driver_intr_t *intr, void *arg, void **cookiep)
640 {
641 uint32_t mask, mask2;
642
643 BUS_SETUP_INTR(device_get_parent(dev), child, res, flags, filt, intr,
644 arg, cookiep);
645
646 get_masks(res, &mask, &mask2);
647 update_masks(intr_enabled | mask, intr_enabled2 | mask2);
648
649 return (0);
650 }
651
652 static int
653 ixp425_teardown_intr(device_t dev, device_t child, struct resource *res,
654 void *cookie)
655 {
656 uint32_t mask, mask2;
657
658 get_masks(res, &mask, &mask2);
659 update_masks(intr_enabled &~ mask, intr_enabled2 &~ mask2);
660
661 return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
662 }
663
664 static device_method_t ixp425_methods[] = {
665 /* Device interface */
666 DEVMETHOD(device_probe, ixp425_probe),
667 DEVMETHOD(device_attach, ixp425_attach),
668 DEVMETHOD(device_identify, ixp425_identify),
669
670 /* Bus interface */
671 DEVMETHOD(bus_add_child, ixp425_add_child),
672 DEVMETHOD(bus_hinted_child, ixp425_hinted_child),
673 DEVMETHOD(bus_read_ivar, ixp425_read_ivar),
674
675 DEVMETHOD(bus_alloc_resource, ixp425_alloc_resource),
676 DEVMETHOD(bus_release_resource, ixp425_release_resource),
677 DEVMETHOD(bus_activate_resource, ixp425_activate_resource),
678 DEVMETHOD(bus_deactivate_resource, ixp425_deactivate_resource),
679 DEVMETHOD(bus_setup_intr, ixp425_setup_intr),
680 DEVMETHOD(bus_teardown_intr, ixp425_teardown_intr),
681
682 {0, 0},
683 };
684
685 static driver_t ixp425_driver = {
686 "ixp",
687 ixp425_methods,
688 sizeof(struct ixp425_softc),
689 };
690 static devclass_t ixp425_devclass;
691
692 DRIVER_MODULE(ixp, nexus, ixp425_driver, ixp425_devclass, 0, 0);
Cache object: e3ad467f1e7c658cc31a89fc94795df3
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