Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/xscale/ixp425/ixp425_pci.c
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1 /* $NetBSD: ixp425_pci.c,v 1.5 2006/04/10 03:36:03 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro@ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD: releng/10.1/sys/arm/xscale/ixp425/ixp425_pci.c 259329 2013-12-13 20:43:11Z ian $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 #define _ARM32_BUS_DMA_PRIVATE 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/rman.h> 47 48 #include <dev/pci/pcivar.h> 49 50 #include <machine/bus.h> 51 #include <machine/cpu.h> 52 #include <machine/pcb.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 #include <vm/vm_extern.h> 57 58 #include <arm/xscale/ixp425/ixp425reg.h> 59 #include <arm/xscale/ixp425/ixp425var.h> 60 61 #include <dev/pci/pcib_private.h> 62 #include "pcib_if.h" 63 64 #include <dev/pci/pcireg.h> 65 extern struct ixp425_softc *ixp425_softc; 66 67 #define PCI_CSR_WRITE_4(sc, reg, data) \ 68 bus_write_4(sc->sc_csr, reg, data) 69 70 #define PCI_CSR_READ_4(sc, reg) \ 71 bus_read_4(sc->sc_csr, reg) 72 73 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 74 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 75 76 static device_probe_t ixppcib_probe; 77 static device_attach_t ixppcib_attach; 78 static bus_read_ivar_t ixppcib_read_ivar; 79 static bus_write_ivar_t ixppcib_write_ivar; 80 static bus_setup_intr_t ixppcib_setup_intr; 81 static bus_teardown_intr_t ixppcib_teardown_intr; 82 static bus_alloc_resource_t ixppcib_alloc_resource; 83 static bus_activate_resource_t ixppcib_activate_resource; 84 static bus_deactivate_resource_t ixppcib_deactivate_resource; 85 static bus_release_resource_t ixppcib_release_resource; 86 static pcib_maxslots_t ixppcib_maxslots; 87 static pcib_read_config_t ixppcib_read_config; 88 static pcib_write_config_t ixppcib_write_config; 89 static pcib_route_interrupt_t ixppcib_route_interrupt; 90 91 static int 92 ixppcib_probe(device_t dev) 93 { 94 device_set_desc(dev, "IXP4XX PCI Bus"); 95 return (0); 96 } 97 98 static void 99 ixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg, 100 uint32_t data) 101 { 102 PCI_CSR_WRITE_4(sc, PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE)); 103 PCI_CSR_WRITE_4(sc, PCI_CRP_AD_WDATA, data); 104 } 105 106 static int 107 ixppcib_attach(device_t dev) 108 { 109 int rid; 110 struct ixppcib_softc *sc; 111 112 sc = device_get_softc(dev); 113 114 rid = 0; 115 sc->sc_csr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 116 IXP425_PCI_HWBASE, IXP425_PCI_HWBASE + IXP425_PCI_SIZE, 117 IXP425_PCI_SIZE, RF_ACTIVE); 118 if (sc->sc_csr == NULL) 119 panic("cannot allocate PCI CSR registers"); 120 121 ixp425_md_attach(dev); 122 /* always setup the base, incase another OS messes w/ it */ 123 PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b); 124 125 rid = 0; 126 sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 127 IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE, 128 IXP425_PCI_MEM_SIZE, RF_ACTIVE); 129 if (sc->sc_mem == NULL) 130 panic("cannot allocate PCI MEM space"); 131 132 /* NB: PCI dma window is 64M so anything above must be bounced */ 133 if (bus_dma_tag_create(NULL, 1, 0, IXP425_AHB_OFFSET + 64 * 1024 * 1024, 134 BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0, 135 NULL, NULL, &sc->sc_dmat)) 136 panic("couldn't create the PCI dma tag !"); 137 /* 138 * The PCI bus can only address 64MB. However, due to the way our 139 * implementation of busdma works, busdma can't tell if a device 140 * is a PCI device or not. So defaults to the PCI dma tag, which 141 * restrict the DMA'able memory to the first 64MB, and explicitely 142 * create less restrictive tags for non-PCI devices. 143 */ 144 arm_root_dma_tag = sc->sc_dmat; 145 /* 146 * Initialize the bus space tags. 147 */ 148 ixp425_io_bs_init(&sc->sc_pci_iot, sc); 149 ixp425_mem_bs_init(&sc->sc_pci_memt, sc); 150 151 sc->sc_dev = dev; 152 153 /* Initialize memory and i/o rmans. */ 154 sc->sc_io_rman.rm_type = RMAN_ARRAY; 155 sc->sc_io_rman.rm_descr = "IXP4XX PCI I/O Ports"; 156 if (rman_init(&sc->sc_io_rman) != 0 || 157 rman_manage_region(&sc->sc_io_rman, 0, 158 IXP425_PCI_IO_SIZE) != 0) { 159 panic("ixppcib_probe: failed to set up I/O rman"); 160 } 161 162 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 163 sc->sc_mem_rman.rm_descr = "IXP4XX PCI Memory"; 164 if (rman_init(&sc->sc_mem_rman) != 0 || 165 rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE, 166 IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) { 167 panic("ixppcib_probe: failed to set up memory rman"); 168 } 169 170 /* 171 * PCI->AHB address translation 172 * begin at the physical memory start + OFFSET 173 */ 174 PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, 175 (IXP425_AHB_OFFSET & 0xFF000000) + 176 ((IXP425_AHB_OFFSET & 0xFF000000) >> 8) + 177 ((IXP425_AHB_OFFSET & 0xFF000000) >> 16) + 178 ((IXP425_AHB_OFFSET & 0xFF000000) >> 24) + 179 0x00010203); 180 181 #define IXPPCIB_WRITE_CONF(sc, reg, val) \ 182 ixp425_pci_conf_reg_write(sc, reg, val) 183 /* Write Mapping registers PCI Configuration Registers */ 184 /* Base Address 0 - 3 */ 185 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, IXP425_AHB_OFFSET + 0x00000000); 186 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, IXP425_AHB_OFFSET + 0x01000000); 187 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, IXP425_AHB_OFFSET + 0x02000000); 188 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, IXP425_AHB_OFFSET + 0x03000000); 189 190 /* Base Address 4 */ 191 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff); 192 193 /* Base Address 5 */ 194 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000); 195 196 /* Assert some PCI errors */ 197 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE); 198 199 #ifdef __ARMEB__ 200 /* 201 * Set up byte lane swapping between little-endian PCI 202 * and the big-endian AHB bus 203 */ 204 PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS); 205 #else 206 PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE); 207 #endif 208 209 /* 210 * Enable bus mastering and I/O,memory access 211 */ 212 IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND, 213 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 214 215 /* 216 * Wait some more to ensure PCI devices have stabilised. 217 */ 218 DELAY(50000); 219 220 device_add_child(dev, "pci", -1); 221 return (bus_generic_attach(dev)); 222 } 223 224 static int 225 ixppcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 226 { 227 struct ixppcib_softc *sc; 228 229 sc = device_get_softc(dev); 230 switch (which) { 231 case PCIB_IVAR_DOMAIN: 232 *result = 0; 233 return (0); 234 case PCIB_IVAR_BUS: 235 *result = sc->sc_bus; 236 return (0); 237 } 238 239 return (ENOENT); 240 } 241 242 static int 243 ixppcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 244 { 245 struct ixppcib_softc *sc; 246 247 sc = device_get_softc(dev); 248 switch (which) { 249 case PCIB_IVAR_DOMAIN: 250 return (EINVAL); 251 case PCIB_IVAR_BUS: 252 sc->sc_bus = value; 253 return (0); 254 } 255 256 return (ENOENT); 257 } 258 259 static int 260 ixppcib_setup_intr(device_t dev, device_t child, struct resource *ires, 261 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 262 void **cookiep) 263 { 264 265 return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 266 filt, intr, arg, cookiep)); 267 } 268 269 static int 270 ixppcib_teardown_intr(device_t dev, device_t child, struct resource *vec, 271 void *cookie) 272 { 273 274 return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, cookie)); 275 } 276 277 static struct resource * 278 ixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid, 279 u_long start, u_long end, u_long count, u_int flags) 280 { 281 struct ixppcib_softc *sc = device_get_softc(bus); 282 struct rman *rmanp; 283 struct resource *rv; 284 285 rv = NULL; 286 switch (type) { 287 case SYS_RES_IRQ: 288 rmanp = &sc->sc_irq_rman; 289 break; 290 291 case SYS_RES_IOPORT: 292 rmanp = &sc->sc_io_rman; 293 break; 294 295 case SYS_RES_MEMORY: 296 rmanp = &sc->sc_mem_rman; 297 break; 298 299 default: 300 return (rv); 301 } 302 303 rv = rman_reserve_resource(rmanp, start, end, count, flags & ~RF_ACTIVE, 304 child); 305 if (rv == NULL) 306 return (NULL); 307 rman_set_rid(rv, *rid); 308 if (flags & RF_ACTIVE) { 309 if (bus_activate_resource(child, type, *rid, rv)) { 310 rman_release_resource(rv); 311 return (NULL); 312 } 313 } 314 315 return (rv); 316 } 317 318 static int 319 ixppcib_activate_resource(device_t bus, device_t child, int type, int rid, 320 struct resource *r) 321 { 322 323 struct ixppcib_softc *sc = device_get_softc(bus); 324 325 switch (type) { 326 case SYS_RES_IOPORT: 327 rman_set_bustag(r, &sc->sc_pci_iot); 328 rman_set_bushandle(r, rman_get_start(r)); 329 break; 330 case SYS_RES_MEMORY: 331 rman_set_bustag(r, &sc->sc_pci_memt); 332 rman_set_bushandle(r, rman_get_bushandle(sc->sc_mem) + 333 (rman_get_start(r) - IXP425_PCI_MEM_HWBASE)); 334 break; 335 } 336 337 return (rman_activate_resource(r)); 338 } 339 340 static int 341 ixppcib_deactivate_resource(device_t bus, device_t child, int type, int rid, 342 struct resource *r) 343 { 344 345 device_printf(bus, "%s called deactivate_resource (unexpected)\n", 346 device_get_nameunit(child)); 347 return (ENXIO); 348 } 349 350 static int 351 ixppcib_release_resource(device_t bus, device_t child, int type, int rid, 352 struct resource *r) 353 { 354 355 device_printf(bus, "%s called release_resource (unexpected)\n", 356 device_get_nameunit(child)); 357 return (ENXIO); 358 } 359 360 static void 361 ixppcib_conf_setup(struct ixppcib_softc *sc, int bus, int slot, int func, 362 int reg) 363 { 364 if (bus == 0) { 365 /* configuration type 0 */ 366 PCI_CSR_WRITE_4(sc, PCI_NP_AD, 367 (1U << (32 - (slot & 0x1f))) | 368 ((func & 0x7) << 8) | (reg & ~3)); 369 } else { 370 /* configuration type 1 */ 371 PCI_CSR_WRITE_4(sc, PCI_NP_AD, 372 (bus << 16) | (slot << 11) | 373 (func << 8) | (reg & ~3) | 1); 374 } 375 376 } 377 378 static int 379 ixppcib_maxslots(device_t dev) 380 { 381 382 return (PCI_SLOTMAX); 383 } 384 385 static u_int32_t 386 ixppcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 387 int bytes) 388 { 389 struct ixppcib_softc *sc = device_get_softc(dev); 390 u_int32_t data, ret; 391 392 ixppcib_conf_setup(sc, bus, slot, func, reg & ~3); 393 394 PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ); 395 ret = PCI_CSR_READ_4(sc, PCI_NP_RDATA); 396 ret >>= (reg & 3) * 8; 397 ret &= 0xffffffff >> ((4 - bytes) * 8); 398 #if 0 399 device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n", 400 __func__, bus, slot, func, reg, bytes, ret); 401 #endif 402 /* check & clear PCI abort */ 403 data = PCI_CSR_READ_4(sc, PCI_ISR); 404 if (data & ISR_PFE) { 405 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE); 406 return (-1); 407 } 408 return (ret); 409 } 410 411 static const int byteenables[] = { 0, 0x10, 0x30, 0x70, 0xf0 }; 412 413 static void 414 ixppcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 415 u_int32_t val, int bytes) 416 { 417 struct ixppcib_softc *sc = device_get_softc(dev); 418 u_int32_t data; 419 420 #if 0 421 device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n", 422 __func__, bus, slot, func, reg, bytes, val); 423 #endif 424 ixppcib_conf_setup(sc, bus, slot, func, reg & ~3); 425 426 /* Byte enables are active low, so not them first */ 427 PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE | 428 (~(byteenables[bytes] << (reg & 3)) & 0xf0)); 429 PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val << ((reg & 3) * 8)); 430 431 /* check & clear PCI abort */ 432 data = PCI_CSR_READ_4(sc, PCI_ISR); 433 if (data & ISR_PFE) 434 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE); 435 } 436 437 static int 438 ixppcib_route_interrupt(device_t bridge, device_t device, int pin) 439 { 440 441 return (ixp425_md_route_interrupt(bridge, device, pin)); 442 } 443 444 static device_method_t ixppcib_methods[] = { 445 /* Device interface */ 446 DEVMETHOD(device_probe, ixppcib_probe), 447 DEVMETHOD(device_attach, ixppcib_attach), 448 449 /* Bus interface */ 450 DEVMETHOD(bus_read_ivar, ixppcib_read_ivar), 451 DEVMETHOD(bus_write_ivar, ixppcib_write_ivar), 452 DEVMETHOD(bus_setup_intr, ixppcib_setup_intr), 453 DEVMETHOD(bus_teardown_intr, ixppcib_teardown_intr), 454 DEVMETHOD(bus_alloc_resource, ixppcib_alloc_resource), 455 DEVMETHOD(bus_activate_resource, ixppcib_activate_resource), 456 DEVMETHOD(bus_deactivate_resource, ixppcib_deactivate_resource), 457 DEVMETHOD(bus_release_resource, ixppcib_release_resource), 458 /* DEVMETHOD(bus_get_dma_tag, ixppcib_get_dma_tag), */ 459 460 /* pcib interface */ 461 DEVMETHOD(pcib_maxslots, ixppcib_maxslots), 462 DEVMETHOD(pcib_read_config, ixppcib_read_config), 463 DEVMETHOD(pcib_write_config, ixppcib_write_config), 464 DEVMETHOD(pcib_route_interrupt, ixppcib_route_interrupt), 465 466 DEVMETHOD_END 467 }; 468 469 static driver_t ixppcib_driver = { 470 "pcib", 471 ixppcib_methods, 472 sizeof(struct ixppcib_softc), 473 }; 474 static devclass_t ixppcib_devclass; 475 476 DRIVER_MODULE(ixppcib, ixp, ixppcib_driver, ixppcib_devclass, 0, 0);
Cache object: 7d800db98eacde7bd993002d461a721b
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