Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/xscale/ixp425/ixp425_pci.c
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1 /* $NetBSD: ixp425_pci.c,v 1.5 2006/04/10 03:36:03 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro@ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 #define _ARM32_BUS_DMA_PRIVATE 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/rman.h> 47 48 #include <dev/pci/pcivar.h> 49 50 #include <machine/armreg.h> 51 #include <machine/bus.h> 52 #include <machine/cpu.h> 53 #include <machine/pcb.h> 54 55 #include <vm/vm.h> 56 #include <vm/pmap.h> 57 #include <vm/vm_extern.h> 58 59 #include <arm/xscale/ixp425/ixp425reg.h> 60 #include <arm/xscale/ixp425/ixp425var.h> 61 62 #include <dev/pci/pcib_private.h> 63 #include "pcib_if.h" 64 65 #include <dev/pci/pcireg.h> 66 extern struct ixp425_softc *ixp425_softc; 67 68 #define PCI_CSR_WRITE_4(sc, reg, data) \ 69 bus_write_4(sc->sc_csr, reg, data) 70 71 #define PCI_CSR_READ_4(sc, reg) \ 72 bus_read_4(sc->sc_csr, reg) 73 74 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(PSR_I) 75 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 76 77 static device_probe_t ixppcib_probe; 78 static device_attach_t ixppcib_attach; 79 static bus_read_ivar_t ixppcib_read_ivar; 80 static bus_write_ivar_t ixppcib_write_ivar; 81 static bus_setup_intr_t ixppcib_setup_intr; 82 static bus_teardown_intr_t ixppcib_teardown_intr; 83 static bus_alloc_resource_t ixppcib_alloc_resource; 84 static bus_activate_resource_t ixppcib_activate_resource; 85 static bus_deactivate_resource_t ixppcib_deactivate_resource; 86 static bus_release_resource_t ixppcib_release_resource; 87 static pcib_maxslots_t ixppcib_maxslots; 88 static pcib_read_config_t ixppcib_read_config; 89 static pcib_write_config_t ixppcib_write_config; 90 static pcib_route_interrupt_t ixppcib_route_interrupt; 91 92 static int 93 ixppcib_probe(device_t dev) 94 { 95 device_set_desc(dev, "IXP4XX PCI Bus"); 96 return (0); 97 } 98 99 static void 100 ixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg, 101 uint32_t data) 102 { 103 PCI_CSR_WRITE_4(sc, PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE)); 104 PCI_CSR_WRITE_4(sc, PCI_CRP_AD_WDATA, data); 105 } 106 107 static int 108 ixppcib_attach(device_t dev) 109 { 110 int rid; 111 struct ixppcib_softc *sc; 112 113 sc = device_get_softc(dev); 114 115 rid = 0; 116 sc->sc_csr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 117 IXP425_PCI_HWBASE, IXP425_PCI_HWBASE + IXP425_PCI_SIZE, 118 IXP425_PCI_SIZE, RF_ACTIVE); 119 if (sc->sc_csr == NULL) 120 panic("cannot allocate PCI CSR registers"); 121 122 ixp425_md_attach(dev); 123 /* always setup the base, incase another OS messes w/ it */ 124 PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b); 125 126 rid = 0; 127 sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 128 IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE, 129 IXP425_PCI_MEM_SIZE, RF_ACTIVE); 130 if (sc->sc_mem == NULL) 131 panic("cannot allocate PCI MEM space"); 132 133 /* NB: PCI dma window is 64M so anything above must be bounced */ 134 if (bus_dma_tag_create(NULL, 1, 0, IXP425_AHB_OFFSET + 64 * 1024 * 1024, 135 BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0, 136 NULL, NULL, &sc->sc_dmat)) 137 panic("couldn't create the PCI dma tag !"); 138 /* 139 * Initialize the bus space tags. 140 */ 141 ixp425_io_bs_init(&sc->sc_pci_iot, sc); 142 ixp425_mem_bs_init(&sc->sc_pci_memt, sc); 143 144 sc->sc_dev = dev; 145 146 /* Initialize memory and i/o rmans. */ 147 sc->sc_io_rman.rm_type = RMAN_ARRAY; 148 sc->sc_io_rman.rm_descr = "IXP4XX PCI I/O Ports"; 149 if (rman_init(&sc->sc_io_rman) != 0 || 150 rman_manage_region(&sc->sc_io_rman, 0, 151 IXP425_PCI_IO_SIZE) != 0) { 152 panic("ixppcib_probe: failed to set up I/O rman"); 153 } 154 155 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 156 sc->sc_mem_rman.rm_descr = "IXP4XX PCI Memory"; 157 if (rman_init(&sc->sc_mem_rman) != 0 || 158 rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE, 159 IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) { 160 panic("ixppcib_probe: failed to set up memory rman"); 161 } 162 163 /* 164 * PCI->AHB address translation 165 * begin at the physical memory start + OFFSET 166 */ 167 PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, 168 (IXP425_AHB_OFFSET & 0xFF000000) + 169 ((IXP425_AHB_OFFSET & 0xFF000000) >> 8) + 170 ((IXP425_AHB_OFFSET & 0xFF000000) >> 16) + 171 ((IXP425_AHB_OFFSET & 0xFF000000) >> 24) + 172 0x00010203); 173 174 #define IXPPCIB_WRITE_CONF(sc, reg, val) \ 175 ixp425_pci_conf_reg_write(sc, reg, val) 176 /* Write Mapping registers PCI Configuration Registers */ 177 /* Base Address 0 - 3 */ 178 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, IXP425_AHB_OFFSET + 0x00000000); 179 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, IXP425_AHB_OFFSET + 0x01000000); 180 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, IXP425_AHB_OFFSET + 0x02000000); 181 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, IXP425_AHB_OFFSET + 0x03000000); 182 183 /* Base Address 4 */ 184 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff); 185 186 /* Base Address 5 */ 187 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000); 188 189 /* Assert some PCI errors */ 190 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE); 191 192 #ifdef __ARMEB__ 193 /* 194 * Set up byte lane swapping between little-endian PCI 195 * and the big-endian AHB bus 196 */ 197 PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS); 198 #else 199 PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE); 200 #endif 201 202 /* 203 * Enable bus mastering and I/O,memory access 204 */ 205 IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND, 206 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 207 208 /* 209 * Wait some more to ensure PCI devices have stabilised. 210 */ 211 DELAY(50000); 212 213 device_add_child(dev, "pci", -1); 214 return (bus_generic_attach(dev)); 215 } 216 217 static int 218 ixppcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 219 { 220 struct ixppcib_softc *sc; 221 222 sc = device_get_softc(dev); 223 switch (which) { 224 case PCIB_IVAR_DOMAIN: 225 *result = 0; 226 return (0); 227 case PCIB_IVAR_BUS: 228 *result = sc->sc_bus; 229 return (0); 230 } 231 232 return (ENOENT); 233 } 234 235 static int 236 ixppcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 237 { 238 struct ixppcib_softc *sc; 239 240 sc = device_get_softc(dev); 241 switch (which) { 242 case PCIB_IVAR_DOMAIN: 243 return (EINVAL); 244 case PCIB_IVAR_BUS: 245 sc->sc_bus = value; 246 return (0); 247 } 248 249 return (ENOENT); 250 } 251 252 static int 253 ixppcib_setup_intr(device_t dev, device_t child, struct resource *ires, 254 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 255 void **cookiep) 256 { 257 258 return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 259 filt, intr, arg, cookiep)); 260 } 261 262 static int 263 ixppcib_teardown_intr(device_t dev, device_t child, struct resource *vec, 264 void *cookie) 265 { 266 267 return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, cookie)); 268 } 269 270 static struct resource * 271 ixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid, 272 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 273 { 274 struct ixppcib_softc *sc = device_get_softc(bus); 275 struct rman *rmanp; 276 struct resource *rv; 277 278 rv = NULL; 279 switch (type) { 280 case SYS_RES_IRQ: 281 rmanp = &sc->sc_irq_rman; 282 break; 283 284 case SYS_RES_IOPORT: 285 rmanp = &sc->sc_io_rman; 286 break; 287 288 case SYS_RES_MEMORY: 289 rmanp = &sc->sc_mem_rman; 290 break; 291 292 default: 293 return (rv); 294 } 295 296 rv = rman_reserve_resource(rmanp, start, end, count, flags & ~RF_ACTIVE, 297 child); 298 if (rv == NULL) 299 return (NULL); 300 rman_set_rid(rv, *rid); 301 if (flags & RF_ACTIVE) { 302 if (bus_activate_resource(child, type, *rid, rv)) { 303 rman_release_resource(rv); 304 return (NULL); 305 } 306 } 307 308 return (rv); 309 } 310 311 static int 312 ixppcib_activate_resource(device_t bus, device_t child, int type, int rid, 313 struct resource *r) 314 { 315 struct ixppcib_softc *sc = device_get_softc(bus); 316 int error; 317 318 error = rman_activate_resource(r); 319 if (error) 320 return (error); 321 switch (type) { 322 case SYS_RES_IOPORT: 323 rman_set_bustag(r, &sc->sc_pci_iot); 324 rman_set_bushandle(r, rman_get_start(r)); 325 break; 326 case SYS_RES_MEMORY: 327 rman_set_bustag(r, &sc->sc_pci_memt); 328 rman_set_bushandle(r, rman_get_bushandle(sc->sc_mem) + 329 (rman_get_start(r) - IXP425_PCI_MEM_HWBASE)); 330 break; 331 } 332 333 return (0); 334 } 335 336 static int 337 ixppcib_deactivate_resource(device_t bus, device_t child, int type, int rid, 338 struct resource *r) 339 { 340 341 device_printf(bus, "%s called deactivate_resource (unexpected)\n", 342 device_get_nameunit(child)); 343 return (ENXIO); 344 } 345 346 static int 347 ixppcib_release_resource(device_t bus, device_t child, int type, int rid, 348 struct resource *r) 349 { 350 351 device_printf(bus, "%s called release_resource (unexpected)\n", 352 device_get_nameunit(child)); 353 return (ENXIO); 354 } 355 356 static bus_dma_tag_t 357 ixppcib_get_dma_tag(device_t bus, device_t child) 358 { 359 struct ixppcib_softc *sc = device_get_softc(bus); 360 361 return (sc->sc_dmat); 362 } 363 364 static void 365 ixppcib_conf_setup(struct ixppcib_softc *sc, int bus, int slot, int func, 366 int reg) 367 { 368 if (bus == 0) { 369 /* configuration type 0 */ 370 PCI_CSR_WRITE_4(sc, PCI_NP_AD, 371 (1U << (32 - (slot & 0x1f))) | 372 ((func & 0x7) << 8) | (reg & ~3)); 373 } else { 374 /* configuration type 1 */ 375 PCI_CSR_WRITE_4(sc, PCI_NP_AD, 376 (bus << 16) | (slot << 11) | 377 (func << 8) | (reg & ~3) | 1); 378 } 379 380 } 381 382 static int 383 ixppcib_maxslots(device_t dev) 384 { 385 386 return (PCI_SLOTMAX); 387 } 388 389 static u_int32_t 390 ixppcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 391 int bytes) 392 { 393 struct ixppcib_softc *sc = device_get_softc(dev); 394 u_int32_t data, ret; 395 396 ixppcib_conf_setup(sc, bus, slot, func, reg & ~3); 397 398 PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ); 399 ret = PCI_CSR_READ_4(sc, PCI_NP_RDATA); 400 ret >>= (reg & 3) * 8; 401 ret &= 0xffffffff >> ((4 - bytes) * 8); 402 #if 0 403 device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n", 404 __func__, bus, slot, func, reg, bytes, ret); 405 #endif 406 /* check & clear PCI abort */ 407 data = PCI_CSR_READ_4(sc, PCI_ISR); 408 if (data & ISR_PFE) { 409 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE); 410 return (-1); 411 } 412 return (ret); 413 } 414 415 static const int byteenables[] = { 0, 0x10, 0x30, 0x70, 0xf0 }; 416 417 static void 418 ixppcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 419 u_int32_t val, int bytes) 420 { 421 struct ixppcib_softc *sc = device_get_softc(dev); 422 u_int32_t data; 423 424 #if 0 425 device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n", 426 __func__, bus, slot, func, reg, bytes, val); 427 #endif 428 ixppcib_conf_setup(sc, bus, slot, func, reg & ~3); 429 430 /* Byte enables are active low, so not them first */ 431 PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE | 432 (~(byteenables[bytes] << (reg & 3)) & 0xf0)); 433 PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val << ((reg & 3) * 8)); 434 435 /* check & clear PCI abort */ 436 data = PCI_CSR_READ_4(sc, PCI_ISR); 437 if (data & ISR_PFE) 438 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE); 439 } 440 441 static int 442 ixppcib_route_interrupt(device_t bridge, device_t device, int pin) 443 { 444 445 return (ixp425_md_route_interrupt(bridge, device, pin)); 446 } 447 448 static device_method_t ixppcib_methods[] = { 449 /* Device interface */ 450 DEVMETHOD(device_probe, ixppcib_probe), 451 DEVMETHOD(device_attach, ixppcib_attach), 452 453 /* Bus interface */ 454 DEVMETHOD(bus_read_ivar, ixppcib_read_ivar), 455 DEVMETHOD(bus_write_ivar, ixppcib_write_ivar), 456 DEVMETHOD(bus_setup_intr, ixppcib_setup_intr), 457 DEVMETHOD(bus_teardown_intr, ixppcib_teardown_intr), 458 DEVMETHOD(bus_alloc_resource, ixppcib_alloc_resource), 459 DEVMETHOD(bus_activate_resource, ixppcib_activate_resource), 460 DEVMETHOD(bus_deactivate_resource, ixppcib_deactivate_resource), 461 DEVMETHOD(bus_release_resource, ixppcib_release_resource), 462 DEVMETHOD(bus_get_dma_tag, ixppcib_get_dma_tag), 463 464 /* pcib interface */ 465 DEVMETHOD(pcib_maxslots, ixppcib_maxslots), 466 DEVMETHOD(pcib_read_config, ixppcib_read_config), 467 DEVMETHOD(pcib_write_config, ixppcib_write_config), 468 DEVMETHOD(pcib_route_interrupt, ixppcib_route_interrupt), 469 470 DEVMETHOD_END 471 }; 472 473 static driver_t ixppcib_driver = { 474 "pcib", 475 ixppcib_methods, 476 sizeof(struct ixppcib_softc), 477 }; 478 static devclass_t ixppcib_devclass; 479 480 DRIVER_MODULE(ixppcib, ixp, ixppcib_driver, ixppcib_devclass, 0, 0);
Cache object: 105765bdebf3bc0f0a486e053f743ecf
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