1 /* $NetBSD: ixp425_pci.c,v 1.5 2006/04/10 03:36:03 simonb Exp $ */
2
3 /*
4 * Copyright (c) 2003
5 * Ichiro FUKUHARA <ichiro@ichiro.org>.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Ichiro FUKUHARA.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD: releng/6.4/sys/arm/xscale/ixp425/ixp425_pci.c 167038 2007-02-26 23:13:09Z cognet $");
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/malloc.h>
42 #include <sys/bus.h>
43 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/rman.h>
46
47 #include <machine/bus.h>
48 #include <machine/cpu.h>
49 #include <machine/pcb.h>
50 #include <vm/vm.h>
51 #include <vm/pmap.h>
52 #include <vm/vm_extern.h>
53 #include <machine/pmap.h>
54
55 #include <arm/xscale/ixp425/ixp425reg.h>
56 #include <arm/xscale/ixp425/ixp425var.h>
57
58 #include <dev/pci/pcib_private.h>
59 #include "pcib_if.h"
60
61 #include <dev/pci/pcireg.h>
62 extern struct ixp425_softc *ixp425_softc;
63
64 #define PCI_CSR_WRITE_4(sc, reg, data) \
65 bus_write_4(sc->sc_csr, reg, data)
66
67 #define PCI_CSR_READ_4(sc, reg) \
68 bus_read_4(sc->sc_csr, reg)
69
70 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
71 #define PCI_CONF_UNLOCK(s) restore_interrupts((s))
72
73 static device_probe_t ixppcib_probe;
74 static device_attach_t ixppcib_attach;
75 static bus_read_ivar_t ixppcib_read_ivar;
76 static bus_write_ivar_t ixppcib_write_ivar;
77 static bus_setup_intr_t ixppcib_setup_intr;
78 static bus_teardown_intr_t ixppcib_teardown_intr;
79 static bus_alloc_resource_t ixppcib_alloc_resource;
80 static bus_activate_resource_t ixppcib_activate_resource;
81 static bus_deactivate_resource_t ixppcib_deactivate_resource;
82 static bus_release_resource_t ixppcib_release_resource;
83 static pcib_maxslots_t ixppcib_maxslots;
84 static pcib_read_config_t ixppcib_read_config;
85 static pcib_write_config_t ixppcib_write_config;
86 static pcib_route_interrupt_t ixppcib_route_interrupt;
87
88 static int
89 ixppcib_probe(device_t dev)
90 {
91
92 device_set_desc(dev, "IXP425 PCI Bus");
93 return (0);
94 }
95
96 static void
97 ixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg,
98 uint32_t data)
99 {
100 PCI_CSR_WRITE_4(sc,
101 PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE));
102 PCI_CSR_WRITE_4(sc,
103 PCI_CRP_AD_WDATA, data);
104 }
105
106 static int
107 ixppcib_attach(device_t dev)
108 {
109 int rid;
110 struct ixppcib_softc *sc;
111
112 sc = device_get_softc(dev);
113
114 rid = 0;
115 sc->sc_csr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
116 IXP425_PCI_HWBASE, IXP425_PCI_HWBASE + IXP425_PCI_SIZE,
117 IXP425_PCI_SIZE, RF_ACTIVE);
118 if (sc->sc_csr == NULL)
119 panic("cannot allocate PCI CSR registers");
120
121 ixp425_md_attach(dev);
122 /* always setup the base, incase another OS messes w/ it */
123 PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);
124
125 rid = 0;
126 sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
127 IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE,
128 IXP425_PCI_MEM_SIZE, RF_ACTIVE);
129 if (sc->sc_mem == NULL)
130 panic("cannot allocate PCI MEM space");
131
132 /*
133 * Initialize the bus space tags.
134 */
135 ixp425_io_bs_init(&sc->sc_pci_iot, sc);
136 ixp425_mem_bs_init(&sc->sc_pci_memt, sc);
137
138 sc->sc_dev = dev;
139
140 /* Initialize memory and i/o rmans. */
141 sc->sc_io_rman.rm_type = RMAN_ARRAY;
142 sc->sc_io_rman.rm_descr = "IXP425 PCI I/O Ports";
143 if (rman_init(&sc->sc_io_rman) != 0 ||
144 rman_manage_region(&sc->sc_io_rman, 0,
145 IXP425_PCI_IO_SIZE) != 0) {
146 panic("ixppcib_probe: failed to set up I/O rman");
147 }
148
149 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
150 sc->sc_mem_rman.rm_descr = "IXP425 PCI Memory";
151 if (rman_init(&sc->sc_mem_rman) != 0 ||
152 rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE,
153 IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) {
154 panic("ixppcib_probe: failed to set up memory rman");
155 }
156
157 /*
158 * PCI->AHB address translation
159 * begin at the physical memory start + OFFSET
160 */
161 #define AHB_OFFSET 0x10000000UL
162 PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE,
163 (AHB_OFFSET & 0xFF000000) +
164 ((AHB_OFFSET & 0xFF000000) >> 8) +
165 ((AHB_OFFSET & 0xFF000000) >> 16) +
166 ((AHB_OFFSET & 0xFF000000) >> 24) +
167 0x00010203);
168
169 #define IXPPCIB_WRITE_CONF(sc, reg, val) \
170 ixp425_pci_conf_reg_write(sc, reg, val)
171 /* Write Mapping registers PCI Configuration Registers */
172 /* Base Address 0 - 3 */
173 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, AHB_OFFSET + 0x00000000);
174 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, AHB_OFFSET + 0x01000000);
175 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, AHB_OFFSET + 0x02000000);
176 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, AHB_OFFSET + 0x03000000);
177
178 /* Base Address 4 */
179 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff);
180
181 /* Base Address 5 */
182 IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000);
183
184 /* Assert some PCI errors */
185 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE);
186
187 #ifdef __ARMEB__
188 /*
189 * Set up byte lane swapping between little-endian PCI
190 * and the big-endian AHB bus
191 */
192 PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS);
193 #else
194 PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE);
195 #endif
196
197 /*
198 * Enable bus mastering and I/O,memory access
199 */
200 IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND,
201 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
202
203 /*
204 * Wait some more to ensure PCI devices have stabilised.
205 */
206 DELAY(50000);
207
208 device_add_child(dev, "pci", -1);
209 return (bus_generic_attach(dev));
210 }
211
212 static int
213 ixppcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
214 {
215 struct ixppcib_softc *sc;
216
217 sc = device_get_softc(dev);
218 switch (which) {
219 case PCIB_IVAR_BUS:
220 *result = sc->sc_bus;
221 return (0);
222 }
223
224 return (ENOENT);
225 }
226
227 static int
228 ixppcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
229 {
230 struct ixppcib_softc *sc;
231
232 sc = device_get_softc(dev);
233 switch (which) {
234 case PCIB_IVAR_BUS:
235 sc->sc_bus = value;
236 return (0);
237 }
238
239 return (ENOENT);
240 }
241
242 static int
243 ixppcib_setup_intr(device_t dev, device_t child, struct resource *ires,
244 int flags, driver_intr_t *intr, void *arg, void **cookiep)
245 {
246
247 return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
248 intr, arg, cookiep));
249 }
250
251 static int
252 ixppcib_teardown_intr(device_t dev, device_t child, struct resource *vec,
253 void *cookie)
254 {
255
256 return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, cookie));
257 }
258
259 static struct resource *
260 ixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
261 u_long start, u_long end, u_long count, u_int flags)
262 {
263 bus_space_tag_t tag;
264 struct ixppcib_softc *sc = device_get_softc(bus);
265 struct rman *rmanp;
266 struct resource *rv;
267
268 tag = NULL; /* shut up stupid gcc */
269 rv = NULL;
270 switch (type) {
271 case SYS_RES_IRQ:
272 rmanp = &sc->sc_irq_rman;
273 break;
274
275 case SYS_RES_IOPORT:
276 rmanp = &sc->sc_io_rman;
277 tag = &sc->sc_pci_iot;
278 break;
279
280 case SYS_RES_MEMORY:
281 rmanp = &sc->sc_mem_rman;
282 tag = &sc->sc_pci_memt;
283 break;
284
285 default:
286 return (rv);
287 }
288
289 rv = rman_reserve_resource(rmanp, start, end, count, flags, child);
290 if (rv != NULL) {
291 rman_set_rid(rv, *rid);
292 if (type == SYS_RES_IOPORT) {
293 rman_set_bustag(rv, tag);
294 rman_set_bushandle(rv, rman_get_start(rv));
295 } else if (type == SYS_RES_MEMORY) {
296 rman_set_bustag(rv, tag);
297 rman_set_bushandle(rv, rman_get_bushandle(sc->sc_mem) +
298 (rman_get_start(rv) - IXP425_PCI_MEM_HWBASE));
299 }
300 }
301
302 return (rv);
303 }
304
305 static int
306 ixppcib_activate_resource(device_t bus, device_t child, int type, int rid,
307 struct resource *r)
308 {
309
310 device_printf(bus, "%s called activate_resource\n", device_get_nameunit(child));
311 return (ENXIO);
312 }
313
314 static int
315 ixppcib_deactivate_resource(device_t bus, device_t child, int type, int rid,
316 struct resource *r)
317 {
318
319 device_printf(bus, "%s called deactivate_resource\n", device_get_nameunit(child));
320 return (ENXIO);
321 }
322
323 static int
324 ixppcib_release_resource(device_t bus, device_t child, int type, int rid,
325 struct resource *r)
326 {
327
328 device_printf(bus, "%s called release_resource\n", device_get_nameunit(child));
329 return (ENXIO);
330 }
331
332 static void
333 ixppcib_conf_setup(struct ixppcib_softc *sc, int bus, int slot, int func,
334 int reg)
335 {
336 if (bus == 0) {
337 if (slot == 0 && func == 0) {
338 PCI_CSR_WRITE_4(sc, PCI_NP_AD, (reg & ~3));
339 } else {
340 bus &= 0xff;
341 slot &= 0x1f;
342 func &= 0x07;
343 /* configuration type 0 */
344 PCI_CSR_WRITE_4(sc, PCI_NP_AD, (1U << (32 - slot)) |
345 (func << 8) | (reg & ~3));
346 }
347 } else {
348 /* configuration type 1 */
349 PCI_CSR_WRITE_4(sc, PCI_NP_AD,
350 (bus << 16) | (slot << 11) |
351 (func << 8) | (reg & ~3) | 1);
352 }
353
354 }
355
356 static int
357 ixppcib_maxslots(device_t dev)
358 {
359
360 return (PCI_SLOTMAX);
361 }
362
363 static u_int32_t
364 ixppcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
365 int bytes)
366 {
367 struct ixppcib_softc *sc = device_get_softc(dev);
368 u_int32_t data, ret;
369
370 ixppcib_conf_setup(sc, bus, slot, func, reg & ~3);
371
372 PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ);
373 ret = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
374 ret >>= (reg & 3) * 8;
375 ret &= 0xffffffff >> ((4 - bytes) * 8);
376 #if 0
377 device_printf(dev, "read config: %u:%u:%u %#x(%d) = %#x\n", bus, slot, func, reg, bytes, ret);
378 #endif
379
380 /* check & clear PCI abort */
381 data = PCI_CSR_READ_4(sc, PCI_ISR);
382 if (data & ISR_PFE) {
383 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
384 return (-1);
385 }
386 return (ret);
387 }
388
389 static const int byteenables[] = { 0, 0x10, 0x30, 0x70, 0xf0 };
390
391 static void
392 ixppcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
393 u_int32_t val, int bytes)
394 {
395 struct ixppcib_softc *sc = device_get_softc(dev);
396 u_int32_t data;
397
398 #if 0
399 device_printf(dev, "write config: %u:%u:%u %#x(%d) = %#x\n", bus, slot, func, reg, bytes, val);
400 #endif
401
402 ixppcib_conf_setup(sc, bus, slot, func, reg & ~3);
403
404 /* Byte enables are active low, so not them first */
405 PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE |
406 (~(byteenables[bytes] << (reg & 3)) & 0xf0));
407 PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val << ((reg & 3) * 8));
408
409 /* check & clear PCI abort */
410 data = PCI_CSR_READ_4(sc, PCI_ISR);
411 if (data & ISR_PFE)
412 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
413 }
414
415 static int
416 ixppcib_route_interrupt(device_t bridge, device_t device, int pin)
417 {
418
419 return (ixp425_md_route_interrupt(bridge, device, pin));
420 }
421
422 static device_method_t ixppcib_methods[] = {
423 /* Device interface */
424 DEVMETHOD(device_probe, ixppcib_probe),
425 DEVMETHOD(device_attach, ixppcib_attach),
426
427 /* Bus interface */
428 DEVMETHOD(bus_print_child, bus_generic_print_child),
429 DEVMETHOD(bus_read_ivar, ixppcib_read_ivar),
430 DEVMETHOD(bus_write_ivar, ixppcib_write_ivar),
431 DEVMETHOD(bus_setup_intr, ixppcib_setup_intr),
432 DEVMETHOD(bus_teardown_intr, ixppcib_teardown_intr),
433 DEVMETHOD(bus_alloc_resource, ixppcib_alloc_resource),
434 DEVMETHOD(bus_activate_resource, ixppcib_activate_resource),
435 DEVMETHOD(bus_deactivate_resource, ixppcib_deactivate_resource),
436 DEVMETHOD(bus_release_resource, ixppcib_release_resource),
437 /* DEVMETHOD(bus_get_dma_tag, ixppcib_get_dma_tag), */
438
439 /* pcib interface */
440 DEVMETHOD(pcib_maxslots, ixppcib_maxslots),
441 DEVMETHOD(pcib_read_config, ixppcib_read_config),
442 DEVMETHOD(pcib_write_config, ixppcib_write_config),
443 DEVMETHOD(pcib_route_interrupt, ixppcib_route_interrupt),
444
445 {0, 0},
446 };
447
448 static driver_t ixppcib_driver = {
449 "pcib",
450 ixppcib_methods,
451 sizeof(struct ixppcib_softc),
452 };
453 static devclass_t ixppcib_devclass;
454
455 DRIVER_MODULE(ixppcib, ixp, ixppcib_driver, ixppcib_devclass, 0, 0);
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