The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/xscale/ixp425/ixp425_pci.c

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    1 /*      $NetBSD: ixp425_pci.c,v 1.5 2006/04/10 03:36:03 simonb Exp $ */
    2 
    3 /*
    4  * Copyright (c) 2003
    5  *      Ichiro FUKUHARA <ichiro@ichiro.org>.
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *      This product includes software developed by Ichiro FUKUHARA.
   19  * 4. The name of the company nor the name of the author may be used to
   20  *    endorse or promote products derived from this software without specific
   21  *    prior written permission.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
   24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   26  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
   27  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   29  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   33  * SUCH DAMAGE.
   34  */
   35 
   36 #include <sys/cdefs.h>
   37 __FBSDID("$FreeBSD$");
   38 
   39 #include <sys/param.h>
   40 #include <sys/systm.h>
   41 #include <sys/malloc.h>
   42 #define _ARM32_BUS_DMA_PRIVATE
   43 #include <sys/bus.h>
   44 #include <sys/kernel.h>
   45 #include <sys/module.h>
   46 #include <sys/rman.h>
   47 
   48 #include <machine/bus.h>
   49 #include <machine/cpu.h>
   50 #include <machine/pcb.h>
   51 #include <vm/vm.h>
   52 #include <vm/pmap.h>
   53 #include <vm/vm_extern.h>
   54 #include <machine/pmap.h>
   55 
   56 #include <arm/xscale/ixp425/ixp425reg.h>
   57 #include <arm/xscale/ixp425/ixp425var.h>
   58 
   59 #include <dev/pci/pcib_private.h>
   60 #include "pcib_if.h"
   61 
   62 #include <dev/pci/pcireg.h>
   63 extern struct ixp425_softc *ixp425_softc;
   64 
   65 #define PCI_CSR_WRITE_4(sc, reg, data)  \
   66         bus_write_4(sc->sc_csr, reg, data)
   67 
   68 #define PCI_CSR_READ_4(sc, reg) \
   69         bus_read_4(sc->sc_csr, reg)
   70 
   71 #define PCI_CONF_LOCK(s)        (s) = disable_interrupts(I32_bit)
   72 #define PCI_CONF_UNLOCK(s)      restore_interrupts((s))
   73 
   74 static device_probe_t ixppcib_probe;
   75 static device_attach_t ixppcib_attach;
   76 static bus_read_ivar_t ixppcib_read_ivar;
   77 static bus_write_ivar_t ixppcib_write_ivar;
   78 static bus_setup_intr_t ixppcib_setup_intr;
   79 static bus_teardown_intr_t ixppcib_teardown_intr;
   80 static bus_alloc_resource_t ixppcib_alloc_resource;
   81 static bus_activate_resource_t ixppcib_activate_resource;
   82 static bus_deactivate_resource_t ixppcib_deactivate_resource;
   83 static bus_release_resource_t ixppcib_release_resource;
   84 static pcib_maxslots_t ixppcib_maxslots;
   85 static pcib_read_config_t ixppcib_read_config;
   86 static pcib_write_config_t ixppcib_write_config;
   87 static pcib_route_interrupt_t ixppcib_route_interrupt;
   88 
   89 static int
   90 ixppcib_probe(device_t dev)
   91 {
   92 
   93         device_set_desc(dev, "IXP425 PCI Bus");
   94         return (0);
   95 }
   96 
   97 static void
   98 ixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg,
   99     uint32_t data)
  100 {
  101         PCI_CSR_WRITE_4(sc,
  102             PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE));
  103         PCI_CSR_WRITE_4(sc,
  104             PCI_CRP_AD_WDATA, data);
  105 }
  106 
  107 static int
  108 ixppcib_attach(device_t dev)
  109 {
  110         int rid;
  111         struct ixppcib_softc *sc;
  112 
  113         sc = device_get_softc(dev);
  114 
  115         rid = 0;
  116         sc->sc_csr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
  117             IXP425_PCI_HWBASE, IXP425_PCI_HWBASE + IXP425_PCI_SIZE,
  118             IXP425_PCI_SIZE, RF_ACTIVE);
  119         if (sc->sc_csr == NULL)
  120                 panic("cannot allocate PCI CSR registers");
  121 
  122         ixp425_md_attach(dev);
  123         /* always setup the base, incase another OS messes w/ it */
  124         PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);
  125 
  126         rid = 0;
  127         sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
  128             IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE,
  129             IXP425_PCI_MEM_SIZE, RF_ACTIVE);
  130         if (sc->sc_mem == NULL)
  131                 panic("cannot allocate PCI MEM space");
  132 
  133 #define AHB_OFFSET      0x10000000UL
  134         if (bus_dma_tag_create(NULL, 1, 0, AHB_OFFSET + 64 * 1024 * 1024,
  135             BUS_SPACE_MAXADDR, NULL, NULL,  0xffffffff, 0xff, 0xffffffff, 0, 
  136             NULL, NULL, &sc->sc_dmat))
  137                 panic("couldn't create the PCI dma tag !");
  138         /* 
  139          * The PCI bus can only address 64MB. However, due to the way our
  140          * implementation of busdma works, busdma can't tell if a device
  141          * is a PCI device or not. So defaults to the PCI dma tag, which
  142          * restrict the DMA'able memory to the first 64MB, and explicitely
  143          * create less restrictive tags for non-PCI devices.
  144          */
  145         arm_root_dma_tag = sc->sc_dmat;
  146         /*
  147          * Initialize the bus space tags.
  148          */
  149         ixp425_io_bs_init(&sc->sc_pci_iot, sc);
  150         ixp425_mem_bs_init(&sc->sc_pci_memt, sc);
  151 
  152         sc->sc_dev = dev;
  153 
  154         /* Initialize memory and i/o rmans. */
  155         sc->sc_io_rman.rm_type = RMAN_ARRAY;
  156         sc->sc_io_rman.rm_descr = "IXP425 PCI I/O Ports";
  157         if (rman_init(&sc->sc_io_rman) != 0 ||
  158                 rman_manage_region(&sc->sc_io_rman, 0, 
  159                     IXP425_PCI_IO_SIZE) != 0) {
  160                 panic("ixppcib_probe: failed to set up I/O rman");
  161         }
  162 
  163         sc->sc_mem_rman.rm_type = RMAN_ARRAY;
  164         sc->sc_mem_rman.rm_descr = "IXP425 PCI Memory";
  165         if (rman_init(&sc->sc_mem_rman) != 0 ||
  166                 rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE,
  167                     IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) {
  168                 panic("ixppcib_probe: failed to set up memory rman");
  169         }
  170 
  171         /*
  172          * PCI->AHB address translation
  173          *      begin at the physical memory start + OFFSET
  174          */
  175         PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE,
  176             (AHB_OFFSET & 0xFF000000) +
  177             ((AHB_OFFSET & 0xFF000000) >> 8) +
  178             ((AHB_OFFSET & 0xFF000000) >> 16) +
  179             ((AHB_OFFSET & 0xFF000000) >> 24) +
  180             0x00010203);
  181         
  182 #define IXPPCIB_WRITE_CONF(sc, reg, val) \
  183         ixp425_pci_conf_reg_write(sc, reg, val)
  184         /* Write Mapping registers PCI Configuration Registers */
  185         /* Base Address 0 - 3 */
  186         IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, AHB_OFFSET + 0x00000000);
  187         IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, AHB_OFFSET + 0x01000000);
  188         IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, AHB_OFFSET + 0x02000000);
  189         IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, AHB_OFFSET + 0x03000000);
  190         
  191         /* Base Address 4 */
  192         IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff);
  193         
  194         /* Base Address 5 */
  195         IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000);
  196         
  197         /* Assert some PCI errors */
  198         PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE);
  199         
  200 #ifdef __ARMEB__
  201         /*
  202          * Set up byte lane swapping between little-endian PCI
  203          * and the big-endian AHB bus
  204          */
  205         PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS);
  206 #else
  207         PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE);
  208 #endif
  209         
  210         /*
  211          * Enable bus mastering and I/O,memory access
  212          */
  213         IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND,
  214             PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
  215         
  216         /*
  217          * Wait some more to ensure PCI devices have stabilised.
  218          */
  219         DELAY(50000);
  220 
  221         device_add_child(dev, "pci", -1);
  222         return (bus_generic_attach(dev));
  223 }
  224 
  225 static int
  226 ixppcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
  227 {
  228         struct ixppcib_softc *sc;
  229 
  230         sc = device_get_softc(dev);
  231         switch (which) {
  232         case PCIB_IVAR_DOMAIN:
  233                 *result = 0;
  234                 return (0);
  235         case PCIB_IVAR_BUS:
  236                 *result = sc->sc_bus;
  237                 return (0);
  238         }
  239 
  240         return (ENOENT);
  241 }
  242 
  243 static int
  244 ixppcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
  245 {
  246         struct ixppcib_softc *sc;
  247 
  248         sc = device_get_softc(dev);
  249         switch (which) {
  250         case PCIB_IVAR_DOMAIN:
  251                 return (EINVAL);
  252         case PCIB_IVAR_BUS:
  253                 sc->sc_bus = value;
  254                 return (0);
  255         }
  256 
  257         return (ENOENT);
  258 }
  259 
  260 static int
  261 ixppcib_setup_intr(device_t dev, device_t child, struct resource *ires,
  262     int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 
  263     void **cookiep)
  264 {
  265 
  266         return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
  267             filt, intr, arg, cookiep));
  268 }
  269 
  270 static int
  271 ixppcib_teardown_intr(device_t dev, device_t child, struct resource *vec,
  272      void *cookie)
  273 {
  274 
  275         return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, cookie));
  276 }
  277 
  278 static struct resource *
  279 ixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
  280     u_long start, u_long end, u_long count, u_int flags)
  281 {
  282         bus_space_tag_t tag;
  283         struct ixppcib_softc *sc = device_get_softc(bus);
  284         struct rman *rmanp;
  285         struct resource *rv;
  286 
  287         tag = NULL; /* shut up stupid gcc */
  288         rv = NULL;
  289         switch (type) {
  290         case SYS_RES_IRQ:
  291                 rmanp = &sc->sc_irq_rman;
  292                 break;
  293 
  294         case SYS_RES_IOPORT:
  295                 rmanp = &sc->sc_io_rman;
  296                 tag = &sc->sc_pci_iot;
  297                 break;
  298 
  299         case SYS_RES_MEMORY:
  300                 rmanp = &sc->sc_mem_rman;
  301                 tag = &sc->sc_pci_memt;
  302                 break;
  303 
  304         default:
  305                 return (rv);
  306         }
  307 
  308         rv = rman_reserve_resource(rmanp, start, end, count, flags, child);
  309         if (rv != NULL) {
  310                 rman_set_rid(rv, *rid);
  311                 if (type == SYS_RES_IOPORT) {
  312                         rman_set_bustag(rv, tag);
  313                         rman_set_bushandle(rv, rman_get_start(rv));
  314                 } else if (type == SYS_RES_MEMORY) {
  315                         rman_set_bustag(rv, tag);
  316                         rman_set_bushandle(rv, rman_get_bushandle(sc->sc_mem) +
  317                             (rman_get_start(rv) - IXP425_PCI_MEM_HWBASE));
  318                 }
  319         }
  320 
  321         return (rv);
  322 }
  323 
  324 static int
  325 ixppcib_activate_resource(device_t bus, device_t child, int type, int rid,
  326     struct resource *r) 
  327 {
  328 
  329         device_printf(bus, "%s called activate_resource\n", device_get_nameunit(child));
  330         return (ENXIO);
  331 }
  332 
  333 static int
  334 ixppcib_deactivate_resource(device_t bus, device_t child, int type, int rid,
  335     struct resource *r) 
  336 {
  337 
  338         device_printf(bus, "%s called deactivate_resource\n", device_get_nameunit(child));
  339         return (ENXIO);
  340 }
  341 
  342 static int
  343 ixppcib_release_resource(device_t bus, device_t child, int type, int rid,
  344     struct resource *r)
  345 {
  346 
  347         device_printf(bus, "%s called release_resource\n", device_get_nameunit(child));
  348         return (ENXIO);
  349 }
  350 
  351 static void
  352 ixppcib_conf_setup(struct ixppcib_softc *sc, int bus, int slot, int func,
  353     int reg)
  354 {
  355         if (bus == 0) {
  356                 if (slot == 0 && func == 0) {
  357                         PCI_CSR_WRITE_4(sc, PCI_NP_AD, (reg & ~3));
  358                 } else {
  359                         bus &= 0xff;
  360                         slot &= 0x1f;
  361                         func &= 0x07;
  362                         /* configuration type 0 */
  363                         PCI_CSR_WRITE_4(sc, PCI_NP_AD, (1U << (32 - slot)) |
  364                                 (func << 8) | (reg & ~3));
  365                 }
  366         } else {
  367                         /* configuration type 1 */
  368                 PCI_CSR_WRITE_4(sc, PCI_NP_AD,
  369                         (bus << 16) | (slot << 11) |
  370                         (func << 8) | (reg & ~3) | 1);
  371         }
  372 
  373 }
  374 
  375 static int
  376 ixppcib_maxslots(device_t dev)
  377 {
  378 
  379         return (PCI_SLOTMAX);
  380 }
  381 
  382 static u_int32_t
  383 ixppcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
  384     int bytes)
  385 {
  386         struct ixppcib_softc *sc = device_get_softc(dev);
  387         u_int32_t data, ret;
  388 
  389         ixppcib_conf_setup(sc, bus, slot, func, reg & ~3);
  390 
  391         PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ);
  392         ret = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
  393         ret >>= (reg & 3) * 8;
  394         ret &= 0xffffffff >> ((4 - bytes) * 8);
  395 #if 0
  396         device_printf(dev, "read config: %u:%u:%u %#x(%d) = %#x\n", bus, slot, func, reg, bytes, ret);
  397 #endif
  398 
  399         /* check & clear PCI abort */
  400         data = PCI_CSR_READ_4(sc, PCI_ISR);
  401         if (data & ISR_PFE) {
  402                 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
  403                 return (-1);
  404         }
  405         return (ret);
  406 }
  407 
  408 static const int byteenables[] = { 0, 0x10, 0x30, 0x70, 0xf0 };
  409 
  410 static void
  411 ixppcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
  412     u_int32_t val, int bytes)
  413 {
  414         struct ixppcib_softc *sc = device_get_softc(dev);
  415         u_int32_t data;
  416 
  417 #if 0
  418         device_printf(dev, "write config: %u:%u:%u %#x(%d) = %#x\n", bus, slot, func, reg, bytes, val);
  419 #endif
  420 
  421         ixppcib_conf_setup(sc, bus, slot, func, reg & ~3);
  422 
  423         /* Byte enables are active low, so not them first */
  424         PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE |
  425             (~(byteenables[bytes] << (reg & 3)) & 0xf0));
  426         PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val << ((reg & 3) * 8));
  427 
  428         /* check & clear PCI abort */
  429         data = PCI_CSR_READ_4(sc, PCI_ISR);
  430         if (data & ISR_PFE)
  431                 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
  432 }
  433 
  434 static int
  435 ixppcib_route_interrupt(device_t bridge, device_t device, int pin)
  436 {
  437 
  438         return (ixp425_md_route_interrupt(bridge, device, pin));
  439 }
  440 
  441 static device_method_t ixppcib_methods[] = {
  442         /* Device interface */
  443         DEVMETHOD(device_probe,                 ixppcib_probe),
  444         DEVMETHOD(device_attach,                ixppcib_attach),
  445 
  446         /* Bus interface */
  447         DEVMETHOD(bus_print_child,              bus_generic_print_child),
  448         DEVMETHOD(bus_read_ivar,                ixppcib_read_ivar),
  449         DEVMETHOD(bus_write_ivar,               ixppcib_write_ivar),
  450         DEVMETHOD(bus_setup_intr,               ixppcib_setup_intr),
  451         DEVMETHOD(bus_teardown_intr,            ixppcib_teardown_intr),
  452         DEVMETHOD(bus_alloc_resource,           ixppcib_alloc_resource),
  453         DEVMETHOD(bus_activate_resource,        ixppcib_activate_resource),
  454         DEVMETHOD(bus_deactivate_resource,      ixppcib_deactivate_resource),
  455         DEVMETHOD(bus_release_resource,         ixppcib_release_resource),
  456         /* DEVMETHOD(bus_get_dma_tag,           ixppcib_get_dma_tag), */
  457 
  458         /* pcib interface */
  459         DEVMETHOD(pcib_maxslots,                ixppcib_maxslots),
  460         DEVMETHOD(pcib_read_config,             ixppcib_read_config),
  461         DEVMETHOD(pcib_write_config,            ixppcib_write_config),
  462         DEVMETHOD(pcib_route_interrupt,         ixppcib_route_interrupt),
  463 
  464         {0, 0},
  465 };
  466 
  467 static driver_t ixppcib_driver = {
  468         "pcib",
  469         ixppcib_methods,
  470         sizeof(struct ixppcib_softc),
  471 };
  472 static devclass_t ixppcib_devclass;
  473 
  474 DRIVER_MODULE(ixppcib, ixp, ixppcib_driver, ixppcib_devclass, 0, 0);

Cache object: 6bb33329fe0a578b5e097890c868faa7


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