The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/xscale/ixp425/ixp425_pci.c

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    1 /*      $NetBSD: ixp425_pci.c,v 1.5 2006/04/10 03:36:03 simonb Exp $ */
    2 
    3 /*
    4  * Copyright (c) 2003
    5  *      Ichiro FUKUHARA <ichiro@ichiro.org>.
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *      This product includes software developed by Ichiro FUKUHARA.
   19  * 4. The name of the company nor the name of the author may be used to
   20  *    endorse or promote products derived from this software without specific
   21  *    prior written permission.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
   24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   26  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
   27  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   29  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   33  * SUCH DAMAGE.
   34  */
   35 
   36 #include <sys/cdefs.h>
   37 __FBSDID("$FreeBSD: stable/8/sys/arm/xscale/ixp425/ixp425_pci.c 230714 2012-01-29 01:22:48Z marius $");
   38 
   39 #include <sys/param.h>
   40 #include <sys/systm.h>
   41 #include <sys/malloc.h>
   42 #define _ARM32_BUS_DMA_PRIVATE
   43 #include <sys/bus.h>
   44 #include <sys/kernel.h>
   45 #include <sys/module.h>
   46 #include <sys/rman.h>
   47 
   48 #include <machine/bus.h>
   49 #include <machine/cpu.h>
   50 #include <machine/pcb.h>
   51 #include <vm/vm.h>
   52 #include <vm/pmap.h>
   53 #include <vm/vm_extern.h>
   54 #include <machine/pmap.h>
   55 
   56 #include <arm/xscale/ixp425/ixp425reg.h>
   57 #include <arm/xscale/ixp425/ixp425var.h>
   58 
   59 #include <dev/pci/pcib_private.h>
   60 #include "pcib_if.h"
   61 
   62 #include <dev/pci/pcireg.h>
   63 extern struct ixp425_softc *ixp425_softc;
   64 
   65 #define PCI_CSR_WRITE_4(sc, reg, data)  \
   66         bus_write_4(sc->sc_csr, reg, data)
   67 
   68 #define PCI_CSR_READ_4(sc, reg) \
   69         bus_read_4(sc->sc_csr, reg)
   70 
   71 #define PCI_CONF_LOCK(s)        (s) = disable_interrupts(I32_bit)
   72 #define PCI_CONF_UNLOCK(s)      restore_interrupts((s))
   73 
   74 static device_probe_t ixppcib_probe;
   75 static device_attach_t ixppcib_attach;
   76 static bus_read_ivar_t ixppcib_read_ivar;
   77 static bus_write_ivar_t ixppcib_write_ivar;
   78 static bus_setup_intr_t ixppcib_setup_intr;
   79 static bus_teardown_intr_t ixppcib_teardown_intr;
   80 static bus_alloc_resource_t ixppcib_alloc_resource;
   81 static bus_activate_resource_t ixppcib_activate_resource;
   82 static bus_deactivate_resource_t ixppcib_deactivate_resource;
   83 static bus_release_resource_t ixppcib_release_resource;
   84 static pcib_maxslots_t ixppcib_maxslots;
   85 static pcib_read_config_t ixppcib_read_config;
   86 static pcib_write_config_t ixppcib_write_config;
   87 static pcib_route_interrupt_t ixppcib_route_interrupt;
   88 
   89 static int
   90 ixppcib_probe(device_t dev)
   91 {
   92         device_set_desc(dev, "IXP4XX PCI Bus");
   93         return (0);
   94 }
   95 
   96 static void
   97 ixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg,
   98     uint32_t data)
   99 {
  100         PCI_CSR_WRITE_4(sc, PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE));
  101         PCI_CSR_WRITE_4(sc, PCI_CRP_AD_WDATA, data);
  102 }
  103 
  104 static int
  105 ixppcib_attach(device_t dev)
  106 {
  107         int rid;
  108         struct ixppcib_softc *sc;
  109 
  110         sc = device_get_softc(dev);
  111 
  112         rid = 0;
  113         sc->sc_csr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
  114             IXP425_PCI_HWBASE, IXP425_PCI_HWBASE + IXP425_PCI_SIZE,
  115             IXP425_PCI_SIZE, RF_ACTIVE);
  116         if (sc->sc_csr == NULL)
  117                 panic("cannot allocate PCI CSR registers");
  118 
  119         ixp425_md_attach(dev);
  120         /* always setup the base, incase another OS messes w/ it */
  121         PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);
  122 
  123         rid = 0;
  124         sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
  125             IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE,
  126             IXP425_PCI_MEM_SIZE, RF_ACTIVE);
  127         if (sc->sc_mem == NULL)
  128                 panic("cannot allocate PCI MEM space");
  129 
  130         /* NB: PCI dma window is 64M so anything above must be bounced */
  131         if (bus_dma_tag_create(NULL, 1, 0, IXP425_AHB_OFFSET + 64 * 1024 * 1024,
  132             BUS_SPACE_MAXADDR, NULL, NULL,  0xffffffff, 0xff, 0xffffffff, 0, 
  133             NULL, NULL, &sc->sc_dmat))
  134                 panic("couldn't create the PCI dma tag !");
  135         /* 
  136          * The PCI bus can only address 64MB. However, due to the way our
  137          * implementation of busdma works, busdma can't tell if a device
  138          * is a PCI device or not. So defaults to the PCI dma tag, which
  139          * restrict the DMA'able memory to the first 64MB, and explicitely
  140          * create less restrictive tags for non-PCI devices.
  141          */
  142         arm_root_dma_tag = sc->sc_dmat;
  143         /*
  144          * Initialize the bus space tags.
  145          */
  146         ixp425_io_bs_init(&sc->sc_pci_iot, sc);
  147         ixp425_mem_bs_init(&sc->sc_pci_memt, sc);
  148 
  149         sc->sc_dev = dev;
  150 
  151         /* Initialize memory and i/o rmans. */
  152         sc->sc_io_rman.rm_type = RMAN_ARRAY;
  153         sc->sc_io_rman.rm_descr = "IXP4XX PCI I/O Ports";
  154         if (rman_init(&sc->sc_io_rman) != 0 ||
  155                 rman_manage_region(&sc->sc_io_rman, 0, 
  156                     IXP425_PCI_IO_SIZE) != 0) {
  157                 panic("ixppcib_probe: failed to set up I/O rman");
  158         }
  159 
  160         sc->sc_mem_rman.rm_type = RMAN_ARRAY;
  161         sc->sc_mem_rman.rm_descr = "IXP4XX PCI Memory";
  162         if (rman_init(&sc->sc_mem_rman) != 0 ||
  163                 rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE,
  164                     IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) {
  165                 panic("ixppcib_probe: failed to set up memory rman");
  166         }
  167 
  168         /*
  169          * PCI->AHB address translation
  170          *      begin at the physical memory start + OFFSET
  171          */
  172         PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE,
  173             (IXP425_AHB_OFFSET & 0xFF000000) +
  174             ((IXP425_AHB_OFFSET & 0xFF000000) >> 8) +
  175             ((IXP425_AHB_OFFSET & 0xFF000000) >> 16) +
  176             ((IXP425_AHB_OFFSET & 0xFF000000) >> 24) +
  177             0x00010203);
  178         
  179 #define IXPPCIB_WRITE_CONF(sc, reg, val) \
  180         ixp425_pci_conf_reg_write(sc, reg, val)
  181         /* Write Mapping registers PCI Configuration Registers */
  182         /* Base Address 0 - 3 */
  183         IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, IXP425_AHB_OFFSET + 0x00000000);
  184         IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, IXP425_AHB_OFFSET + 0x01000000);
  185         IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, IXP425_AHB_OFFSET + 0x02000000);
  186         IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, IXP425_AHB_OFFSET + 0x03000000);
  187         
  188         /* Base Address 4 */
  189         IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff);
  190         
  191         /* Base Address 5 */
  192         IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000);
  193         
  194         /* Assert some PCI errors */
  195         PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE);
  196         
  197 #ifdef __ARMEB__
  198         /*
  199          * Set up byte lane swapping between little-endian PCI
  200          * and the big-endian AHB bus
  201          */
  202         PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS);
  203 #else
  204         PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE);
  205 #endif
  206         
  207         /*
  208          * Enable bus mastering and I/O,memory access
  209          */
  210         IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND,
  211             PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
  212         
  213         /*
  214          * Wait some more to ensure PCI devices have stabilised.
  215          */
  216         DELAY(50000);
  217 
  218         device_add_child(dev, "pci", -1);
  219         return (bus_generic_attach(dev));
  220 }
  221 
  222 static int
  223 ixppcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
  224 {
  225         struct ixppcib_softc *sc;
  226 
  227         sc = device_get_softc(dev);
  228         switch (which) {
  229         case PCIB_IVAR_DOMAIN:
  230                 *result = 0;
  231                 return (0);
  232         case PCIB_IVAR_BUS:
  233                 *result = sc->sc_bus;
  234                 return (0);
  235         }
  236 
  237         return (ENOENT);
  238 }
  239 
  240 static int
  241 ixppcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
  242 {
  243         struct ixppcib_softc *sc;
  244 
  245         sc = device_get_softc(dev);
  246         switch (which) {
  247         case PCIB_IVAR_DOMAIN:
  248                 return (EINVAL);
  249         case PCIB_IVAR_BUS:
  250                 sc->sc_bus = value;
  251                 return (0);
  252         }
  253 
  254         return (ENOENT);
  255 }
  256 
  257 static int
  258 ixppcib_setup_intr(device_t dev, device_t child, struct resource *ires,
  259     int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 
  260     void **cookiep)
  261 {
  262 
  263         return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
  264             filt, intr, arg, cookiep));
  265 }
  266 
  267 static int
  268 ixppcib_teardown_intr(device_t dev, device_t child, struct resource *vec,
  269      void *cookie)
  270 {
  271 
  272         return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, cookie));
  273 }
  274 
  275 static struct resource *
  276 ixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
  277     u_long start, u_long end, u_long count, u_int flags)
  278 {
  279         struct ixppcib_softc *sc = device_get_softc(bus);
  280         struct rman *rmanp;
  281         struct resource *rv;
  282 
  283         rv = NULL;
  284         switch (type) {
  285         case SYS_RES_IRQ:
  286                 rmanp = &sc->sc_irq_rman;
  287                 break;
  288 
  289         case SYS_RES_IOPORT:
  290                 rmanp = &sc->sc_io_rman;
  291                 break;
  292 
  293         case SYS_RES_MEMORY:
  294                 rmanp = &sc->sc_mem_rman;
  295                 break;
  296 
  297         default:
  298                 return (rv);
  299         }
  300 
  301         rv = rman_reserve_resource(rmanp, start, end, count, flags & ~RF_ACTIVE,
  302             child);
  303         if (rv == NULL)
  304                 return (NULL);
  305         rman_set_rid(rv, *rid);
  306         if (flags & RF_ACTIVE) {
  307                 if (bus_activate_resource(child, type, *rid, rv)) {
  308                         rman_release_resource(rv);
  309                         return (NULL);
  310                 }
  311         }
  312 
  313         return (rv);
  314 }
  315 
  316 static int
  317 ixppcib_activate_resource(device_t bus, device_t child, int type, int rid,
  318     struct resource *r) 
  319 {
  320 
  321         struct ixppcib_softc *sc = device_get_softc(bus);
  322   
  323         switch (type) {
  324         case SYS_RES_IOPORT:
  325                 rman_set_bustag(r, &sc->sc_pci_iot);
  326                 rman_set_bushandle(r, rman_get_start(r));
  327                 break;
  328         case SYS_RES_MEMORY:
  329                 rman_set_bustag(r, &sc->sc_pci_memt);
  330                 rman_set_bushandle(r, rman_get_bushandle(sc->sc_mem) +
  331                     (rman_get_start(r) - IXP425_PCI_MEM_HWBASE));
  332                 break;
  333         }
  334                 
  335         return (rman_activate_resource(r));
  336 }
  337 
  338 static int
  339 ixppcib_deactivate_resource(device_t bus, device_t child, int type, int rid,
  340     struct resource *r) 
  341 {
  342 
  343         device_printf(bus, "%s called deactivate_resource (unexpected)\n",
  344             device_get_nameunit(child));
  345         return (ENXIO);
  346 }
  347 
  348 static int
  349 ixppcib_release_resource(device_t bus, device_t child, int type, int rid,
  350     struct resource *r)
  351 {
  352 
  353         device_printf(bus, "%s called release_resource (unexpected)\n",
  354             device_get_nameunit(child));
  355         return (ENXIO);
  356 }
  357 
  358 static void
  359 ixppcib_conf_setup(struct ixppcib_softc *sc, int bus, int slot, int func,
  360     int reg)
  361 {
  362         if (bus == 0) {
  363                 /* configuration type 0 */
  364                 PCI_CSR_WRITE_4(sc, PCI_NP_AD,
  365                     (1U << (32 - (slot & 0x1f))) |
  366                     ((func & 0x7) << 8) | (reg & ~3));
  367         } else {
  368                 /* configuration type 1 */
  369                 PCI_CSR_WRITE_4(sc, PCI_NP_AD,
  370                     (bus << 16) | (slot << 11) |
  371                     (func << 8) | (reg & ~3) | 1);
  372         }
  373 
  374 }
  375 
  376 static int
  377 ixppcib_maxslots(device_t dev)
  378 {
  379 
  380         return (PCI_SLOTMAX);
  381 }
  382 
  383 static u_int32_t
  384 ixppcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
  385     int bytes)
  386 {
  387         struct ixppcib_softc *sc = device_get_softc(dev);
  388         u_int32_t data, ret;
  389 
  390         ixppcib_conf_setup(sc, bus, slot, func, reg & ~3);
  391 
  392         PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ);
  393         ret = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
  394         ret >>= (reg & 3) * 8;
  395         ret &= 0xffffffff >> ((4 - bytes) * 8);
  396 #if 0
  397         device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n",
  398             __func__, bus, slot, func, reg, bytes, ret);
  399 #endif
  400         /* check & clear PCI abort */
  401         data = PCI_CSR_READ_4(sc, PCI_ISR);
  402         if (data & ISR_PFE) {
  403                 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
  404                 return (-1);
  405         }
  406         return (ret);
  407 }
  408 
  409 static const int byteenables[] = { 0, 0x10, 0x30, 0x70, 0xf0 };
  410 
  411 static void
  412 ixppcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
  413     u_int32_t val, int bytes)
  414 {
  415         struct ixppcib_softc *sc = device_get_softc(dev);
  416         u_int32_t data;
  417 
  418 #if 0
  419         device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n",
  420             __func__, bus, slot, func, reg, bytes, val);
  421 #endif
  422         ixppcib_conf_setup(sc, bus, slot, func, reg & ~3);
  423 
  424         /* Byte enables are active low, so not them first */
  425         PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE |
  426             (~(byteenables[bytes] << (reg & 3)) & 0xf0));
  427         PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val << ((reg & 3) * 8));
  428 
  429         /* check & clear PCI abort */
  430         data = PCI_CSR_READ_4(sc, PCI_ISR);
  431         if (data & ISR_PFE)
  432                 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
  433 }
  434 
  435 static int
  436 ixppcib_route_interrupt(device_t bridge, device_t device, int pin)
  437 {
  438 
  439         return (ixp425_md_route_interrupt(bridge, device, pin));
  440 }
  441 
  442 static device_method_t ixppcib_methods[] = {
  443         /* Device interface */
  444         DEVMETHOD(device_probe,                 ixppcib_probe),
  445         DEVMETHOD(device_attach,                ixppcib_attach),
  446 
  447         /* Bus interface */
  448         DEVMETHOD(bus_read_ivar,                ixppcib_read_ivar),
  449         DEVMETHOD(bus_write_ivar,               ixppcib_write_ivar),
  450         DEVMETHOD(bus_setup_intr,               ixppcib_setup_intr),
  451         DEVMETHOD(bus_teardown_intr,            ixppcib_teardown_intr),
  452         DEVMETHOD(bus_alloc_resource,           ixppcib_alloc_resource),
  453         DEVMETHOD(bus_activate_resource,        ixppcib_activate_resource),
  454         DEVMETHOD(bus_deactivate_resource,      ixppcib_deactivate_resource),
  455         DEVMETHOD(bus_release_resource,         ixppcib_release_resource),
  456         /* DEVMETHOD(bus_get_dma_tag,           ixppcib_get_dma_tag), */
  457 
  458         /* pcib interface */
  459         DEVMETHOD(pcib_maxslots,                ixppcib_maxslots),
  460         DEVMETHOD(pcib_read_config,             ixppcib_read_config),
  461         DEVMETHOD(pcib_write_config,            ixppcib_write_config),
  462         DEVMETHOD(pcib_route_interrupt,         ixppcib_route_interrupt),
  463 
  464         DEVMETHOD_END
  465 };
  466 
  467 static driver_t ixppcib_driver = {
  468         "pcib",
  469         ixppcib_methods,
  470         sizeof(struct ixppcib_softc),
  471 };
  472 static devclass_t ixppcib_devclass;
  473 
  474 DRIVER_MODULE(ixppcib, ixp, ixppcib_driver, ixppcib_devclass, 0, 0);

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