The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/xscale/ixp425/ixp425_qmgr.h

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    1 /*-
    2  * Copyright (c) 2006 Sam Leffler, Errno Consulting
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer,
   10  *    without modification.
   11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
   12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
   13  *    redistribution must be conditioned upon including a substantially
   14  *    similar Disclaimer requirement for further binary redistribution.
   15  *
   16  * NO WARRANTY
   17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
   20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
   21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
   22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
   25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   27  * THE POSSIBILITY OF SUCH DAMAGES.
   28  *
   29  * $FreeBSD: releng/8.3/sys/arm/xscale/ixp425/ixp425_qmgr.h 193096 2009-05-30 15:14:44Z attilio $
   30  */
   31 
   32 /*-
   33  * Copyright (c) 2001-2005, Intel Corporation.
   34  * All rights reserved.
   35  * 
   36  * Redistribution and use in source and binary forms, with or without
   37  * modification, are permitted provided that the following conditions
   38  * are met:
   39  * 1. Redistributions of source code must retain the above copyright
   40  *    notice, this list of conditions and the following disclaimer.
   41  * 2. Redistributions in binary form must reproduce the above copyright
   42  *    notice, this list of conditions and the following disclaimer in the
   43  *    documentation and/or other materials provided with the distribution.
   44  * 3. Neither the name of the Intel Corporation nor the names of its contributors
   45  *    may be used to endorse or promote products derived from this software
   46  *    without specific prior written permission.
   47  * 
   48  * 
   49  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
   50  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   51  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   52  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
   53  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   54  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   55  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   56  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   57  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   58  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   59  * SUCH DAMAGE.
   60 */
   61 
   62 #ifndef ARM_XSCALE_IXP425_QMGR_H
   63 #define ARM_XSCALE_IXP425_QMGR_H
   64 
   65 #define IX_QMGR_MAX_NUM_QUEUES          64
   66 #define IX_QMGR_MIN_QUEUPP_QID          32
   67 
   68 #define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16
   69 
   70 /* Total size of SRAM */
   71 #define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000
   72 
   73 #define IX_QMGR_Q_PRIORITY_0            0
   74 #define IX_QMGR_Q_PRIORITY_1            1
   75 #define IX_QMGR_Q_PRIORITY_2            2
   76 #define IX_QMGR_NUM_PRIORITY_LEVELS     3       /* number of priority levels */
   77 
   78 #define IX_QMGR_Q_STATUS_E_BIT_MASK     0x1     /* Empty */
   79 #define IX_QMGR_Q_STATUS_NE_BIT_MASK    0x2     /* Nearly Empty */
   80 #define IX_QMGR_Q_STATUS_NF_BIT_MASK    0x4     /* Nearly Full */
   81 #define IX_QMGR_Q_STATUS_F_BIT_MASK     0x8     /* Full */
   82 #define IX_QMGR_Q_STATUS_UF_BIT_MASK    0x10    /* Underflow */
   83 #define IX_QMGR_Q_STATUS_OF_BIT_MASK    0x20    /* Overflow */
   84 
   85 #define IX_QMGR_Q_SOURCE_ID_E           0 /* Q Empty after last read */
   86 #define IX_QMGR_Q_SOURCE_ID_NE          1 /* Q Nearly Empty after last read */
   87 #define IX_QMGR_Q_SOURCE_ID_NF          2 /* Q Nearly Full after last write */
   88 #define IX_QMGR_Q_SOURCE_ID_F           3 /* Q Full after last write */
   89 #define IX_QMGR_Q_SOURCE_ID_NOT_E       4 /* Q !Empty after last write */
   90 #define IX_QMGR_Q_SOURCE_ID_NOT_NE      5 /* Q !Nearly Empty after last write */
   91 #define IX_QMGR_Q_SOURCE_ID_NOT_NF      6 /* Q !Nearly Full after last read */
   92 #define IX_QMGR_Q_SOURCE_ID_NOT_F       7 /* Q !Full after last read */
   93 
   94 #define IX_QMGR_UNDERFLOW_BIT_OFFSET    0x0     /* underflow bit mask */
   95 #define IX_QMGR_OVERFLOW_BIT_OFFSET     0x1     /* overflow bit mask */
   96 
   97 #define IX_QMGR_QUEACC0_OFFSET          0x0000  /* q 0 access register */
   98 #define IX_QMGR_QUEACC_SIZE             0x4/*words*/
   99 
  100 #define IX_QMGR_QUELOWSTAT0_OFFSET      0x400   /* Q status, q's 0-7 */
  101 #define IX_QMGR_QUELOWSTAT1_OFFSET      0x404   /* Q status, q's 8-15 */
  102 #define IX_QMGR_QUELOWSTAT2_OFFSET      0x408   /* Q status, q's 16-23 */
  103 #define IX_QMGR_QUELOWSTAT3_OFFSET      0x40c   /* Q status, q's 24-31 */
  104 
  105 /* Queue status register Q status bits mask */
  106 #define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF
  107 /* Size of queue 0-31 status register */
  108 #define IX_QMGR_QUELOWSTAT_SIZE     0x4 /*words*/
  109 #define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 8   /* # status/word */
  110 
  111 #define IX_QMGR_QUEUOSTAT0_OFFSET       0x410   /* Q UF/OF status, q's 0-15 */
  112 #define IX_QMGR_QUEUOSTAT1_OFFSET       0x414   /* Q UF/OF status, q's 16-31 */
  113 
  114 #define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 16   /* # UF/OF status/word */
  115 
  116 #define IX_QMGR_QUEUPPSTAT0_OFFSET      0x418   /* NE status, q's 32-63 */
  117 #define IX_QMGR_QUEUPPSTAT1_OFFSET      0x41c   /* F status, q's 32-63 */
  118 
  119 #define IX_QMGR_INT0SRCSELREG0_OFFSET   0x420   /* INT src select, q's 0-7 */
  120 #define IX_QMGR_INT0SRCSELREG1_OFFSET   0x424   /* INT src select, q's 8-15 */
  121 #define IX_QMGR_INT0SRCSELREG2_OFFSET   0x428   /* INT src select, q's 16-23 */
  122 #define IX_QMGR_INT0SRCSELREG3_OFFSET   0x42c   /* INT src select, q's 24-31 */
  123 
  124 #define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 8       /* # INT src select/word */
  125 
  126 #define IX_QMGR_QUEIEREG0_OFFSET        0x430   /* INT enable, q's 0-31 */
  127 #define IX_QMGR_QUEIEREG1_OFFSET        0x434   /* INT enable, q's 32-63 */
  128 #define IX_QMGR_QINTREG0_OFFSET         0x438   /* INT status, q's 0-31 */
  129 #define IX_QMGR_QINTREG1_OFFSET         0x43c   /* INT status, q's 32-63 */
  130 
  131 #define IX_QMGR_QUECONFIG_BASE_OFFSET   0x2000  /* Q config register, q 0 */
  132 
  133 #define IX_QMGR_QUECONFIG_SIZE          0x100   /* total size of Q config regs*/
  134 
  135 #define IX_QMGR_QUEBUFFER_SPACE_OFFSET  0x2100  /* start of SRAM */
  136 
  137 /* Total bits in a word */
  138 #define BITS_PER_WORD 32
  139 
  140 /* Size of queue buffer space */
  141 #define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00
  142 
  143 /*
  144  * This macro will return the address of the access register for the
  145  * queue  specified by qId
  146  */
  147 #define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\
  148         (((qId) * (IX_QMGR_QUEACC_SIZE * sizeof(uint32_t)))\
  149          + IX_QMGR_QUEACC0_OFFSET)
  150 
  151 /* 
  152  * Bit location of bit-3 of INT0SRCSELREG0 register to enabled
  153  * sticky interrupt register.
  154  */
  155 #define IX_QMGR_INT0SRCSELREG0_BIT3 3
  156 
  157 /*
  158  * These defines are the bit offsets of the various fields of
  159  * the queue configuration register.
  160  */
  161 #if 0
  162 #define IX_QMGR_Q_CONFIG_WRPTR_OFFSET       0x00
  163 #define IX_QMGR_Q_CONFIG_RDPTR_OFFSET       0x07
  164 #define IX_QMGR_Q_CONFIG_BADDR_OFFSET       0x0E
  165 #define IX_QMGR_Q_CONFIG_ESIZE_OFFSET       0x16
  166 #define IX_QMGR_Q_CONFIG_BSIZE_OFFSET       0x18
  167 #define IX_QMGR_Q_CONFIG_NE_OFFSET          0x1A
  168 #define IX_QMGR_Q_CONFIG_NF_OFFSET          0x1D
  169 
  170 #define IX_QMGR_NE_NF_CLEAR_MASK            0x03FFFFFF
  171 #define IX_QMGR_NE_MASK                     0x7
  172 #define IX_QMGR_NF_MASK                     0x7
  173 #define IX_QMGR_SIZE_MASK                   0x3
  174 #define IX_QMGR_ENTRY_SIZE_MASK             0x3
  175 #define IX_QMGR_BADDR_MASK                  0x003FC000
  176 #define IX_QMGR_RDPTR_MASK                  0x7F
  177 #define IX_QMGR_WRPTR_MASK                  0x7F
  178 #define IX_QMGR_RDWRPTR_MASK                0x00003FFF
  179 #else
  180 #define IX_QMGR_Q_CONFIG_WRPTR_OFFSET       0
  181 #define IX_QMGR_WRPTR_MASK                  0x7F
  182 #define IX_QMGR_Q_CONFIG_RDPTR_OFFSET       7
  183 #define IX_QMGR_RDPTR_MASK                  0x7F
  184 #define IX_QMGR_Q_CONFIG_BADDR_OFFSET       14
  185 #define IX_QMGR_BADDR_MASK                  0x3FC000    /* XXX not used */
  186 #define IX_QMGR_Q_CONFIG_ESIZE_OFFSET       22
  187 #define IX_QMGR_ENTRY_SIZE_MASK             0x3
  188 #define IX_QMGR_Q_CONFIG_BSIZE_OFFSET       24
  189 #define IX_QMGR_SIZE_MASK                   0x3
  190 #define IX_QMGR_Q_CONFIG_NE_OFFSET          26
  191 #define IX_QMGR_NE_MASK                     0x7
  192 #define IX_QMGR_Q_CONFIG_NF_OFFSET          29
  193 #define IX_QMGR_NF_MASK                     0x7
  194 
  195 #define IX_QMGR_RDWRPTR_MASK                0x00003FFF
  196 #define IX_QMGR_NE_NF_CLEAR_MASK            0x03FFFFFF
  197 #endif
  198 
  199 #define IX_QMGR_BASE_ADDR_16_WORD_ALIGN     64
  200 #define IX_QMGR_BASE_ADDR_16_WORD_SHIFT     6
  201 
  202 #define IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS 0x1000
  203 
  204 /* Base address of AQM SRAM */
  205 #define IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET \
  206 ((IX_QMGR_QUECONFIG_BASE_OFFSET) + (IX_QMGR_QUECONFIG_SIZE))
  207 
  208 /* Min buffer size used for generating buffer size in QUECONFIG */
  209 #define IX_QMGR_MIN_BUFFER_SIZE 16
  210 
  211 /* Reset values of QMgr hardware registers */
  212 #define IX_QMGR_QUELOWSTAT_RESET_VALUE    0x33333333
  213 #define IX_QMGR_QUEUOSTAT_RESET_VALUE     0x00000000
  214 #define IX_QMGR_QUEUPPSTAT0_RESET_VALUE   0xFFFFFFFF
  215 #define IX_QMGR_QUEUPPSTAT1_RESET_VALUE   0x00000000
  216 #define IX_QMGR_INT0SRCSELREG_RESET_VALUE 0x00000000
  217 #define IX_QMGR_QUEIEREG_RESET_VALUE      0x00000000
  218 #define IX_QMGR_QINTREG_RESET_VALUE       0xFFFFFFFF
  219 #define IX_QMGR_QUECONFIG_RESET_VALUE     0x00000000
  220 
  221 #define IX_QMGR_QUELOWSTAT_BITS_PER_Q \
  222         (BITS_PER_WORD/IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)
  223 
  224 #define IX_QMGR_QUELOWSTAT_QID_MASK 0x7
  225 #define IX_QMGR_Q_CONFIG_ADDR_GET(qId)\
  226         (((qId) * sizeof(uint32_t)) + IX_QMGR_QUECONFIG_BASE_OFFSET)
  227 
  228 #define IX_QMGR_ENTRY1_OFFSET 0
  229 #define IX_QMGR_ENTRY2_OFFSET 1
  230 #define IX_QMGR_ENTRY4_OFFSET 3
  231 
  232 typedef void qconfig_hand_t(int, void *);
  233 
  234 int     ixpqmgr_qconfig(int qId, int qSizeInWords, int ne, int nf, int srcSel,
  235             qconfig_hand_t *cb, void *cbarg);
  236 int     ixpqmgr_qwrite(int qId, uint32_t entry);
  237 int     ixpqmgr_qread(int qId, uint32_t *entry);
  238 int     ixpqmgr_qreadm(int qId, uint32_t n, uint32_t *p);
  239 uint32_t ixpqmgr_getqstatus(int qId);
  240 uint32_t ixpqmgr_getqconfig(int qId);
  241 void    ixpqmgr_notify_enable(int qId, int srcSel);
  242 void    ixpqmgr_notify_disable(int qId);
  243 void    ixpqmgr_dump(void);
  244 
  245 #endif /* ARM_XSCALE_IXP425_QMGR_H */

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