1 /* $NetBSD: ixp425reg.h,v 1.19 2005/12/11 12:16:51 christos Exp $ */
2 /*
3 * Copyright (c) 2003
4 * Ichiro FUKUHARA <ichiro@ichiro.org>.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Ichiro FUKUHARA.
18 * 4. The name of the company nor the name of the author may be used to
19 * endorse or promote products derived from this software without specific
20 * prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $FreeBSD$
35 *
36 */
37
38 #ifndef _IXP425REG_H_
39 #define _IXP425REG_H_
40
41 /*
42 * Physical memory map for the Intel IXP425
43 */
44 /*
45 * CC00 00FF ---------------------------
46 * SDRAM Configuration Registers
47 * CC00 0000 ---------------------------
48 *
49 * C800 BFFF ---------------------------
50 * System and Peripheral Registers
51 * C800 0000 ---------------------------
52 * Expansion Bus Configuration Registers
53 * C400 0000 ---------------------------
54 * PCI Configuration and Status Registers
55 * C000 0000 ---------------------------
56 *
57 * 6400 0000 ---------------------------
58 * Queue manager
59 * 6000 0000 ---------------------------
60 * Expansion Bus Data
61 * 5000 0000 ---------------------------
62 * PCI Data
63 * 4800 0000 ---------------------------
64 *
65 * 4000 0000 ---------------------------
66 * SDRAM
67 * 1000 0000 ---------------------------
68 */
69
70 /*
71 * Virtual memory map for the Intel IXP425 integrated devices
72 */
73 /*
74 * FFFF FFFF ---------------------------
75 *
76 * FC00 0000 ---------------------------
77 * PCI Data (memory space)
78 * F800 0000 ---------------------------
79 *
80 * F020 1000 ---------------------------
81 * SDRAM Controller
82 * F020 0000 ---------------------------
83 *
84 * F001 2000 ---------------------------
85 * PCI Configuration and Status Registers
86 * F001 1000 ---------------------------
87 * Expansion bus Configuration Registers
88 * F001 0000 ---------------------------
89 * System and Peripheral Registers
90 * VA F000 0000 = PA C800 0000 (SIZE 0x10000)
91 * F000 0000 ---------------------------
92 *
93 * 0000 0000 ---------------------------
94 *
95 */
96
97 /* Physical/Virtual address for I/O space */
98
99 #define IXP425_IO_VBASE 0xf0000000UL
100 #define IXP425_IO_HWBASE 0xc8000000UL
101 #define IXP425_IO_SIZE 0x00010000UL
102
103 /* Offset */
104
105 #define IXP425_UART0_OFFSET 0x00000000UL
106 #define IXP425_UART1_OFFSET 0x00001000UL
107 #define IXP425_PMC_OFFSET 0x00002000UL
108 #define IXP425_INTR_OFFSET 0x00003000UL
109 #define IXP425_GPIO_OFFSET 0x00004000UL
110 #define IXP425_TIMER_OFFSET 0x00005000UL
111 #define IXP425_NPE_A_OFFSET 0x00006000UL /* Not User Programmable */
112 #define IXP425_NPE_B_OFFSET 0x00007000UL /* Not User Programmable */
113 #define IXP425_NPE_C_OFFSET 0x00008000UL /* Not User Programmable */
114 #define IXP425_MAC_A_OFFSET 0x00009000UL
115 #define IXP425_MAC_B_OFFSET 0x0000a000UL
116 #define IXP425_USB_OFFSET 0x0000b000UL
117
118 #define IXP425_REG_SIZE 0x1000
119
120 /*
121 * UART
122 * UART0 0xc8000000
123 * UART1 0xc8001000
124 *
125 */
126 /* I/O space */
127 #define IXP425_UART0_HWBASE (IXP425_IO_HWBASE + IXP425_UART0_OFFSET)
128 #define IXP425_UART1_HWBASE (IXP425_IO_HWBASE + IXP425_UART1_OFFSET)
129
130 #define IXP425_UART0_VBASE (IXP425_IO_VBASE + IXP425_UART0_OFFSET)
131 /* 0xf0000000 */
132 #define IXP425_UART1_VBASE (IXP425_IO_VBASE + IXP425_UART1_OFFSET)
133 /* 0xf0001000 */
134
135 #define IXP425_UART_FREQ 14745600
136
137 #define IXP425_UART_IER 0x01 /* interrupt enable register */
138 #define IXP425_UART_IER_RTOIE 0x10 /* receiver timeout interrupt enable */
139 #define IXP425_UART_IER_UUE 0x40 /* UART Unit enable */
140
141 /*#define IXP4XX_COM_NPORTS 8*/
142
143 /*
144 * Timers
145 *
146 */
147 #define IXP425_TIMER_HWBASE (IXP425_IO_HWBASE + IXP425_TIMER_OFFSET)
148 #define IXP425_TIMER_VBASE (IXP425_IO_VBASE + IXP425_TIMER_OFFSET)
149
150 #define IXP425_OST_TS 0x0000
151 #define IXP425_OST_TIM0 0x0004
152 #define IXP425_OST_TIM1 0x000C
153
154 #define IXP425_OST_TIM0_RELOAD 0x0008
155 #define IXP425_OST_TIM1_RELOAD 0x0010
156 #define TIMERRELOAD_MASK 0xFFFFFFFC
157 #define OST_ONESHOT_EN (1U << 1)
158 #define OST_TIMER_EN (1U << 0)
159
160 #define IXP425_OST_STATUS 0x0020
161 #define OST_WARM_RESET (1U << 4)
162 #define OST_WDOG_INT (1U << 3)
163 #define OST_TS_INT (1U << 2)
164 #define OST_TIM1_INT (1U << 1)
165 #define OST_TIM0_INT (1U << 0)
166
167 #define IXP425_OST_WDOG 0x0014
168 #define IXP425_OST_WDOG_ENAB 0x0018
169 #define IXP425_OST_WDOG_KEY 0x001c
170 #define OST_WDOG_KEY_MAJICK 0x482e
171 #define OST_WDOG_ENAB_RST_ENA (1u << 0)
172 #define OST_WDOG_ENAB_INT_ENA (1u << 1)
173 #define OST_WDOG_ENAB_CNT_ENA (1u << 2)
174
175 /*
176 * Interrupt Controller Unit.
177 * PA 0xc8003000
178 */
179
180 #define IXP425_IRQ_HWBASE IXP425_IO_HWBASE + IXP425_INTR_OFFSET
181 #define IXP425_IRQ_VBASE IXP425_IO_VBASE + IXP425_INTR_OFFSET
182 /* 0xf0003000 */
183 #define IXP425_IRQ_SIZE 0x00000020UL
184
185 #define IXP425_INT_STATUS (IXP425_IRQ_VBASE + 0x00)
186 #define IXP425_INT_ENABLE (IXP425_IRQ_VBASE + 0x04)
187 #define IXP425_INT_SELECT (IXP425_IRQ_VBASE + 0x08)
188 #define IXP425_IRQ_STATUS (IXP425_IRQ_VBASE + 0x0C)
189 #define IXP425_FIQ_STATUS (IXP425_IRQ_VBASE + 0x10)
190 #define IXP425_INT_PRTY (IXP425_IRQ_VBASE + 0x14)
191 #define IXP425_IRQ_ENC (IXP425_IRQ_VBASE + 0x18)
192 #define IXP425_FIQ_ENC (IXP425_IRQ_VBASE + 0x1C)
193
194 #define IXP425_INT_SW1 31 /* SW Interrupt 1 */
195 #define IXP425_INT_SW0 30 /* SW Interrupt 0 */
196 #define IXP425_INT_GPIO_12 29 /* GPIO 12 */
197 #define IXP425_INT_GPIO_11 28 /* GPIO 11 */
198 #define IXP425_INT_GPIO_10 27 /* GPIO 11 */
199 #define IXP425_INT_GPIO_9 26 /* GPIO 9 */
200 #define IXP425_INT_GPIO_8 25 /* GPIO 8 */
201 #define IXP425_INT_GPIO_7 24 /* GPIO 7 */
202 #define IXP425_INT_GPIO_6 23 /* GPIO 6 */
203 #define IXP425_INT_GPIO_5 22 /* GPIO 5 */
204 #define IXP425_INT_GPIO_4 21 /* GPIO 4 */
205 #define IXP425_INT_GPIO_3 20 /* GPIO 3 */
206 #define IXP425_INT_GPIO_2 19 /* GPIO 2 */
207 #define IXP425_INT_XSCALE_PMU 18 /* XScale PMU */
208 #define IXP425_INT_AHB_PMU 17 /* AHB PMU */
209 #define IXP425_INT_WDOG 16 /* Watchdog Timer */
210 #define IXP425_INT_UART0 15 /* HighSpeed UART */
211 #define IXP425_INT_STAMP 14 /* Timestamp Timer */
212 #define IXP425_INT_UART1 13 /* Console UART */
213 #define IXP425_INT_USB 12 /* USB */
214 #define IXP425_INT_TMR1 11 /* General-Purpose Timer1 */
215 #define IXP425_INT_PCIDMA2 10 /* PCI DMA Channel 2 */
216 #define IXP425_INT_PCIDMA1 9 /* PCI DMA Channel 1 */
217 #define IXP425_INT_PCIINT 8 /* PCI Interrupt */
218 #define IXP425_INT_GPIO_1 7 /* GPIO 1 */
219 #define IXP425_INT_GPIO_0 6 /* GPIO 0 */
220 #define IXP425_INT_TMR0 5 /* General-Purpose Timer0 */
221 #define IXP425_INT_QUE33_64 4 /* Queue Manager 33-64 */
222 #define IXP425_INT_QUE1_32 3 /* Queue Manager 1-32 */
223 #define IXP425_INT_NPE_C 2 /* NPE C */
224 #define IXP425_INT_NPE_B 1 /* NPE B */
225 #define IXP425_INT_NPE_A 0 /* NPE A */
226
227 /*
228 * software interrupt
229 */
230 #define IXP425_INT_bit31 31
231 #define IXP425_INT_bit30 30
232 #define IXP425_INT_bit14 14
233 #define IXP425_INT_bit11 11
234
235 #define IXP425_INT_HWMASK (0xffffffff & \
236 ~((1 << IXP425_INT_bit31) | \
237 (1 << IXP425_INT_bit30) | \
238 (1 << IXP425_INT_bit14) | \
239 (1 << IXP425_INT_bit11)))
240 #define IXP425_INT_GPIOMASK (0x3ff800c0u)
241
242 /*
243 * GPIO
244 */
245 #define IXP425_GPIO_HWBASE IXP425_IO_HWBASE + IXP425_GPIO_OFFSET
246 #define IXP425_GPIO_VBASE IXP425_IO_VBASE + IXP425_GPIO_OFFSET
247 /* 0xf0004000 */
248 #define IXP425_GPIO_SIZE 0x00000020UL
249
250 #define IXP425_GPIO_GPOUTR 0x00
251 #define IXP425_GPIO_GPOER 0x04
252 #define IXP425_GPIO_GPINR 0x08
253 #define IXP425_GPIO_GPISR 0x0c
254 #define IXP425_GPIO_GPIT1R 0x10
255 #define IXP425_GPIO_GPIT2R 0x14
256 #define IXP425_GPIO_GPCLKR 0x18
257 # define GPCLKR_MUX14 (1U << 8)
258 # define GPCLKR_CLK0TC_SHIFT 4
259 # define GPCLKR_CLK0DC_SHIFT 0
260
261 /* GPIO Output */
262 #define GPOUT_ON 0x1
263 #define GPOUT_OFF 0x0
264
265 /* GPIO direction */
266 #define GPOER_INPUT 0x1
267 #define GPOER_OUTPUT 0x0
268
269 /* GPIO Type bits */
270 #define GPIO_TYPE_ACT_HIGH 0x0
271 #define GPIO_TYPE_ACT_LOW 0x1
272 #define GPIO_TYPE_EDG_RISING 0x2
273 #define GPIO_TYPE_EDG_FALLING 0x3
274 #define GPIO_TYPE_TRANSITIONAL 0x4
275 #define GPIO_TYPE_MASK 0x7
276 #define GPIO_TYPE(b,v) ((v) << (((b) & 0x7) * 3))
277 #define GPIO_TYPE_REG(b) (((b)&8)?IXP425_GPIO_GPIT2R:IXP425_GPIO_GPIT1R)
278
279 /*
280 * Expansion Bus Configuration Space.
281 */
282 #define IXP425_EXP_HWBASE 0xc4000000UL
283 #define IXP425_EXP_VBASE (IXP425_IO_VBASE + IXP425_IO_SIZE)
284 /* 0xf0010000 */
285 #define IXP425_EXP_SIZE IXP425_REG_SIZE /* 0x1000 */
286
287 /* offset */
288 #define EXP_TIMING_CS0_OFFSET 0x0000
289 #define EXP_TIMING_CS1_OFFSET 0x0004
290 #define EXP_TIMING_CS2_OFFSET 0x0008
291 #define EXP_TIMING_CS3_OFFSET 0x000c
292 #define EXP_TIMING_CS4_OFFSET 0x0010
293 #define EXP_TIMING_CS5_OFFSET 0x0014
294 #define EXP_TIMING_CS6_OFFSET 0x0018
295 #define EXP_TIMING_CS7_OFFSET 0x001c
296 #define EXP_CNFG0_OFFSET 0x0020
297 #define EXP_CNFG1_OFFSET 0x0024
298 #define EXP_FCTRL_OFFSET 0x0028
299
300 #define IXP425_EXP_RECOVERY_SHIFT 16
301 #define IXP425_EXP_HOLD_SHIFT 20
302 #define IXP425_EXP_STROBE_SHIFT 22
303 #define IXP425_EXP_SETUP_SHIFT 26
304 #define IXP425_EXP_ADDR_SHIFT 28
305 #define IXP425_EXP_CS_EN (1U << 31)
306
307 #define IXP425_EXP_RECOVERY_T(x) (((x) & 15) << IXP425_EXP_RECOVERY_SHIFT)
308 #define IXP425_EXP_HOLD_T(x) (((x) & 3) << IXP425_EXP_HOLD_SHIFT)
309 #define IXP425_EXP_STROBE_T(x) (((x) & 15) << IXP425_EXP_STROBE_SHIFT)
310 #define IXP425_EXP_SETUP_T(x) (((x) & 3) << IXP425_EXP_SETUP_SHIFT)
311 #define IXP425_EXP_ADDR_T(x) (((x) & 3) << IXP425_EXP_ADDR_SHIFT)
312
313 /* EXP_CSn bits */
314 #define EXP_BYTE_EN 0x00000001 /* bus uses only 8-bit data */
315 #define EXP_WR_EN 0x00000002 /* ena writes to CS region */
316 /* bit 2 is reserved */
317 #define EXP_SPLT_EN 0x00000008 /* ena AHB split transfers */
318 #define EXP_MUX_EN 0x00000010 /* multiplexed address/data */
319 #define EXP_HRDY_POL 0x00000020 /* HPI|HRDY polarity */
320 #define EXP_BYTE_RD16 0x00000040 /* byte rd access to word dev */
321 #define EXP_CNFG 0x00003c00 /* device config size */
322 #define EXP_SZ_512 (0 << 10)
323 #define EXP_SZ_1K (1 << 10)
324 #define EXP_SZ_2K (2 << 10)
325 #define EXP_SZ_4K (3 << 10)
326 #define EXP_SZ_8K (4 << 10)
327 #define EXP_SZ_16K (5 << 10)
328 #define EXP_SZ_32K (6 << 10)
329 #define EXP_SZ_64K (7 << 10)
330 #define EXP_SZ_128K (8 << 10)
331 #define EXP_SZ_256K (9 << 10)
332 #define EXP_SZ_512K (10 << 10)
333 #define EXP_SZ_1M (11 << 10)
334 #define EXP_SZ_2M (12 << 10)
335 #define EXP_SZ_4M (13 << 10)
336 #define EXP_SZ_8M (14 << 10)
337 #define EXP_SZ_16M (15 << 10)
338 #define EXP_CYC_TYPE 0x0000c000 /* bus cycle "type" */
339 #define EXP_CYC_INTEL (0 << 14)
340 #define EXP_CYC_MOTO (1 << 14)
341 #define EXP_CYC_HPI (2 << 14)
342 #define EXP_T5 0x000f0000 /* recovery timing */
343 #define EXP_T4 0x00300000 /* hold timing */
344 #define EXP_T3 0x03c00000 /* strobe timing */
345 #define EXP_T2 0x0c000000 /* setup/chip select timing */
346 #define EXP_T1 0x30000000 /* address timing */
347 /* bit 30 is reserved */
348 #define EXP_CS_EN 0x80000000 /* chip select enabled */
349
350 /* EXP_CNFG0 bits */
351 #define EXP_CNFG0_8BIT (1 << 0)
352 #define EXP_CNFG0_PCI_HOST (1 << 1)
353 #define EXP_CNFG0_PCI_ARB (1 << 2)
354 #define EXP_CNFG0_PCI_66MHZ (1 << 4)
355 #define EXP_CNFG0_MEM_MAP (1 << 31)
356
357 /* EXP_CNFG1 bits */
358 #define EXP_CNFG1_SW_INT0 (1 << 0)
359 #define EXP_CNFG1_SW_INT1 (1 << 1)
360
361 #define EXP_FCTRL_RCOMP (1<<0)
362 #define EXP_FCTRL_USB (1<<1)
363 #define EXP_FCTRL_HASH (1<<2)
364 #define EXP_FCTRL_AES (1<<3)
365 #define EXP_FCTRL_DES (1<<4)
366 #define EXP_FCTRL_HDLC (1<<5)
367 #define EXP_FCTRL_AAL (1<<6)
368 #define EXP_FCTRL_HSS (1<<7)
369 #define EXP_FCTRL_UTOPIA (1<<8)
370 #define EXP_FCTRL_ETH0 (1<<9)
371 #define EXP_FCTRL_ETH1 (1<<10)
372 #define EXP_FCTRL_NPEA (1<<11)
373 #define EXP_FCTRL_NPEB (1<<12)
374 #define EXP_FCTRL_NPEC (1<<13)
375 #define EXP_FCTRL_PCI (1<<14)
376 /* XXX more stuff we don't care about */
377
378 /*
379 * PCI
380 */
381 #define IXP425_PCI_HWBASE 0xc0000000
382 #define IXP425_PCI_VBASE (IXP425_EXP_VBASE + IXP425_EXP_SIZE)
383 /* 0xf0011000 */
384 #define IXP425_PCI_SIZE IXP425_REG_SIZE /* 0x1000 */
385
386 /*
387 * Mapping registers of IXP425 PCI Configuration
388 */
389 /* PCI_ID_REG 0x00 */
390 /* PCI_COMMAND_STATUS_REG 0x04 */
391 /* PCI_CLASS_REG 0x08 */
392 /* PCI_BHLC_REG 0x0c */
393 #define PCI_MAPREG_BAR0 0x10 /* Base Address 0 */
394 #define PCI_MAPREG_BAR1 0x14 /* Base Address 1 */
395 #define PCI_MAPREG_BAR2 0x18 /* Base Address 2 */
396 #define PCI_MAPREG_BAR3 0x1c /* Base Address 3 */
397 #define PCI_MAPREG_BAR4 0x20 /* Base Address 4 */
398 #define PCI_MAPREG_BAR5 0x24 /* Base Address 5 */
399 /* PCI_SUBSYS_ID_REG 0x2c */
400 /* PCI_INTERRUPT_REG 0x3c */
401 #define PCI_RTOTTO 0x40
402
403 /* PCI Controller CSR Base Address */
404 #define IXP425_PCI_CSR_BASE IXP425_PCI_VBASE
405
406 /* PCI Memory Space */
407 #define IXP425_PCI_MEM_HWBASE 0x48000000UL
408 #define IXP425_PCI_MEM_VBASE 0xf8000000UL
409 #define IXP425_PCI_MEM_SIZE 0x04000000UL /* 64MB */
410
411 /* PCI I/O Space */
412 #define IXP425_PCI_IO_HWBASE 0x00000000UL
413 #define IXP425_PCI_IO_SIZE 0x00100000UL /* 1Mbyte */
414
415 /* PCI Controller Configuration Offset */
416 #define PCI_NP_AD 0x00
417 #define PCI_NP_CBE 0x04
418 # define NP_CBE_SHIFT 4
419 #define PCI_NP_WDATA 0x08
420 #define PCI_NP_RDATA 0x0c
421 #define PCI_CRP_AD_CBE 0x10
422 #define PCI_CRP_AD_WDATA 0x14
423 #define PCI_CRP_AD_RDATA 0x18
424 #define PCI_CSR 0x1c
425 # define CSR_PRST (1U << 16)
426 # define CSR_IC (1U << 15)
427 # define CSR_ABE (1U << 4)
428 # define CSR_PDS (1U << 3)
429 # define CSR_ADS (1U << 2)
430 # define CSR_HOST (1U << 0)
431 #define PCI_ISR 0x20
432 # define ISR_AHBE (1U << 3)
433 # define ISR_PPE (1U << 2)
434 # define ISR_PFE (1U << 1)
435 # define ISR_PSE (1U << 0)
436 #define PCI_INTEN 0x24
437 #define PCI_DMACTRL 0x28
438 #define PCI_AHBMEMBASE 0x2c
439 #define PCI_AHBIOBASE 0x30
440 #define PCI_PCIMEMBASE 0x34
441 #define PCI_AHBDOORBELL 0x38
442 #define PCI_PCIDOORBELL 0x3c
443 #define PCI_ATPDMA0_AHBADDR 0x40
444 #define PCI_ATPDMA0_PCIADDR 0x44
445 #define PCI_ATPDMA0_LENGTH 0x48
446 #define PCI_ATPDMA1_AHBADDR 0x4c
447 #define PCI_ATPDMA1_PCIADDR 0x50
448 #define PCI_ATPDMA1_LENGTH 0x54
449 #define PCI_PTADMA0_AHBADDR 0x58
450 #define PCI_PTADMA0_PCIADDR 0x5c
451 #define PCI_PTADMA0_LENGTH 0x60
452 #define PCI_PTADMA1_AHBADDR 0x64
453 #define PCI_PTADMA1_PCIADDR 0x68
454 #define PCI_PTADMA1_LENGTH 0x6c
455
456 /* PCI target(T)/initiator(I) Interface Commands for PCI_NP_CBE register */
457 #define COMMAND_NP_IA 0x0 /* Interrupt Acknowledge (I)*/
458 #define COMMAND_NP_SC 0x1 /* Special Cycle (I)*/
459 #define COMMAND_NP_IO_READ 0x2 /* I/O Read (T)(I) */
460 #define COMMAND_NP_IO_WRITE 0x3 /* I/O Write (T)(I) */
461 #define COMMAND_NP_MEM_READ 0x6 /* Memory Read (T)(I) */
462 #define COMMAND_NP_MEM_WRITE 0x7 /* Memory Write (T)(I) */
463 #define COMMAND_NP_CONF_READ 0xa /* Configuration Read (T)(I) */
464 #define COMMAND_NP_CONF_WRITE 0xb /* Configuration Write (T)(I) */
465
466 /* PCI byte enables */
467 #define BE_8BIT(a) ((0x10u << ((a) & 0x03)) ^ 0xf0)
468 #define BE_16BIT(a) ((0x30u << ((a) & 0x02)) ^ 0xf0)
469 #define BE_32BIT(a) 0x00
470
471 /* PCI byte selects */
472 #define READ_8BIT(v,a) ((u_int8_t)((v) >> (((a) & 3) * 8)))
473 #define READ_16BIT(v,a) ((u_int16_t)((v) >> (((a) & 2) * 8)))
474 #define WRITE_8BIT(v,a) (((u_int32_t)(v)) << (((a) & 3) * 8))
475 #define WRITE_16BIT(v,a) (((u_int32_t)(v)) << (((a) & 2) * 8))
476
477 /* PCI Controller Configuration Commands for PCI_CRP_AD_CBE */
478 #define COMMAND_CRP_READ 0x00
479 #define COMMAND_CRP_WRITE (1U << 16)
480
481 /*
482 * SDRAM Configuration Register
483 */
484 #define IXP425_MCU_HWBASE 0xcc000000UL
485 #define IXP425_MCU_VBASE 0xf0200000UL
486 #define IXP425_MCU_SIZE 0x1000 /* Actually only 256 bytes */
487 #define MCU_SDR_CONFIG 0x00
488 #define MCU_SDR_CONFIG_MCONF(x) ((x) & 0x7)
489 #define MCU_SDR_CONFIG_64MBIT (1u << 5)
490 #define MCU_SDR_REFRESH 0x04
491 #define MCU_SDR_IR 0x08
492
493 /*
494 * Performance Monitoring Unit (CP14)
495 *
496 * CP14.0.1 Performance Monitor Control Register(PMNC)
497 * CP14.1.1 Clock Counter(CCNT)
498 * CP14.4.1 Interrupt Enable Register(INTEN)
499 * CP14.5.1 Overflow Flag Register(FLAG)
500 * CP14.8.1 Event Selection Register(EVTSEL)
501 * CP14.0.2 Performance Counter Register 0(PMN0)
502 * CP14.1.2 Performance Counter Register 0(PMN1)
503 * CP14.2.2 Performance Counter Register 0(PMN2)
504 * CP14.3.2 Performance Counter Register 0(PMN3)
505 */
506
507 #define PMNC_E 0x00000001 /* enable all counters */
508 #define PMNC_P 0x00000002 /* reset all PMNs to 0 */
509 #define PMNC_C 0x00000004 /* clock counter reset */
510 #define PMNC_D 0x00000008 /* clock counter / 64 */
511
512 #define INTEN_CC_IE 0x00000001 /* enable clock counter interrupt */
513 #define INTEN_PMN0_IE 0x00000002 /* enable PMN0 interrupt */
514 #define INTEN_PMN1_IE 0x00000004 /* enable PMN1 interrupt */
515 #define INTEN_PMN2_IE 0x00000008 /* enable PMN2 interrupt */
516 #define INTEN_PMN3_IE 0x00000010 /* enable PMN3 interrupt */
517
518 #define FLAG_CC_IF 0x00000001 /* clock counter overflow */
519 #define FLAG_PMN0_IF 0x00000002 /* PMN0 overflow */
520 #define FLAG_PMN1_IF 0x00000004 /* PMN1 overflow */
521 #define FLAG_PMN2_IF 0x00000008 /* PMN2 overflow */
522 #define FLAG_PMN3_IF 0x00000010 /* PMN3 overflow */
523
524 #define EVTSEL_EVCNT_MASK 0x0000000ff /* event to count for PMNs */
525 #define PMNC_EVCNT0_SHIFT 0
526 #define PMNC_EVCNT1_SHIFT 8
527 #define PMNC_EVCNT2_SHIFT 16
528 #define PMNC_EVCNT3_SHIFT 24
529
530 /*
531 * Queue Manager
532 */
533 #define IXP425_QMGR_HWBASE 0x60000000UL
534 #define IXP425_QMGR_VBASE (IXP425_PCI_VBASE + IXP425_PCI_SIZE)
535 #define IXP425_QMGR_SIZE 0x4000
536
537 /*
538 * Network Processing Engines (NPE's) and associated Ethernet MAC's.
539 */
540 #define IXP425_NPE_A_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_A_OFFSET)
541 #define IXP425_NPE_A_VBASE (IXP425_IO_VBASE + IXP425_NPE_A_OFFSET)
542 #define IXP425_NPE_A_SIZE 0x1000 /* Actually only 256 bytes */
543
544 #define IXP425_NPE_B_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_B_OFFSET)
545 #define IXP425_NPE_B_VBASE (IXP425_IO_VBASE + IXP425_NPE_B_OFFSET)
546 #define IXP425_NPE_B_SIZE 0x1000 /* Actually only 256 bytes */
547
548 #define IXP425_NPE_C_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_C_OFFSET)
549 #define IXP425_NPE_C_VBASE (IXP425_IO_VBASE + IXP425_NPE_C_OFFSET)
550 #define IXP425_NPE_C_SIZE 0x1000 /* Actually only 256 bytes */
551
552 #define IXP425_MAC_A_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_A_OFFSET)
553 #define IXP425_MAC_A_VBASE (IXP425_IO_VBASE + IXP425_MAC_A_OFFSET)
554 #define IXP425_MAC_A_SIZE 0x1000 /* Actually only 256 bytes */
555
556 #define IXP425_MAC_B_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_B_OFFSET)
557 #define IXP425_MAC_B_VBASE (IXP425_IO_VBASE + IXP425_MAC_B_OFFSET)
558 #define IXP425_MAC_B_SIZE 0x1000 /* Actually only 256 bytes */
559
560 /*
561 * Expansion Bus Data Space.
562 */
563 #define IXP425_EXP_BUS_HWBASE 0x50000000UL
564 #define IXP425_EXP_BUS_SIZE 0x01000000 /* max, typically smaller */
565
566 #define IXP425_EXP_BUS_CSx_HWBASE(i) \
567 (IXP425_EXP_BUS_HWBASE + (i)*IXP425_EXP_BUS_SIZE)
568
569 #define IXP425_EXP_BUS_CSx_VBASE(i) \
570 (IXP425_MAC_B_VBASE + (i)*IXP425_MAC_B_SIZE)
571
572 #define IXP425_EXP_BUS_CS1_HWBASE IXP425_EXP_BUS_CSx_HWBASE(1)
573 #define IXP425_EXP_BUS_CS1_VBASE IXP425_EXP_BUS_CSx_VBASE(1)
574 #define IXP425_EXP_BUS_CS1_SIZE 0x1000
575 #define IXP425_EXP_BUS_CS2_HWBASE IXP425_EXP_BUS_CSx_HWBASE(2)
576 #define IXP425_EXP_BUS_CS2_VBASE IXP425_EXP_BUS_CSx_VBASE(2)
577 #define IXP425_EXP_BUS_CS2_SIZE 0x1000
578 #define IXP425_EXP_BUS_CS3_HWBASE IXP425_EXP_BUS_CSx_HWBASE(3)
579 #define IXP425_EXP_BUS_CS3_VBASE IXP425_EXP_BUS_CSx_VBASE(3)
580 #define IXP425_EXP_BUS_CS3_SIZE 0x1000
581 #define IXP425_EXP_BUS_CS4_HWBASE IXP425_EXP_BUS_CSx_HWBASE(4)
582 #define IXP425_EXP_BUS_CS4_VBASE IXP425_EXP_BUS_CSx_VBASE(4)
583 #define IXP425_EXP_BUS_CS4_SIZE 0x1000
584
585 /* NB: not mapped (yet) */
586 #define IXP425_EXP_BUS_CS0_HWBASE IXP425_EXP_BUS_CSx_HWBASE(0)
587 #define IXP425_EXP_BUS_CS5_HWBASE IXP425_EXP_BUS_CSx_HWBASE(5)
588 #define IXP425_EXP_BUS_CS6_HWBASE IXP425_EXP_BUS_CSx_HWBASE(6)
589 #define IXP425_EXP_BUS_CS7_HWBASE IXP425_EXP_BUS_CSx_HWBASE(7)
590
591 #endif /* _IXP425REG_H_ */
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