1 /* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */
2
3 /*-
4 * Copyright (c) 1994-1998 Mark Brinicombe.
5 * Copyright (c) 1994 Brini.
6 * All rights reserved.
7 *
8 * This code is derived from software written for Brini by Mark Brinicombe
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Brini.
21 * 4. The name of the company nor the name of the author may be used to
22 * endorse or promote products derived from this software without specific
23 * prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * RiscBSD kernel project
38 *
39 * machdep.c
40 *
41 * Machine dependant functions for kernel setup
42 *
43 * This file needs a lot of work.
44 *
45 * Created : 17/09/94
46 */
47
48 #include "opt_ddb.h"
49
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD: releng/10.0/sys/arm/xscale/pxa/pxa_machdep.c 247564 2013-03-01 19:02:41Z alc $");
52
53 #define _ARM32_BUS_DMA_PRIVATE
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/sysproto.h>
57 #include <sys/signalvar.h>
58 #include <sys/imgact.h>
59 #include <sys/kernel.h>
60 #include <sys/ktr.h>
61 #include <sys/linker.h>
62 #include <sys/lock.h>
63 #include <sys/malloc.h>
64 #include <sys/mutex.h>
65 #include <sys/pcpu.h>
66 #include <sys/proc.h>
67 #include <sys/ptrace.h>
68 #include <sys/cons.h>
69 #include <sys/bio.h>
70 #include <sys/bus.h>
71 #include <sys/buf.h>
72 #include <sys/exec.h>
73 #include <sys/kdb.h>
74 #include <sys/msgbuf.h>
75 #include <machine/reg.h>
76 #include <machine/cpu.h>
77
78 #include <vm/vm.h>
79 #include <vm/pmap.h>
80 #include <vm/vm_object.h>
81 #include <vm/vm_page.h>
82 #include <vm/vm_map.h>
83 #include <machine/vmparam.h>
84 #include <machine/pcb.h>
85 #include <machine/undefined.h>
86 #include <machine/machdep.h>
87 #include <machine/metadata.h>
88 #include <machine/armreg.h>
89 #include <machine/bus.h>
90 #include <sys/reboot.h>
91
92 #include <arm/xscale/pxa/pxareg.h>
93 #include <arm/xscale/pxa/pxavar.h>
94
95 #define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
96 #define KERNEL_PT_IOPXS 1
97 #define KERNEL_PT_BEFOREKERN 2
98 #define KERNEL_PT_AFKERNEL 3 /* L2 table for mapping after kernel */
99 #define KERNEL_PT_AFKERNEL_NUM 9
100
101 /* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
102 #define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
103
104 extern u_int data_abort_handler_address;
105 extern u_int prefetch_abort_handler_address;
106 extern u_int undefined_handler_address;
107
108 struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
109
110 /* Physical and virtual addresses for some global pages */
111
112 vm_paddr_t phys_avail[PXA2X0_SDRAM_BANKS * 2 + 4];
113 vm_paddr_t dump_avail[PXA2X0_SDRAM_BANKS * 2 + 4];
114
115 struct pv_addr systempage;
116 struct pv_addr msgbufpv;
117 struct pv_addr irqstack;
118 struct pv_addr undstack;
119 struct pv_addr abtstack;
120 struct pv_addr kernelstack;
121 struct pv_addr minidataclean;
122
123 static void pxa_probe_sdram(bus_space_tag_t, bus_space_handle_t,
124 uint32_t *, uint32_t *);
125
126 /* Static device mappings. */
127 static const struct pmap_devmap pxa_devmap[] = {
128 /*
129 * Map the on-board devices up into the KVA region so we don't muck
130 * up user-space.
131 */
132 {
133 PXA2X0_PERIPH_START + PXA2X0_PERIPH_OFFSET,
134 PXA2X0_PERIPH_START,
135 PXA250_PERIPH_END - PXA2X0_PERIPH_START,
136 VM_PROT_READ|VM_PROT_WRITE,
137 PTE_NOCACHE,
138 },
139 { 0, 0, 0, 0, 0, }
140 };
141
142 #define SDRAM_START 0xa0000000
143
144 extern vm_offset_t xscale_cache_clean_addr;
145
146 void *
147 initarm(struct arm_boot_params *abp)
148 {
149 struct pv_addr kernel_l1pt;
150 struct pv_addr dpcpu;
151 int loop;
152 u_int l1pagetable;
153 vm_offset_t freemempos;
154 vm_offset_t freemem_pt;
155 vm_offset_t afterkern;
156 vm_offset_t freemem_after;
157 vm_offset_t lastaddr;
158 int i, j;
159 uint32_t memsize[PXA2X0_SDRAM_BANKS], memstart[PXA2X0_SDRAM_BANKS];
160
161 lastaddr = parse_boot_param(abp);
162 set_cpufuncs();
163 pcpu_init(pcpup, 0, sizeof(struct pcpu));
164 PCPU_SET(curthread, &thread0);
165
166 /* Do basic tuning, hz etc */
167 init_param1();
168
169 freemempos = 0xa0200000;
170 /* Define a macro to simplify memory allocation */
171 #define valloc_pages(var, np) \
172 alloc_pages((var).pv_pa, (np)); \
173 (var).pv_va = (var).pv_pa + 0x20000000;
174
175 #define alloc_pages(var, np) \
176 freemempos -= (np * PAGE_SIZE); \
177 (var) = freemempos; \
178 memset((char *)(var), 0, ((np) * PAGE_SIZE));
179
180 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
181 freemempos -= PAGE_SIZE;
182 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
183 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
184 if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
185 valloc_pages(kernel_pt_table[loop],
186 L2_TABLE_SIZE / PAGE_SIZE);
187 } else {
188 kernel_pt_table[loop].pv_pa = freemempos +
189 (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
190 L2_TABLE_SIZE_REAL;
191 kernel_pt_table[loop].pv_va =
192 kernel_pt_table[loop].pv_pa + 0x20000000;
193 }
194 }
195 freemem_pt = freemempos;
196 freemempos = 0xa0100000;
197 /*
198 * Allocate a page for the system page mapped to V0x00000000
199 * This page will just contain the system vectors and can be
200 * shared by all processes.
201 */
202 valloc_pages(systempage, 1);
203
204 /* Allocate dynamic per-cpu area. */
205 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
206 dpcpu_init((void *)dpcpu.pv_va, 0);
207
208 /* Allocate stacks for all modes */
209 valloc_pages(irqstack, IRQ_STACK_SIZE);
210 valloc_pages(abtstack, ABT_STACK_SIZE);
211 valloc_pages(undstack, UND_STACK_SIZE);
212 valloc_pages(kernelstack, KSTACK_PAGES);
213 alloc_pages(minidataclean.pv_pa, 1);
214 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
215 #ifdef ARM_USE_SMALL_ALLOC
216 freemempos -= PAGE_SIZE;
217 freemem_pt = trunc_page(freemem_pt);
218 freemem_after = freemempos - ((freemem_pt - 0xa0100000) /
219 PAGE_SIZE) * sizeof(struct arm_small_page);
220 arm_add_smallalloc_pages((void *)(freemem_after + 0x20000000)
221 , (void *)0xc0100000, freemem_pt - 0xa0100000, 1);
222 freemem_after -= ((freemem_after - 0xa0001000) / PAGE_SIZE) *
223 sizeof(struct arm_small_page);
224 arm_add_smallalloc_pages((void *)(freemem_after + 0x20000000)
225 , (void *)0xc0001000, trunc_page(freemem_after) - 0xa0001000, 0);
226 freemempos = trunc_page(freemem_after);
227 freemempos -= PAGE_SIZE;
228 #endif
229 /*
230 * Allocate memory for the l1 and l2 page tables. The scheme to avoid
231 * wasting memory by allocating the l1pt on the first 16k memory was
232 * taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for
233 * this to work (which is supposed to be the case).
234 */
235
236 /*
237 * Now we start construction of the L1 page table
238 * We start by mapping the L2 page tables into the L1.
239 * This means that we can replace L1 mappings later on if necessary
240 */
241 l1pagetable = kernel_l1pt.pv_va;
242
243 /* Map the L2 pages tables in the L1 page table */
244 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
245 &kernel_pt_table[KERNEL_PT_SYS]);
246 #if 0 /* XXXBJR: What is this? Don't know if there's an analogue. */
247 pmap_link_l2pt(l1pagetable, IQ80321_IOPXS_VBASE,
248 &kernel_pt_table[KERNEL_PT_IOPXS]);
249 #endif
250 pmap_link_l2pt(l1pagetable, KERNBASE,
251 &kernel_pt_table[KERNEL_PT_BEFOREKERN]);
252 pmap_map_chunk(l1pagetable, KERNBASE, SDRAM_START, 0x100000,
253 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
254 pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, SDRAM_START + 0x100000,
255 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
256 pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, SDRAM_START + 0x200000,
257 (((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1),
258 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
259 freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
260 afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) &
261 ~(L1_S_SIZE - 1));
262 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
263 pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
264 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
265 }
266 pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
267 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
268
269 #ifdef ARM_USE_SMALL_ALLOC
270 if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) {
271 arm_add_smallalloc_pages((void *)(freemem_after),
272 (void*)(freemem_after + PAGE_SIZE),
273 afterkern - (freemem_after + PAGE_SIZE), 0);
274 }
275 #endif
276
277 /* Map the Mini-Data cache clean area. */
278 xscale_setup_minidata(l1pagetable, afterkern,
279 minidataclean.pv_pa);
280
281 /* Map the vector page. */
282 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
283 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
284 pmap_devmap_bootstrap(l1pagetable, pxa_devmap);
285
286 /*
287 * Give the XScale global cache clean code an appropriately
288 * sized chunk of unmapped VA space starting at 0xff000000
289 * (our device mappings end before this address).
290 */
291 xscale_cache_clean_addr = 0xff000000U;
292
293 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
294 setttb(kernel_l1pt.pv_pa);
295 cpu_tlb_flushID();
296 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
297
298 /*
299 * Pages were allocated during the secondary bootstrap for the
300 * stacks for different CPU modes.
301 * We must now set the r13 registers in the different CPU modes to
302 * point to these stacks.
303 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
304 * of the stack memory.
305 */
306 set_stackptrs(0);
307
308 /*
309 * We must now clean the cache again....
310 * Cleaning may be done by reading new data to displace any
311 * dirty data in the cache. This will have happened in setttb()
312 * but since we are boot strapping the addresses used for the read
313 * may have just been remapped and thus the cache could be out
314 * of sync. A re-clean after the switch will cure this.
315 * After booting there are no gross relocations of the kernel thus
316 * this problem will not occur after initarm().
317 */
318 cpu_idcache_wbinv_all();
319
320 /*
321 * Sort out bus_space for on-board devices.
322 */
323 pxa_obio_tag_init();
324
325 /*
326 * Fetch the SDRAM start/size from the PXA2X0 SDRAM configration
327 * registers.
328 */
329 pxa_probe_sdram(obio_tag, PXA2X0_MEMCTL_BASE, memstart, memsize);
330
331 physmem = 0;
332 for (i = 0; i < PXA2X0_SDRAM_BANKS; i++) {
333 physmem += memsize[i] / PAGE_SIZE;
334 }
335
336 /* Fire up consoles. */
337 cninit();
338
339 /* Set stack for exception handlers */
340 data_abort_handler_address = (u_int)data_abort_handler;
341 prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
342 undefined_handler_address = (u_int)undefinedinstruction_bounce;
343 undefined_init();
344
345 init_proc0(kernelstack.pv_va);
346
347 /* Enable MMU, I-cache, D-cache, write buffer. */
348 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
349
350 pmap_curmaxkvaddr = afterkern + PAGE_SIZE;
351 /*
352 * ARM USE_SMALL_ALLOC uses dump_avail, so it must be filled before
353 * calling pmap_bootstrap.
354 */
355 i = 0;
356 for (j = 0; j < PXA2X0_SDRAM_BANKS; j++) {
357 if (memsize[j] > 0) {
358 dump_avail[i++] = round_page(memstart[j]);
359 dump_avail[i++] =
360 trunc_page(memstart[j] + memsize[j]);
361 }
362 }
363 dump_avail[i] = 0;
364 dump_avail[i] = 0;
365 vm_max_kernel_address = 0xd0000000;
366 pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt);
367 msgbufp = (void*)msgbufpv.pv_va;
368 msgbufinit(msgbufp, msgbufsize);
369 mutex_init();
370
371 i = 0;
372 #ifdef ARM_USE_SMALL_ALLOC
373 phys_avail[i++] = 0xa0000000;
374 phys_avail[i++] = 0xa0001000; /*
375 *XXX: Gross hack to get our
376 * pages in the vm_page_array
377 . */
378 #endif
379 for (j = 0; j < PXA2X0_SDRAM_BANKS; j++) {
380 if (memsize[j] > 0) {
381 phys_avail[i] = round_page(memstart[j]);
382 dump_avail[i++] = round_page(memstart[j]);
383 phys_avail[i] =
384 trunc_page(memstart[j] + memsize[j]);
385 dump_avail[i++] =
386 trunc_page(memstart[j] + memsize[j]);
387 }
388 }
389
390 dump_avail[i] = 0;
391 phys_avail[i++] = 0;
392 dump_avail[i] = 0;
393 phys_avail[i] = 0;
394 #ifdef ARM_USE_SMALL_ALLOC
395 phys_avail[2] = round_page(virtual_avail - KERNBASE + phys_avail[2]);
396 #else
397 phys_avail[0] = round_page(virtual_avail - KERNBASE + phys_avail[0]);
398 #endif
399
400 init_param2(physmem);
401 kdb_init();
402 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
403 sizeof(struct pcb)));
404 }
405
406 static void
407 pxa_probe_sdram(bus_space_tag_t bst, bus_space_handle_t bsh,
408 uint32_t *memstart, uint32_t *memsize)
409 {
410 uint32_t mdcnfg, dwid, dcac, drac, dnb;
411 int i;
412
413 mdcnfg = bus_space_read_4(bst, bsh, MEMCTL_MDCNFG);
414
415 /*
416 * Scan all 4 SDRAM banks
417 */
418 for (i = 0; i < PXA2X0_SDRAM_BANKS; i++) {
419 memstart[i] = 0;
420 memsize[i] = 0;
421
422 switch (i) {
423 case 0:
424 case 1:
425 if ((i == 0 && (mdcnfg & MDCNFG_DE0) == 0) ||
426 (i == 1 && (mdcnfg & MDCNFG_DE1) == 0))
427 continue;
428 dwid = mdcnfg >> MDCNFD_DWID01_SHIFT;
429 dcac = mdcnfg >> MDCNFD_DCAC01_SHIFT;
430 drac = mdcnfg >> MDCNFD_DRAC01_SHIFT;
431 dnb = mdcnfg >> MDCNFD_DNB01_SHIFT;
432 break;
433
434 case 2:
435 case 3:
436 if ((i == 2 && (mdcnfg & MDCNFG_DE2) == 0) ||
437 (i == 3 && (mdcnfg & MDCNFG_DE3) == 0))
438 continue;
439 dwid = mdcnfg >> MDCNFD_DWID23_SHIFT;
440 dcac = mdcnfg >> MDCNFD_DCAC23_SHIFT;
441 drac = mdcnfg >> MDCNFD_DRAC23_SHIFT;
442 dnb = mdcnfg >> MDCNFD_DNB23_SHIFT;
443 break;
444 default:
445 panic("pxa_probe_sdram: impossible");
446 }
447
448 dwid = 2 << (1 - (dwid & MDCNFD_DWID_MASK)); /* 16/32 width */
449 dcac = 1 << ((dcac & MDCNFD_DCAC_MASK) + 8); /* 8-11 columns */
450 drac = 1 << ((drac & MDCNFD_DRAC_MASK) + 11); /* 11-13 rows */
451 dnb = 2 << (dnb & MDCNFD_DNB_MASK); /* # of banks */
452
453 memsize[i] = dwid * dcac * drac * dnb;
454 memstart[i] = PXA2X0_SDRAM0_START +
455 (i * PXA2X0_SDRAM_BANK_SIZE);
456 }
457 }
458
459 #define TIMER_FREQUENCY 3686400
460 #define UNIMPLEMENTED panic("%s: unimplemented", __func__)
461
462 /* XXXBJR: Belongs with DELAY in a timer.c of some sort. */
463 void
464 cpu_startprofclock(void)
465 {
466 UNIMPLEMENTED;
467 }
468
469 void
470 cpu_stopprofclock(void)
471 {
472 UNIMPLEMENTED;
473 }
474
475 static struct arm32_dma_range pxa_range = {
476 .dr_sysbase = 0,
477 .dr_busbase = 0,
478 .dr_len = ~0u,
479 };
480
481 struct arm32_dma_range *
482 bus_dma_get_range(void)
483 {
484
485 return (&pxa_range);
486 }
487
488 int
489 bus_dma_get_range_nb(void)
490 {
491
492 return (1);
493 }
Cache object: ccaee0a59d05c76d9ed93d800c931ee6
|