Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm64/arm64/exception.S
Version:
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1 /*- 2 * Copyright (c) 2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28 #include <machine/asm.h> 29 __FBSDID("$FreeBSD: releng/11.2/sys/arm64/arm64/exception.S 319205 2017-05-30 13:16:06Z andrew $"); 30 31 #include "assym.s" 32 33 .text 34 35 .macro save_registers el 36 .if \el == 1 37 mov x18, sp 38 sub sp, sp, #128 39 .endif 40 sub sp, sp, #(TF_SIZE + 16) 41 stp x29, x30, [sp, #(TF_SIZE)] 42 stp x28, x29, [sp, #(TF_X + 28 * 8)] 43 stp x26, x27, [sp, #(TF_X + 26 * 8)] 44 stp x24, x25, [sp, #(TF_X + 24 * 8)] 45 stp x22, x23, [sp, #(TF_X + 22 * 8)] 46 stp x20, x21, [sp, #(TF_X + 20 * 8)] 47 stp x18, x19, [sp, #(TF_X + 18 * 8)] 48 stp x16, x17, [sp, #(TF_X + 16 * 8)] 49 stp x14, x15, [sp, #(TF_X + 14 * 8)] 50 stp x12, x13, [sp, #(TF_X + 12 * 8)] 51 stp x10, x11, [sp, #(TF_X + 10 * 8)] 52 stp x8, x9, [sp, #(TF_X + 8 * 8)] 53 stp x6, x7, [sp, #(TF_X + 6 * 8)] 54 stp x4, x5, [sp, #(TF_X + 4 * 8)] 55 stp x2, x3, [sp, #(TF_X + 2 * 8)] 56 stp x0, x1, [sp, #(TF_X + 0 * 8)] 57 mrs x10, elr_el1 58 mrs x11, spsr_el1 59 mrs x12, esr_el1 60 .if \el == 0 61 mrs x18, sp_el0 62 .endif 63 str x10, [sp, #(TF_ELR)] 64 stp w11, w12, [sp, #(TF_SPSR)] 65 stp x18, lr, [sp, #(TF_SP)] 66 mrs x18, tpidr_el1 67 add x29, sp, #(TF_SIZE) 68 .endm 69 70 .macro restore_registers el 71 .if \el == 1 72 msr daifset, #2 73 /* 74 * Disable interrupts, x18 may change in the interrupt exception 75 * handler. For EL0 exceptions, do_ast already did this. 76 */ 77 .endif 78 ldp x18, lr, [sp, #(TF_SP)] 79 ldp x10, x11, [sp, #(TF_ELR)] 80 .if \el == 0 81 msr sp_el0, x18 82 .endif 83 msr spsr_el1, x11 84 msr elr_el1, x10 85 ldp x0, x1, [sp, #(TF_X + 0 * 8)] 86 ldp x2, x3, [sp, #(TF_X + 2 * 8)] 87 ldp x4, x5, [sp, #(TF_X + 4 * 8)] 88 ldp x6, x7, [sp, #(TF_X + 6 * 8)] 89 ldp x8, x9, [sp, #(TF_X + 8 * 8)] 90 ldp x10, x11, [sp, #(TF_X + 10 * 8)] 91 ldp x12, x13, [sp, #(TF_X + 12 * 8)] 92 ldp x14, x15, [sp, #(TF_X + 14 * 8)] 93 ldp x16, x17, [sp, #(TF_X + 16 * 8)] 94 .if \el == 0 95 /* 96 * We only restore the callee saved registers when returning to 97 * userland as they may have been updated by a system call or signal. 98 */ 99 ldp x18, x19, [sp, #(TF_X + 18 * 8)] 100 ldp x20, x21, [sp, #(TF_X + 20 * 8)] 101 ldp x22, x23, [sp, #(TF_X + 22 * 8)] 102 ldp x24, x25, [sp, #(TF_X + 24 * 8)] 103 ldp x26, x27, [sp, #(TF_X + 26 * 8)] 104 ldp x28, x29, [sp, #(TF_X + 28 * 8)] 105 .else 106 ldr x29, [sp, #(TF_X + 29 * 8)] 107 .endif 108 .if \el == 0 109 add sp, sp, #(TF_SIZE + 16) 110 .else 111 mov sp, x18 112 mrs x18, tpidr_el1 113 .endif 114 .endm 115 116 .macro do_ast 117 /* Disable interrupts */ 118 mrs x19, daif 119 1: 120 msr daifset, #2 121 122 /* Read the current thread flags */ 123 ldr x1, [x18, #PC_CURTHREAD] /* Load curthread */ 124 ldr x2, [x1, #TD_FLAGS] 125 126 /* Check if we have either bits set */ 127 mov x3, #((TDF_ASTPENDING|TDF_NEEDRESCHED) >> 8) 128 lsl x3, x3, #8 129 and x2, x2, x3 130 cbz x2, 2f 131 132 /* Restore interrupts */ 133 msr daif, x19 134 135 /* handle the ast */ 136 mov x0, sp 137 bl _C_LABEL(ast) 138 139 /* Re-check for new ast scheduled */ 140 b 1b 141 2: 142 .endm 143 144 ENTRY(handle_el1h_sync) 145 save_registers 1 146 ldr x0, [x18, #PC_CURTHREAD] 147 mov x1, sp 148 bl do_el1h_sync 149 restore_registers 1 150 eret 151 END(handle_el1h_sync) 152 153 ENTRY(handle_el1h_irq) 154 save_registers 1 155 mov x0, sp 156 bl intr_irq_handler 157 restore_registers 1 158 eret 159 END(handle_el1h_irq) 160 161 ENTRY(handle_el1h_error) 162 brk 0xf13 163 END(handle_el1h_error) 164 165 ENTRY(handle_el0_sync) 166 save_registers 0 167 ldr x0, [x18, #PC_CURTHREAD] 168 mov x1, sp 169 str x1, [x0, #TD_FRAME] 170 bl do_el0_sync 171 do_ast 172 restore_registers 0 173 eret 174 END(handle_el0_sync) 175 176 ENTRY(handle_el0_irq) 177 save_registers 0 178 mov x0, sp 179 bl intr_irq_handler 180 do_ast 181 restore_registers 0 182 eret 183 END(handle_el0_irq) 184 185 ENTRY(handle_el0_error) 186 save_registers 0 187 mov x0, sp 188 bl do_el0_error 189 brk 0xf23 190 1: b 1b 191 END(handle_el0_error) 192 193 .macro vempty 194 .align 7 195 brk 0xfff 196 1: b 1b 197 .endm 198 199 .macro vector name 200 .align 7 201 b handle_\name 202 .endm 203 204 .align 11 205 .globl exception_vectors 206 exception_vectors: 207 vempty /* Synchronous EL1t */ 208 vempty /* IRQ EL1t */ 209 vempty /* FIQ EL1t */ 210 vempty /* Error EL1t */ 211 212 vector el1h_sync /* Synchronous EL1h */ 213 vector el1h_irq /* IRQ EL1h */ 214 vempty /* FIQ EL1h */ 215 vector el1h_error /* Error EL1h */ 216 217 vector el0_sync /* Synchronous 64-bit EL0 */ 218 vector el0_irq /* IRQ 64-bit EL0 */ 219 vempty /* FIQ 64-bit EL0 */ 220 vector el0_error /* Error 64-bit EL0 */ 221 222 vempty /* Synchronous 32-bit EL0 */ 223 vempty /* IRQ 32-bit EL0 */ 224 vempty /* FIQ 32-bit EL0 */ 225 vempty /* Error 32-bit EL0 */ 226
Cache object: 52b6ac5ad497998fbff2285dd57dd85e
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