Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/arm64/arm64/gic_v3_reg.h
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1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * 4 * This software was developed by Semihalf under 5 * the sponsorship of the FreeBSD Foundation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _GIC_V3_REG_H_ 32 #define _GIC_V3_REG_H_ 33 34 /* 35 * Maximum number of interrupts 36 * supported by GIC (including SGIs, PPIs and SPIs) 37 */ 38 #define GIC_I_NUM_MAX (1020) 39 /* 40 * Priority MAX/MIN values 41 */ 42 #define GIC_PRIORITY_MAX (0x00UL) 43 /* Upper value is determined by LPI max priority */ 44 #define GIC_PRIORITY_MIN (0xFCUL) 45 46 /* Numbers for shared peripheral interrupts */ 47 #define GIC_LAST_SPI (1019) 48 /* Numbers for local peripheral interrupts */ 49 #define GIC_FIRST_LPI (8192) 50 51 /* 52 * Registers (v2/v3) 53 */ 54 /* GICD_CTLR */ 55 #define GICD_CTLR_G1 (1 << 0) 56 #define GICD_CTLR_G1A (1 << 1) 57 #define GICD_CTLR_ARE_NS (1 << 4) 58 #define GICD_CTLR_RWP (1 << 31) 59 60 /* GICD_TYPER */ 61 #define GICD_TYPER_SECURITYEXTN (1 << 10) 62 #define GICD_TYPER_MBIS (1 << 16) 63 #define GICD_TYPER_LPIS (1 << 17) 64 #define GICD_TYPER_DVIS (1 << 18) 65 #define GICD_TYPER_IDBITS_SHIFT 19 66 #define GICD_TYPER_IDBITS(n) ((((n) >> 19) & 0x1F) + 1) 67 68 /* 69 * Registers (v3) 70 */ 71 #define GICD_STATUSR 0x0010 72 73 #define GICD_SETSPI_NSR 0x0040 74 #define GICD_CLRSPI_NSR 0x0048 75 #define GICD_SETSPI_SR 0x0050 76 #define GICD_CLRSPI_SR 0x0058 77 #define GICD_SPI_INTID_MASK 0x3ff 78 79 #define GICD_IROUTER(n) (0x6000 + ((n) * 8)) 80 #define GICD_AFF3 (0xfful << 32) 81 #define GICD_IROUTER_IRM (1ul << 31) 82 #define GICD_AFF2 (0xfful << 16) 83 #define GICD_AFF1 (0xfful << 8) 84 #define GICD_AFF0 (0xfful << 0) 85 #define GICD_AFF (GICD_AFF0 | GICD_AFF1 | GICD_AFF1 | GICD_AFF3) 86 87 #define GICD_PIDR4 0xFFD0 88 #define GICD_PIDR5 0xFFD4 89 #define GICD_PIDR6 0xFFD8 90 #define GICD_PIDR7 0xFFDC 91 #define GICD_PIDR0 0xFFE0 92 #define GICD_PIDR1 0xFFE4 93 #define GICD_PIDR2 0xFFE8 94 95 #define GICD_SIZE 0x10000 96 97 #define GICR_PIDR2_ARCH_SHIFT 4 98 #define GICR_PIDR2_ARCH_MASK 0xF0 99 #define GICR_PIDR2_ARCH(x) \ 100 (((x) & GICR_PIDR2_ARCH_MASK) >> GICR_PIDR2_ARCH_SHIFT) 101 #define GICR_PIDR2_ARCH_GICv3 0x3 102 #define GICR_PIDR2_ARCH_GICv4 0x4 103 104 #define GICD_PIDR3 0xFFEC 105 106 /* 107 * Redistributor registers 108 */ 109 110 /* RD_base registers */ 111 #define GICR_CTLR 0x0000 112 #define GICR_CTLR_LPI_ENABLE (1 << 0) 113 #define GICR_CTLR_RWP (1 << 3) 114 #define GICR_CTLR_DPG0 (1 << 24) 115 #define GICR_CTLR_DPG1NS (1 << 25) 116 #define GICR_CTLR_DPG1S (1 << 26) 117 #define GICR_CTLR_UWP (1 << 31) 118 119 #define GICR_IIDR 0x0004 120 121 #define GICR_TYPER 0x0008 122 #define GICR_TYPER_PLPIS (1 << 0) 123 #define GICR_TYPER_VLPIS (1 << 1) 124 #define GICR_TYPER_LAST (1 << 4) 125 #define GICR_TYPER_CPUNUM_SHIFT (8) 126 #define GICR_TYPER_CPUNUM_MASK (0xFFFUL << GICR_TYPER_CPUNUM_SHIFT) 127 #define GICR_TYPER_CPUNUM(x) \ 128 (((x) & GICR_TYPER_CPUNUM_MASK) >> GICR_TYPER_CPUNUM_SHIFT) 129 #define GICR_TYPER_AFF_SHIFT 32 130 #define GICR_TYPER_AFF_MASK (0xfffffffful << GICR_TYPER_AFF_SHIFT) 131 #define GICR_TYPER_AFF(x) \ 132 (((x) & GICR_TYPER_AFF_MASK) >> GICR_TYPER_AFF_SHIFT) 133 134 #define GICR_STATUSR 0x0010 135 136 #define GICR_WAKER 0x0014 137 #define GICR_WAKER_PS (1 << 1) /* Processor sleep */ 138 #define GICR_WAKER_CA (1 << 2) /* Children asleep */ 139 140 #define GICR_SETLPIR 0x0040 141 #define GICR_CLRLPIR 0x0048 142 143 #define GICR_PROPBASER 0x0070 144 #define GICR_PROPBASER_IDBITS_MASK 0x1FUL 145 /* 146 * Cacheability 147 * 0x0 - Device-nGnRnE 148 * 0x1 - Normal Inner Non-cacheable 149 * 0x2 - Normal Inner Read-allocate, Write-through 150 * 0x3 - Normal Inner Read-allocate, Write-back 151 * 0x4 - Normal Inner Write-allocate, Write-through 152 * 0x5 - Normal Inner Write-allocate, Write-back 153 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through 154 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back 155 */ 156 #define GICR_PROPBASER_CACHE_SHIFT 7 157 #define GICR_PROPBASER_CACHE_DnGnRnE 0x0UL 158 #define GICR_PROPBASER_CACHE_NIN 0x1UL 159 #define GICR_PROPBASER_CACHE_NIRAWT 0x2UL 160 #define GICR_PROPBASER_CACHE_NIRAWB 0x3UL 161 #define GICR_PROPBASER_CACHE_NIWAWT 0x4UL 162 #define GICR_PROPBASER_CACHE_NIWAWB 0x5UL 163 #define GICR_PROPBASER_CACHE_NIRAWAWT 0x6UL 164 #define GICR_PROPBASER_CACHE_NIRAWAWB 0x7UL 165 #define GICR_PROPBASER_CACHE_MASK \ 166 (0x7UL << GICR_PROPBASER_CACHE_SHIFT) 167 168 /* 169 * Shareability 170 * 0x0 - Non-shareable 171 * 0x1 - Inner-shareable 172 * 0x2 - Outer-shareable 173 * 0x3 - Reserved. Threated as 0x0 174 */ 175 #define GICR_PROPBASER_SHARE_SHIFT 10 176 #define GICR_PROPBASER_SHARE_NS 0x0UL 177 #define GICR_PROPBASER_SHARE_IS 0x1UL 178 #define GICR_PROPBASER_SHARE_OS 0x2UL 179 #define GICR_PROPBASER_SHARE_RES 0x3UL 180 #define GICR_PROPBASER_SHARE_MASK \ 181 (0x3UL << GICR_PROPBASER_SHARE_SHIFT) 182 183 #define GICR_PROPBASER_OUTER_CACHE_SHIFT 56 184 #define GICR_PROPBASER_OUTER_CACHE_MASK \ 185 (0x7UL << GICR_PROPBASER_OUTER_CACHE_SHIFT) 186 187 #define GICR_PENDBASER 0x0078 188 /* 189 * Cacheability 190 * 0x0 - Device-nGnRnE 191 * 0x1 - Normal Inner Non-cacheable 192 * 0x2 - Normal Inner Read-allocate, Write-through 193 * 0x3 - Normal Inner Read-allocate, Write-back 194 * 0x4 - Normal Inner Write-allocate, Write-through 195 * 0x5 - Normal Inner Write-allocate, Write-back 196 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through 197 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back 198 */ 199 #define GICR_PENDBASER_CACHE_SHIFT 7 200 #define GICR_PENDBASER_CACHE_DnGnRnE 0x0UL 201 #define GICR_PENDBASER_CACHE_NIN 0x1UL 202 #define GICR_PENDBASER_CACHE_NIRAWT 0x2UL 203 #define GICR_PENDBASER_CACHE_NIRAWB 0x3UL 204 #define GICR_PENDBASER_CACHE_NIWAWT 0x4UL 205 #define GICR_PENDBASER_CACHE_NIWAWB 0x5UL 206 #define GICR_PENDBASER_CACHE_NIRAWAWT 0x6UL 207 #define GICR_PENDBASER_CACHE_NIRAWAWB 0x7UL 208 #define GICR_PENDBASER_CACHE_MASK \ 209 (0x7UL << GICR_PENDBASER_CACHE_SHIFT) 210 211 /* 212 * Shareability 213 * 0x0 - Non-shareable 214 * 0x1 - Inner-shareable 215 * 0x2 - Outer-shareable 216 * 0x3 - Reserved. Threated as 0x0 217 */ 218 #define GICR_PENDBASER_SHARE_SHIFT 10 219 #define GICR_PENDBASER_SHARE_NS 0x0UL 220 #define GICR_PENDBASER_SHARE_IS 0x1UL 221 #define GICR_PENDBASER_SHARE_OS 0x2UL 222 #define GICR_PENDBASER_SHARE_RES 0x3UL 223 #define GICR_PENDBASER_SHARE_MASK \ 224 (0x3UL << GICR_PENDBASER_SHARE_SHIFT) 225 226 #define GICR_PENDBASER_OUTER_CACHE_SHIFT 56 227 #define GICR_PENDBASER_OUTER_CACHE_MASK \ 228 (0x7UL << GICR_PENDBASER_OUTER_CACHE_SHIFT) 229 230 #define GICR_INVLPIR 0x00a0 231 #define GICR_INVALLR 0x00b0 232 #define GICR_SYNCR 0x00c0 233 234 #define GICR_PIDR2 GICD_PIDR2 235 236 /* SGI_base registers */ 237 #define GICR_IGROUPR0 (0x0080) 238 #define GICR_ISENABLER0 (0x0100) 239 #define GICR_ICENABLER0 (0x0180) 240 #define GICR_I_ENABLER_SGI_MASK (0x0000FFFF) 241 #define GICR_I_ENABLER_PPI_MASK (0xFFFF0000) 242 243 #define GICR_I_PER_IPRIORITYn (GICD_I_PER_IPRIORITYn) 244 245 #define GICR_ISPENDR0 0x0200 246 #define GICR_ICPENDR0 0x0280 247 #define GICR_ISACTIVER0 0x0300 248 #define GICR_ICACTIVER0 0x0380 249 #define GICR_IPRIORITYR(n) (0x0400 + (((n) >> 2) * 4)) 250 #define GICR_ICFGR0 0x0c00 251 #define GICR_ICFGR1 0x0c04 252 #define GICR_IGRPMODR0 0x0d00 253 #define GICR_NSACR 0x0e00 254 255 /* Re-distributor registers for SGIs and PPIs */ 256 #define GICR_RD_BASE 0 257 #define GICR_RD_BASE_SIZE PAGE_SIZE_64K 258 #define GICR_SGI_BASE (1 * PAGE_SIZE_64K) 259 #define GICR_SGI_BASE_SIZE PAGE_SIZE_64K 260 #define GICR_VLPI_BASE (2 * PAGE_SIZE_64K) 261 #define GICR_VLPI_BASE_SIZE PAGE_SIZE_64K 262 #define GICR_RESERVED_SIZE PAGE_SIZE_64K 263 264 /* 265 * ITS registers 266 */ 267 #define GITS_PIDR2 GICR_PIDR2 268 #define GITS_PIDR2_ARCH_MASK GICR_PIDR2_ARCH_MASK 269 #define GITS_PIDR2_ARCH_GICv3 GICR_PIDR2_ARCH_GICv3 270 #define GITS_PIDR2_ARCH_GICv4 GICR_PIDR2_ARCH_GICv4 271 272 #define GITS_CTLR (0x0000) 273 #define GITS_CTLR_EN (1 << 0) 274 275 #define GITS_IIDR (0x0004) 276 #define GITS_IIDR_PRODUCT_SHIFT 24 277 #define GITS_IIDR_PRODUCT_MASK (0xff << GITS_IIDR_PRODUCT_SHIFT) 278 #define GITS_IIDR_VARIANT_SHIFT 16 279 #define GITS_IIDR_VARIANT_MASK (0xf << GITS_IIDR_VARIANT_SHIFT) 280 #define GITS_IIDR_REVISION_SHIFT 12 281 #define GITS_IIDR_REVISION_MASK (0xf << GITS_IIDR_REVISION_SHIFT) 282 #define GITS_IIDR_IMPLEMENTOR_SHIFT 0 283 #define GITS_IIDR_IMPLEMENTOR_MASK (0xfff << GITS_IIDR_IMPLEMENTOR_SHIFT) 284 285 #define GITS_IIDR_RAW(impl, prod, var, rev) \ 286 ((prod) << GITS_IIDR_PRODUCT_SHIFT | \ 287 (var) << GITS_IIDR_VARIANT_SHIFT | \ 288 (rev) << GITS_IIDR_REVISION_SHIFT | \ 289 (impl) << GITS_IIDR_IMPLEMENTOR_SHIFT) 290 291 #define GITS_IIDR_IMPL_ARM (0x43B) 292 #define GITS_IIDR_PROD_GIC500 (0x0) 293 #define GITS_IIDR_IMPL_CAVIUM (0x34c) 294 #define GITS_IIDR_PROD_THUNDER (0xa1) 295 #define GITS_IIDR_VAR_THUNDER_1 (0x0) 296 297 #define GITS_CBASER (0x0080) 298 #define GITS_CBASER_VALID (1UL << 63) 299 /* 300 * Cacheability 301 * 0x0 - Device-nGnRnE 302 * 0x1 - Normal Inner Non-cacheable 303 * 0x2 - Normal Inner Read-allocate, Write-through 304 * 0x3 - Normal Inner Read-allocate, Write-back 305 * 0x4 - Normal Inner Write-allocate, Write-through 306 * 0x5 - Normal Inner Write-allocate, Write-back 307 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through 308 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back 309 */ 310 #define GITS_CBASER_CACHE_SHIFT 59 311 #define GITS_CBASER_CACHE_DnGnRnE 0x0UL 312 #define GITS_CBASER_CACHE_NIN 0x1UL 313 #define GITS_CBASER_CACHE_NIRAWT 0x2UL 314 #define GITS_CBASER_CACHE_NIRAWB 0x3UL 315 #define GITS_CBASER_CACHE_NIWAWT 0x4UL 316 #define GITS_CBASER_CACHE_NIWAWB 0x5UL 317 #define GITS_CBASER_CACHE_NIRAWAWT 0x6UL 318 #define GITS_CBASER_CACHE_NIRAWAWB 0x7UL 319 #define GITS_CBASER_CACHE_MASK (0x7UL << GITS_CBASER_CACHE_SHIFT) 320 /* 321 * Shareability 322 * 0x0 - Non-shareable 323 * 0x1 - Inner-shareable 324 * 0x2 - Outer-shareable 325 * 0x3 - Reserved. Threated as 0x0 326 */ 327 #define GITS_CBASER_SHARE_SHIFT 10 328 #define GITS_CBASER_SHARE_NS 0x0UL 329 #define GITS_CBASER_SHARE_IS 0x1UL 330 #define GITS_CBASER_SHARE_OS 0x2UL 331 #define GITS_CBASER_SHARE_RES 0x3UL 332 #define GITS_CBASER_SHARE_MASK \ 333 (0x3UL << GITS_CBASER_SHARE_SHIFT) 334 335 #define GITS_CBASER_PA_SHIFT 12 336 #define GITS_CBASER_PA_MASK (0xFFFFFFFFFUL << GITS_CBASER_PA_SHIFT) 337 #define GITS_CBASER_SIZE_SHIFT 0 338 #define GITS_CBASER_SIZE_MASK (0xFF << GITS_CBASER_SIZE_SHIFT) 339 #define GITS_CBASER_SIZE(x) \ 340 (4096 * (((x) & GITS_CBASER_SIZE_MASK) + 1)) 341 342 #define GITS_CWRITER (0x0088) 343 #define GITS_CREADR (0x0090) 344 #define GITS_CREADR_STALL 1ul 345 346 #define GITS_CMD_OFFSET(reg) ((reg) & 0xfffe0ul) 347 #define GITS_CMD_SIZE 0x20 348 349 #define GITS_BASER_BASE (0x0100) 350 #define GITS_BASER(x) (GITS_BASER_BASE + (x) * 8) 351 352 #define GITS_BASER_VALID (1UL << 63) 353 354 #define GITS_BASER_INDIRECT_SHIFT 62 355 #define GITS_BASER_INDIRECT (1UL << GITS_BASER_INDIRECT_SHIFT) 356 357 #define GITS_BASER_TYPE_SHIFT 56 358 #define GITS_BASER_TYPE(x) \ 359 (((x) & GITS_BASER_TYPE_MASK) >> GITS_BASER_TYPE_SHIFT) 360 #define GITS_BASER_TYPE_UNIMPL 0x0UL /* Unimplemented */ 361 #define GITS_BASER_TYPE_DEV 0x1UL /* Devices */ 362 #define GITS_BASER_TYPE_VP 0x2UL /* Virtual Processors */ 363 #define GITS_BASER_TYPE_PP 0x3UL /* Physical Processors */ 364 #define GITS_BASER_TYPE_IC 0x4UL /* Interrupt Collections */ 365 #define GITS_BASER_TYPE_RES5 0x5UL /* Reserved */ 366 #define GITS_BASER_TYPE_RES6 0x6UL /* Reserved */ 367 #define GITS_BASER_TYPE_RES7 0x7UL /* Reserved */ 368 #define GITS_BASER_TYPE_MASK (0x7UL << GITS_BASER_TYPE_SHIFT) 369 /* 370 * Cacheability 371 * 0x0 - Non-cacheable, non-bufferable 372 * 0x1 - Non-cacheable 373 * 0x2 - Read-allocate, Write-through 374 * 0x3 - Read-allocate, Write-back 375 * 0x4 - Write-allocate, Write-through 376 * 0x5 - Write-allocate, Write-back 377 * 0x6 - Read-allocate, Write-allocate, Write-through 378 * 0x7 - Read-allocate, Write-allocate, Write-back 379 */ 380 #define GITS_BASER_CACHE_SHIFT 59 381 #define GITS_BASER_CACHE_NCNB 0x0UL 382 #define GITS_BASER_CACHE_NC 0x1UL 383 #define GITS_BASER_CACHE_RAWT 0x2UL 384 #define GITS_BASER_CACHE_RAWB 0x3UL 385 #define GITS_BASER_CACHE_WAWT 0x4UL 386 #define GITS_BASER_CACHE_WAWB 0x5UL 387 #define GITS_BASER_CACHE_RAWAWT 0x6UL 388 #define GITS_BASER_CACHE_RAWAWB 0x7UL 389 #define GITS_BASER_CACHE_MASK (0x7UL << GITS_BASER_CACHE_SHIFT) 390 391 #define GITS_BASER_ESIZE_SHIFT 48 392 #define GITS_BASER_ESIZE_MASK (0x1FUL << GITS_BASER_ESIZE_SHIFT) 393 #define GITS_BASER_ESIZE(x) \ 394 ((((x) & GITS_BASER_ESIZE_MASK) >> GITS_BASER_ESIZE_SHIFT) + 1) 395 396 #define GITS_BASER_PA_SHIFT 12 397 #define GITS_BASER_PA_MASK (0xFFFFFFFFFUL << GITS_BASER_PA_SHIFT) 398 399 /* 400 * Shareability 401 * 0x0 - Non-shareable 402 * 0x1 - Inner-shareable 403 * 0x2 - Outer-shareable 404 * 0x3 - Reserved. Threated as 0x0 405 */ 406 #define GITS_BASER_SHARE_SHIFT 10 407 #define GITS_BASER_SHARE_NS 0x0UL 408 #define GITS_BASER_SHARE_IS 0x1UL 409 #define GITS_BASER_SHARE_OS 0x2UL 410 #define GITS_BASER_SHARE_RES 0x3UL 411 #define GITS_BASER_SHARE_MASK (0x3UL << GITS_BASER_SHARE_SHIFT) 412 413 #define GITS_BASER_PSZ_SHIFT 8 414 #define GITS_BASER_PSZ_4K 0x0UL 415 #define GITS_BASER_PSZ_16K 0x1UL 416 #define GITS_BASER_PSZ_64K 0x2UL 417 #define GITS_BASER_PSZ_MASK (0x3UL << GITS_BASER_PSZ_SHIFT) 418 419 #define GITS_BASER_SIZE_MASK 0xFFUL 420 421 #define GITS_BASER_NUM 8 422 423 #define GITS_TYPER (0x0008) 424 #define GITS_TYPER_HCC_SHIFT 24 425 #define GITS_TYPER_PTA (1UL << 19) 426 #define GITS_TYPER_DEVB_SHIFT 13 427 #define GITS_TYPER_DEVB_MASK (0x1FUL << GITS_TYPER_DEVB_SHIFT) 428 /* Number of device identifiers implemented */ 429 #define GITS_TYPER_DEVB(x) \ 430 ((((x) & GITS_TYPER_DEVB_MASK) >> GITS_TYPER_DEVB_SHIFT) + 1) 431 #define GITS_TYPER_ITTES_SHIFT 4 432 #define GITS_TYPER_ITTES_MASK (0xFUL << GITS_TYPER_ITTES_SHIFT) 433 /* Number of bytes per ITT Entry */ 434 #define GITS_TYPER_ITTES(x) \ 435 ((((x) & GITS_TYPER_ITTES_MASK) >> GITS_TYPER_ITTES_SHIFT) + 1) 436 437 #define GITS_TRANSLATER (0x10040) 438 /* 439 * LPI related 440 */ 441 #define LPI_CONF_PRIO_MASK (0xFC) 442 #define LPI_CONF_GROUP1 (1 << 1) 443 #define LPI_CONF_ENABLE (1 << 0) 444 445 /* 446 * GIC 500 ITS tracking facility 447 */ 448 #define GITS_TRKCTLR 0xC000 449 #define GITS_TRKR 0xC004 450 #define GITS_TRKDIDR 0xC008 451 #define GITS_TRKPIDR 0xC00C 452 #define GITS_TRKVIDR 0xC010 453 #define GITS_TRKTGTR 0xC014 454 #define GITS_TRKICR 0xC018 455 #define GITS_TRKLCR 0xC018 456 457 /* 458 * CPU interface 459 */ 460 461 /* 462 * Registers list (ICC_xyz_EL1): 463 * 464 * PMR - Priority Mask Register 465 * * interrupts of priority higher than specified 466 * in this mask will be signalled to the CPU. 467 * (0xff - lowest possible prio., 0x00 - highest prio.) 468 * 469 * CTLR - Control Register 470 * * controls behavior of the CPU interface and displays 471 * implemented features. 472 * 473 * IGRPEN1 - Interrupt Group 1 Enable Register 474 * 475 * IAR1 - Interrupt Acknowledge Register Group 1 476 * * contains number of the highest priority pending 477 * interrupt from the Group 1. 478 * 479 * EOIR1 - End of Interrupt Register Group 1 480 * * Writes inform CPU interface about completed Group 1 481 * interrupts processing. 482 */ 483 484 #define gic_icc_write(reg, val) \ 485 do { \ 486 WRITE_SPECIALREG(icc_ ##reg ##_el1, val); \ 487 isb(); \ 488 } while (0) 489 490 #define gic_icc_read(reg) \ 491 ({ \ 492 uint64_t val; \ 493 \ 494 val = READ_SPECIALREG(icc_ ##reg ##_el1); \ 495 (val); \ 496 }) 497 498 #define gic_icc_set(reg, mask) \ 499 do { \ 500 uint64_t val; \ 501 val = gic_icc_read(reg); \ 502 val |= (mask); \ 503 gic_icc_write(reg, val); \ 504 } while (0) 505 506 #define gic_icc_clear(reg, mask) \ 507 do { \ 508 uint64_t val; \ 509 val = gic_icc_read(reg); \ 510 val &= ~(mask); \ 511 gic_icc_write(reg, val); \ 512 } while (0) 513 514 #endif /* _GIC_V3_REG_H_ */
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