Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/arm64/arm64/gic_v3_reg.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 2015 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Semihalf under 6 * the sponsorship of the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: releng/11.2/sys/arm64/arm64/gic_v3_reg.h 300308 2016-05-20 15:43:51Z andrew $ 30 */ 31 32 #ifndef _GIC_V3_REG_H_ 33 #define _GIC_V3_REG_H_ 34 35 /* 36 * Maximum number of interrupts 37 * supported by GIC (including SGIs, PPIs and SPIs) 38 */ 39 #define GIC_I_NUM_MAX (1020) 40 /* 41 * Priority MAX/MIN values 42 */ 43 #define GIC_PRIORITY_MAX (0x00UL) 44 /* Upper value is determined by LPI max priority */ 45 #define GIC_PRIORITY_MIN (0xFCUL) 46 47 /* Numbers for software generated interrupts */ 48 #define GIC_FIRST_SGI (0) 49 #define GIC_LAST_SGI (15) 50 /* Numbers for private peripheral interrupts */ 51 #define GIC_FIRST_PPI (16) 52 #define GIC_LAST_PPI (31) 53 /* Numbers for spared peripheral interrupts */ 54 #define GIC_FIRST_SPI (32) 55 #define GIC_LAST_SPI (1019) 56 /* Numbers for local peripheral interrupts */ 57 #define GIC_FIRST_LPI (8192) 58 59 /* 60 * Registers (v2/v3) 61 */ 62 #define GICD_CTLR (0x0000) 63 #define GICD_CTLR_G1 (1 << 0) 64 #define GICD_CTLR_G1A (1 << 1) 65 #define GICD_CTLR_ARE_NS (1 << 4) 66 #define GICD_CTLR_RWP (1 << 31) 67 68 #define GICD_TYPER (0x0004) 69 #define GICD_TYPER_IDBITS(n) ((((n) >> 19) & 0x1F) + 1) 70 #define GICD_TYPER_I_NUM(n) ((((n) & 0x1F) + 1) * 32) 71 72 #define GICD_ISENABLER(n) (0x0100 + (((n) >> 5) * 4)) 73 #define GICD_I_PER_ISENABLERn (32) 74 75 #define GICD_ICENABLER(n) (0x0180 + (((n) >> 5) * 4)) 76 #define GICD_IPRIORITYR(n) (0x0400 + (((n) >> 2) * 4)) 77 #define GICD_I_PER_IPRIORITYn (4) 78 79 #define GICD_I_MASK(n) (1 << ((n) % 32)) 80 81 #define GICD_ICFGR(n) (0x0C00 + (((n) >> 4) * 4)) 82 /* First bit is a polarity bit (0 - low, 1 - high) */ 83 #define GICD_ICFGR_POL_LOW (0 << 0) 84 #define GICD_ICFGR_POL_HIGH (1 << 0) 85 #define GICD_ICFGR_POL_MASK (0x1) 86 /* Second bit is a trigger bit (0 - level, 1 - edge) */ 87 #define GICD_ICFGR_TRIG_LVL (0 << 1) 88 #define GICD_ICFGR_TRIG_EDGE (1 << 1) 89 #define GICD_ICFGR_TRIG_MASK (0x2) 90 91 #define GICD_I_PER_ICFGRn (16) 92 93 /* 94 * Registers (v3) 95 */ 96 #define GICD_IROUTER(n) (0x6000 + ((n) * 8)) 97 #define GICD_PIDR2 (0xFFE8) 98 99 #define GICR_PIDR2_ARCH_MASK (0xF0) 100 #define GICR_PIDR2_ARCH_GICv3 (0x30) 101 #define GICR_PIDR2_ARCH_GICv4 (0x40) 102 103 /* Redistributor registers */ 104 #define GICR_CTLR GICD_CTLR 105 #define GICR_CTLR_LPI_ENABLE (1 << 0) 106 107 #define GICR_PIDR2 GICD_PIDR2 108 109 #define GICR_TYPER (0x0008) 110 #define GICR_TYPER_PLPIS (1 << 0) 111 #define GICR_TYPER_VLPIS (1 << 1) 112 #define GICR_TYPER_LAST (1 << 4) 113 #define GICR_TYPER_CPUNUM_SHIFT (8) 114 #define GICR_TYPER_CPUNUM_MASK (0xFFFUL << GICR_TYPER_CPUNUM_SHIFT) 115 #define GICR_TYPER_CPUNUM(x) \ 116 (((x) & GICR_TYPER_CPUNUM_MASK) >> GICR_TYPER_CPUNUM_SHIFT) 117 #define GICR_TYPER_AFF_SHIFT (32) 118 119 #define GICR_WAKER (0x0014) 120 #define GICR_WAKER_PS (1 << 1) /* Processor sleep */ 121 #define GICR_WAKER_CA (1 << 2) /* Children asleep */ 122 123 #define GICR_PROPBASER (0x0070) 124 #define GICR_PROPBASER_IDBITS_MASK 0x1FUL 125 /* 126 * Cacheability 127 * 0x0 - Device-nGnRnE 128 * 0x1 - Normal Inner Non-cacheable 129 * 0x2 - Normal Inner Read-allocate, Write-through 130 * 0x3 - Normal Inner Read-allocate, Write-back 131 * 0x4 - Normal Inner Write-allocate, Write-through 132 * 0x5 - Normal Inner Write-allocate, Write-back 133 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through 134 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back 135 */ 136 #define GICR_PROPBASER_CACHE_SHIFT 7 137 #define GICR_PROPBASER_CACHE_DnGnRnE 0x0UL 138 #define GICR_PROPBASER_CACHE_NIN 0x1UL 139 #define GICR_PROPBASER_CACHE_NIRAWT 0x2UL 140 #define GICR_PROPBASER_CACHE_NIRAWB 0x3UL 141 #define GICR_PROPBASER_CACHE_NIWAWT 0x4UL 142 #define GICR_PROPBASER_CACHE_NIWAWB 0x5UL 143 #define GICR_PROPBASER_CACHE_NIRAWAWT 0x6UL 144 #define GICR_PROPBASER_CACHE_NIRAWAWB 0x7UL 145 #define GICR_PROPBASER_CACHE_MASK \ 146 (0x7UL << GICR_PROPBASER_CACHE_SHIFT) 147 148 /* 149 * Shareability 150 * 0x0 - Non-shareable 151 * 0x1 - Inner-shareable 152 * 0x2 - Outer-shareable 153 * 0x3 - Reserved. Threated as 0x0 154 */ 155 #define GICR_PROPBASER_SHARE_SHIFT 10 156 #define GICR_PROPBASER_SHARE_NS 0x0UL 157 #define GICR_PROPBASER_SHARE_IS 0x1UL 158 #define GICR_PROPBASER_SHARE_OS 0x2UL 159 #define GICR_PROPBASER_SHARE_RES 0x3UL 160 #define GICR_PROPBASER_SHARE_MASK \ 161 (0x3UL << GICR_PROPBASER_SHARE_SHIFT) 162 163 #define GICR_PENDBASER (0x0078) 164 /* 165 * Cacheability 166 * 0x0 - Device-nGnRnE 167 * 0x1 - Normal Inner Non-cacheable 168 * 0x2 - Normal Inner Read-allocate, Write-through 169 * 0x3 - Normal Inner Read-allocate, Write-back 170 * 0x4 - Normal Inner Write-allocate, Write-through 171 * 0x5 - Normal Inner Write-allocate, Write-back 172 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through 173 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back 174 */ 175 #define GICR_PENDBASER_CACHE_SHIFT 7 176 #define GICR_PENDBASER_CACHE_DnGnRnE 0x0UL 177 #define GICR_PENDBASER_CACHE_NIN 0x1UL 178 #define GICR_PENDBASER_CACHE_NIRAWT 0x2UL 179 #define GICR_PENDBASER_CACHE_NIRAWB 0x3UL 180 #define GICR_PENDBASER_CACHE_NIWAWT 0x4UL 181 #define GICR_PENDBASER_CACHE_NIWAWB 0x5UL 182 #define GICR_PENDBASER_CACHE_NIRAWAWT 0x6UL 183 #define GICR_PENDBASER_CACHE_NIRAWAWB 0x7UL 184 #define GICR_PENDBASER_CACHE_MASK \ 185 (0x7UL << GICR_PENDBASER_CACHE_SHIFT) 186 187 /* 188 * Shareability 189 * 0x0 - Non-shareable 190 * 0x1 - Inner-shareable 191 * 0x2 - Outer-shareable 192 * 0x3 - Reserved. Threated as 0x0 193 */ 194 #define GICR_PENDBASER_SHARE_SHIFT 10 195 #define GICR_PENDBASER_SHARE_NS 0x0UL 196 #define GICR_PENDBASER_SHARE_IS 0x1UL 197 #define GICR_PENDBASER_SHARE_OS 0x2UL 198 #define GICR_PENDBASER_SHARE_RES 0x3UL 199 #define GICR_PENDBASER_SHARE_MASK \ 200 (0x3UL << GICR_PENDBASER_SHARE_SHIFT) 201 202 /* Re-distributor registers for SGIs and PPIs */ 203 #define GICR_RD_BASE_SIZE PAGE_SIZE_64K 204 #define GICR_SGI_BASE_SIZE PAGE_SIZE_64K 205 #define GICR_VLPI_BASE_SIZE PAGE_SIZE_64K 206 #define GICR_RESERVED_SIZE PAGE_SIZE_64K 207 208 #define GICR_ISENABLER0 (0x0100) 209 #define GICR_ICENABLER0 (0x0180) 210 #define GICR_I_ENABLER_SGI_MASK (0x0000FFFF) 211 #define GICR_I_ENABLER_PPI_MASK (0xFFFF0000) 212 213 #define GICR_I_PER_IPRIORITYn (GICD_I_PER_IPRIORITYn) 214 215 /* ITS registers */ 216 #define GITS_PIDR2 GICR_PIDR2 217 #define GITS_PIDR2_ARCH_MASK GICR_PIDR2_ARCH_MASK 218 #define GITS_PIDR2_ARCH_GICv3 GICR_PIDR2_ARCH_GICv3 219 #define GITS_PIDR2_ARCH_GICv4 GICR_PIDR2_ARCH_GICv4 220 221 #define GITS_CTLR (0x0000) 222 #define GITS_CTLR_EN (1 << 0) 223 224 #define GITS_IIDR (0x0004) 225 #define GITS_IIDR_PRODUCT_SHIFT 24 226 #define GITS_IIDR_PRODUCT_MASK (0xff << GITS_IIDR_PRODUCT_SHIFT) 227 #define GITS_IIDR_VARIANT_SHIFT 16 228 #define GITS_IIDR_VARIANT_MASK (0xf << GITS_IIDR_VARIANT_SHIFT) 229 #define GITS_IIDR_REVISION_SHIFT 12 230 #define GITS_IIDR_REVISION_MASK (0xf << GITS_IIDR_REVISION_SHIFT) 231 #define GITS_IIDR_IMPLEMENTOR_SHIFT 0 232 #define GITS_IIDR_IMPLEMENTOR_MASK (0xfff << GITS_IIDR_IMPLEMENTOR_SHIFT) 233 234 #define GITS_IIDR_RAW(impl, prod, var, rev) \ 235 ((prod) << GITS_IIDR_PRODUCT_SHIFT | \ 236 (var) << GITS_IIDR_VARIANT_SHIFT | \ 237 (rev) << GITS_IIDR_REVISION_SHIFT | \ 238 (impl) << GITS_IIDR_IMPLEMENTOR_SHIFT) 239 240 #define GITS_IIDR_IMPL_CAVIUM (0x34c) 241 #define GITS_IIDR_PROD_THUNDER (0xa1) 242 #define GITS_IIDR_VAR_THUNDER_1 (0x0) 243 244 #define GITS_CBASER (0x0080) 245 #define GITS_CBASER_VALID (1UL << 63) 246 /* 247 * Cacheability 248 * 0x0 - Device-nGnRnE 249 * 0x1 - Normal Inner Non-cacheable 250 * 0x2 - Normal Inner Read-allocate, Write-through 251 * 0x3 - Normal Inner Read-allocate, Write-back 252 * 0x4 - Normal Inner Write-allocate, Write-through 253 * 0x5 - Normal Inner Write-allocate, Write-back 254 * 0x6 - Normal Inner Read-allocate, Write-allocate, Write-through 255 * 0x7 - Normal Inner Read-allocate, Write-allocate, Write-back 256 */ 257 #define GITS_CBASER_CACHE_SHIFT 59 258 #define GITS_CBASER_CACHE_DnGnRnE 0x0UL 259 #define GITS_CBASER_CACHE_NIN 0x1UL 260 #define GITS_CBASER_CACHE_NIRAWT 0x2UL 261 #define GITS_CBASER_CACHE_NIRAWB 0x3UL 262 #define GITS_CBASER_CACHE_NIWAWT 0x4UL 263 #define GITS_CBASER_CACHE_NIWAWB 0x5UL 264 #define GITS_CBASER_CACHE_NIRAWAWT 0x6UL 265 #define GITS_CBASER_CACHE_NIRAWAWB 0x7UL 266 #define GITS_CBASER_CACHE_MASK (0x7UL << GITS_CBASER_CACHE_SHIFT) 267 /* 268 * Shareability 269 * 0x0 - Non-shareable 270 * 0x1 - Inner-shareable 271 * 0x2 - Outer-shareable 272 * 0x3 - Reserved. Threated as 0x0 273 */ 274 #define GITS_CBASER_SHARE_SHIFT 10 275 #define GITS_CBASER_SHARE_NS 0x0UL 276 #define GITS_CBASER_SHARE_IS 0x1UL 277 #define GITS_CBASER_SHARE_OS 0x2UL 278 #define GITS_CBASER_SHARE_RES 0x3UL 279 #define GITS_CBASER_SHARE_MASK \ 280 (0x3UL << GITS_CBASER_SHARE_SHIFT) 281 282 #define GITS_CBASER_PA_SHIFT 12 283 #define GITS_CBASER_PA_MASK (0xFFFFFFFFFUL << GITS_CBASER_PA_SHIFT) 284 285 #define GITS_CWRITER (0x0088) 286 #define GITS_CREADR (0x0090) 287 288 #define GITS_BASER_BASE (0x0100) 289 #define GITS_BASER(x) (GITS_BASER_BASE + (x) * 8) 290 291 #define GITS_BASER_VALID (1UL << 63) 292 293 #define GITS_BASER_TYPE_SHIFT 56 294 #define GITS_BASER_TYPE(x) \ 295 (((x) & GITS_BASER_TYPE_MASK) >> GITS_BASER_TYPE_SHIFT) 296 #define GITS_BASER_TYPE_UNIMPL 0x0UL /* Unimplemented */ 297 #define GITS_BASER_TYPE_DEV 0x1UL /* Devices */ 298 #define GITS_BASER_TYPE_VP 0x2UL /* Virtual Processors */ 299 #define GITS_BASER_TYPE_PP 0x3UL /* Physical Processors */ 300 #define GITS_BASER_TYPE_IC 0x4UL /* Interrupt Collections */ 301 #define GITS_BASER_TYPE_RES5 0x5UL /* Reserved */ 302 #define GITS_BASER_TYPE_RES6 0x6UL /* Reserved */ 303 #define GITS_BASER_TYPE_RES7 0x7UL /* Reserved */ 304 #define GITS_BASER_TYPE_MASK (0x7UL << GITS_BASER_TYPE_SHIFT) 305 /* 306 * Cacheability 307 * 0x0 - Non-cacheable, non-bufferable 308 * 0x1 - Non-cacheable 309 * 0x2 - Read-allocate, Write-through 310 * 0x3 - Read-allocate, Write-back 311 * 0x4 - Write-allocate, Write-through 312 * 0x5 - Write-allocate, Write-back 313 * 0x6 - Read-allocate, Write-allocate, Write-through 314 * 0x7 - Read-allocate, Write-allocate, Write-back 315 */ 316 #define GITS_BASER_CACHE_SHIFT 59 317 #define GITS_BASER_CACHE_NCNB 0x0UL 318 #define GITS_BASER_CACHE_NC 0x1UL 319 #define GITS_BASER_CACHE_RAWT 0x2UL 320 #define GITS_BASER_CACHE_RAWB 0x3UL 321 #define GITS_BASER_CACHE_WAWT 0x4UL 322 #define GITS_BASER_CACHE_WAWB 0x5UL 323 #define GITS_BASER_CACHE_RAWAWT 0x6UL 324 #define GITS_BASER_CACHE_RAWAWB 0x7UL 325 #define GITS_BASER_CACHE_MASK (0x7UL << GITS_BASER_CACHE_SHIFT) 326 327 #define GITS_BASER_ESIZE_SHIFT 48 328 #define GITS_BASER_ESIZE_MASK (0x1FUL << GITS_BASER_ESIZE_SHIFT) 329 #define GITS_BASER_ESIZE(x) \ 330 ((((x) & GITS_BASER_ESIZE_MASK) >> GITS_BASER_ESIZE_SHIFT) + 1) 331 332 #define GITS_BASER_PA_SHIFT 12 333 #define GITS_BASER_PA_MASK (0xFFFFFFFFFUL << GITS_BASER_PA_SHIFT) 334 335 /* 336 * Shareability 337 * 0x0 - Non-shareable 338 * 0x1 - Inner-shareable 339 * 0x2 - Outer-shareable 340 * 0x3 - Reserved. Threated as 0x0 341 */ 342 #define GITS_BASER_SHARE_SHIFT 10 343 #define GITS_BASER_SHARE_NS 0x0UL 344 #define GITS_BASER_SHARE_IS 0x1UL 345 #define GITS_BASER_SHARE_OS 0x2UL 346 #define GITS_BASER_SHARE_RES 0x3UL 347 #define GITS_BASER_SHARE_MASK (0x3UL << GITS_BASER_SHARE_SHIFT) 348 349 #define GITS_BASER_PSZ_SHIFT 8 350 #define GITS_BASER_PSZ_4K 0x0UL 351 #define GITS_BASER_PSZ_16K 0x1UL 352 #define GITS_BASER_PSZ_64K 0x2UL 353 #define GITS_BASER_PSZ_MASK (0x3UL << GITS_BASER_PSZ_SHIFT) 354 355 #define GITS_BASER_SIZE_MASK 0xFFUL 356 357 #define GITS_BASER_NUM 8 358 359 #define GITS_TYPER (0x0008) 360 #define GITS_TYPER_PTA (1UL << 19) 361 #define GITS_TYPER_DEVB_SHIFT 13 362 #define GITS_TYPER_DEVB_MASK (0x1FUL << GITS_TYPER_DEVB_SHIFT) 363 /* Number of device identifiers implemented */ 364 #define GITS_TYPER_DEVB(x) \ 365 ((((x) & GITS_TYPER_DEVB_MASK) >> GITS_TYPER_DEVB_SHIFT) + 1) 366 #define GITS_TYPER_ITTES_SHIFT 4 367 #define GITS_TYPER_ITTES_MASK (0xFUL << GITS_TYPER_ITTES_SHIFT) 368 /* Number of bytes per ITT Entry */ 369 #define GITS_TYPER_ITTES(x) \ 370 ((((x) & GITS_TYPER_ITTES_MASK) >> GITS_TYPER_ITTES_SHIFT) + 1) 371 372 #define GITS_TRANSLATER (0x10040) 373 /* 374 * LPI related 375 */ 376 #define LPI_CONF_PRIO_MASK (0xFC) 377 #define LPI_CONF_GROUP1 (1 << 1) 378 #define LPI_CONF_ENABLE (1 << 0) 379 380 /* 381 * CPU interface 382 */ 383 384 /* 385 * Registers list (ICC_xyz_EL1): 386 * 387 * PMR - Priority Mask Register 388 * * interrupts of priority higher than specified 389 * in this mask will be signalled to the CPU. 390 * (0xff - lowest possible prio., 0x00 - highest prio.) 391 * 392 * CTLR - Control Register 393 * * controls behavior of the CPU interface and displays 394 * implemented features. 395 * 396 * IGRPEN1 - Interrupt Group 1 Enable Register 397 * 398 * IAR1 - Interrupt Acknowledge Register Group 1 399 * * contains number of the highest priority pending 400 * interrupt from the Group 1. 401 * 402 * EOIR1 - End of Interrupt Register Group 1 403 * * Writes inform CPU interface about completed Group 1 404 * interrupts processing. 405 */ 406 407 #define gic_icc_write(reg, val) \ 408 do { \ 409 WRITE_SPECIALREG(ICC_ ##reg ##_EL1, val); \ 410 isb(); \ 411 } while (0) 412 413 #define gic_icc_read(reg) \ 414 ({ \ 415 uint64_t val; \ 416 \ 417 val = READ_SPECIALREG(ICC_ ##reg ##_EL1); \ 418 (val); \ 419 }) 420 421 #define gic_icc_set(reg, mask) \ 422 do { \ 423 uint64_t val; \ 424 val = gic_icc_read(reg); \ 425 val |= (mask); \ 426 gic_icc_write(reg, val); \ 427 } while (0) 428 429 #define gic_icc_clear(reg, mask) \ 430 do { \ 431 uint64_t val; \ 432 val = gic_icc_read(reg); \ 433 val &= ~(mask); \ 434 gic_icc_write(reg, val); \ 435 } while (0) 436 437 #endif /* _GIC_V3_REG_H_ */
Cache object: 316ffcaa28caad66fd8c1c51abe9eabe
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]