Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/arm64/broadcom/genet/if_genetreg.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* $NetBSD: bcmgenetreg.h,v 1.2 2020/02/22 13:41:41 jmcneill Exp $ */ 2 3 /* derived from NetBSD's bcmgenetreg.h */ 4 5 /*- 6 * Copyright (c) 2020 Michael J Karels 7 * Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * Broadcom GENETv5 35 */ 36 37 #ifndef _BCMGENETREG_H 38 #define _BCMGENETREG_H 39 40 #define GENET_SYS_REV_CTRL 0x000 41 #define SYS_REV_MAJOR __BITS(27,24) 42 #define SYS_REV_MINOR __BITS(19,16) 43 #define REV_MAJOR 0xf000000 44 #define REV_MAJOR_SHIFT 24 45 #define REV_MAJOR_V5 6 46 #define REV_MINOR 0xf0000 47 #define REV_MINOR_SHIFT 16 48 #define REV_PHY 0xffff 49 #define GENET_SYS_PORT_CTRL 0x004 50 #define GENET_SYS_PORT_MODE_EXT_GPHY 3 51 #define GENET_SYS_RBUF_FLUSH_CTRL 0x008 52 #define GENET_SYS_RBUF_FLUSH_RESET __BIT(1) 53 #define GENET_SYS_TBUF_FLUSH_CTRL 0x00c 54 #define GENET_EXT_RGMII_OOB_CTRL 0x08c 55 #define GENET_EXT_RGMII_OOB_ID_MODE_DISABLE __BIT(16) 56 #define GENET_EXT_RGMII_OOB_RGMII_MODE_EN __BIT(6) 57 #define GENET_EXT_RGMII_OOB_OOB_DISABLE __BIT(5) 58 #define GENET_EXT_RGMII_OOB_RGMII_LINK __BIT(4) 59 #define GENET_INTRL2_CPU_STAT 0x200 60 #define GENET_INTRL2_CPU_CLEAR 0x208 61 #define GENET_INTRL2_CPU_STAT_MASK 0x20c 62 #define GENET_INTRL2_CPU_SET_MASK 0x210 63 #define GENET_INTRL2_CPU_CLEAR_MASK 0x214 64 #define GENET_IRQ_MDIO_ERROR __BIT(24) 65 #define GENET_IRQ_MDIO_DONE __BIT(23) 66 #define GENET_IRQ_TXDMA_DONE __BIT(16) 67 #define GENET_IRQ_RXDMA_DONE __BIT(13) 68 #define GENET_RBUF_CTRL 0x300 69 #define GENET_RBUF_BAD_DIS __BIT(2) 70 #define GENET_RBUF_ALIGN_2B __BIT(1) 71 #define GENET_RBUF_64B_EN __BIT(0) 72 #define GENET_RBUF_CHECK_CTRL 0x314 73 #define GENET_RBUF_CHECK_CTRL_EN __BIT(0) 74 #define GENET_RBUF_CHECK_SKIP_FCS __BIT(4) 75 #define GENET_RBUF_TBUF_SIZE_CTRL 0x3b4 76 #define GENET_TBUF_CTRL 0x600 77 #define GENET_UMAC_CMD 0x808 78 #define GENET_UMAC_CMD_LCL_LOOP_EN __BIT(15) 79 #define GENET_UMAC_CMD_SW_RESET __BIT(13) 80 #define GENET_UMAC_CMD_PROMISC __BIT(4) 81 #ifdef __BITS 82 #define GENET_UMAC_CMD_SPEED __BITS(3,2) 83 #define GENET_UMAC_CMD_SPEED_10 0 84 #define GENET_UMAC_CMD_SPEED_100 1 85 #define GENET_UMAC_CMD_SPEED_1000 2 86 #else 87 #define GENET_UMAC_CMD_SPEED (3 << 2) 88 #define GENET_UMAC_CMD_SPEED_10 (0 << 2) 89 #define GENET_UMAC_CMD_SPEED_100 (1 << 2) 90 #define GENET_UMAC_CMD_SPEED_1000 (2 << 2) 91 #define GENET_UMAC_CMD_CRC_FWD __BIT(6) 92 #endif 93 #define GENET_UMAC_CMD_RXEN __BIT(1) 94 #define GENET_UMAC_CMD_TXEN __BIT(0) 95 #define GENET_UMAC_MAC0 0x80c 96 #define GENET_UMAC_MAC1 0x810 97 #define GENET_UMAC_MAX_FRAME_LEN 0x814 98 #define GENET_UMAC_TX_FLUSH 0xb34 99 #define GENET_UMAC_MIB_CTRL 0xd80 100 #define GENET_UMAC_MIB_RESET_TX __BIT(2) 101 #define GENET_UMAC_MIB_RESET_RUNT __BIT(1) 102 #define GENET_UMAC_MIB_RESET_RX __BIT(0) 103 #define GENET_MDIO_CMD 0xe14 104 #define GENET_MDIO_START_BUSY __BIT(29) 105 #define GENET_MDIO_READ_FAILED __BIT(28) 106 #define GENET_MDIO_READ __BIT(27) 107 #define GENET_MDIO_WRITE __BIT(26) 108 #define GENET_MDIO_PMD __BITS(25,21) 109 #define GENET_MDIO_REG __BITS(20,16) 110 #define GENET_MDIO_ADDR_SHIFT 21 111 #define GENET_MDIO_REG_SHIFT 16 112 #define GENET_MDIO_VAL_MASK 0xffff 113 #define GENET_UMAC_MDF_CTRL 0xe50 114 #define GENET_UMAC_MDF_ADDR0(n) (0xe54 + (n) * 0x8) 115 #define GENET_UMAC_MDF_ADDR1(n) (0xe58 + (n) * 0x8) 116 #define GENET_MAX_MDF_FILTER 17 117 118 #define GENET_DMA_DESC_COUNT 256 119 #define GENET_DMA_DESC_SIZE 12 120 #define GENET_DMA_DEFAULT_QUEUE 16 121 122 #define GENET_DMA_RING_SIZE 0x40 123 #define GENET_DMA_RINGS_SIZE (GENET_DMA_RING_SIZE * (GENET_DMA_DEFAULT_QUEUE + 1)) 124 125 #define GENET_RX_BASE 0x2000 126 #define GENET_TX_BASE 0x4000 127 128 #define GENET_RX_DMA_RINGBASE(qid) (GENET_RX_BASE + 0xc00 + GENET_DMA_RING_SIZE * (qid)) 129 #define GENET_RX_DMA_WRITE_PTR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x00) 130 #define GENET_RX_DMA_WRITE_PTR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x04) 131 #define GENET_RX_DMA_PROD_INDEX(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x08) 132 #define GENET_RX_DMA_CONS_INDEX(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x0c) 133 #define GENET_RX_DMA_PROD_CONS_MASK 0xffff 134 #define GENET_RX_DMA_RING_BUF_SIZE(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x10) 135 #define GENET_RX_DMA_RING_BUF_SIZE_DESC_COUNT __BITS(31,16) 136 #define GENET_RX_DMA_RING_BUF_SIZE_BUF_LENGTH __BITS(15,0) 137 #define GENET_RX_DMA_RING_BUF_SIZE_DESC_SHIFT 16 138 #define GENET_RX_DMA_RING_BUF_SIZE_BUF_LEN_MASK 0xffff 139 #define GENET_RX_DMA_START_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x14) 140 #define GENET_RX_DMA_START_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x18) 141 #define GENET_RX_DMA_END_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x1c) 142 #define GENET_RX_DMA_END_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x20) 143 #define GENET_RX_DMA_XON_XOFF_THRES(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x28) 144 #define GENET_RX_DMA_XON_XOFF_THRES_LO __BITS(31,16) 145 #define GENET_RX_DMA_XON_XOFF_THRES_HI __BITS(15,0) 146 #define GENET_RX_DMA_XON_XOFF_THRES_LO_SHIFT 16 147 #define GENET_RX_DMA_READ_PTR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x2c) 148 #define GENET_RX_DMA_READ_PTR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x30) 149 150 #define GENET_TX_DMA_RINGBASE(qid) (GENET_TX_BASE + 0xc00 + GENET_DMA_RING_SIZE * (qid)) 151 #define GENET_TX_DMA_READ_PTR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x00) 152 #define GENET_TX_DMA_READ_PTR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x04) 153 #define GENET_TX_DMA_CONS_INDEX(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x08) 154 #define GENET_TX_DMA_PROD_INDEX(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x0c) 155 #define GENET_TX_DMA_PROD_CONS_MASK 0xffff 156 #define GENET_TX_DMA_RING_BUF_SIZE(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x10) 157 #define GENET_TX_DMA_RING_BUF_SIZE_DESC_COUNT __BITS(31,16) 158 #define GENET_TX_DMA_RING_BUF_SIZE_BUF_LENGTH __BITS(15,0) 159 #define GENET_TX_DMA_RING_BUF_SIZE_DESC_SHIFT 16 160 #define GENET_TX_DMA_RING_BUF_SIZE_BUF_LEN_MASK 0xffff 161 #define GENET_TX_DMA_START_ADDR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x14) 162 #define GENET_TX_DMA_START_ADDR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x18) 163 #define GENET_TX_DMA_END_ADDR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x1c) 164 #define GENET_TX_DMA_END_ADDR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x20) 165 #define GENET_TX_DMA_MBUF_DONE_THRES(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x24) 166 #define GENET_TX_DMA_FLOW_PERIOD(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x28) 167 #define GENET_TX_DMA_WRITE_PTR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x2c) 168 #define GENET_TX_DMA_WRITE_PTR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x30) 169 170 #define GENET_RX_DESC_STATUS(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x00) 171 #define GENET_RX_DESC_STATUS_BUFLEN __BITS(27,16) 172 #define GENET_RX_DESC_STATUS_BUFLEN_MASK 0xfff0000 173 #define GENET_RX_DESC_STATUS_BUFLEN_SHIFT 16 174 #define GENET_RX_DESC_STATUS_OWN __BIT(15) /* ??? */ 175 #define GENET_RX_DESC_STATUS_CKSUM_OK __BIT(15) 176 #define GENET_RX_DESC_STATUS_EOP __BIT(14) 177 #define GENET_RX_DESC_STATUS_SOP __BIT(13) 178 #define GENET_RX_DESC_STATUS_RX_ERROR __BIT(2) 179 #define GENET_RX_DESC_ADDRESS_LO(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x04) 180 #define GENET_RX_DESC_ADDRESS_HI(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x08) 181 182 #define GENET_TX_DESC_STATUS(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x00) 183 #define GENET_TX_DESC_STATUS_BUFLEN __BITS(27,16) 184 #define GENET_TX_DESC_STATUS_OWN __BIT(15) 185 #define GENET_TX_DESC_STATUS_EOP __BIT(14) 186 #define GENET_TX_DESC_STATUS_SOP __BIT(13) 187 #define GENET_TX_DESC_STATUS_QTAG __BITS(12,7) 188 #define GENET_TX_DESC_STATUS_CRC __BIT(6) 189 #define GENET_TX_DESC_STATUS_CKSUM __BIT(4) 190 #define GENET_TX_DESC_STATUS_BUFLEN_SHIFT 16 191 #define GENET_TX_DESC_STATUS_BUFLEN_MASK 0x7ff0000 192 #define GENET_TX_DESC_STATUS_QTAG_MASK 0x1f80 193 #define GENET_TX_DESC_ADDRESS_LO(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x04) 194 #define GENET_TX_DESC_ADDRESS_HI(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x08) 195 196 /* Status block prepended to tx/rx packets (optional) */ 197 struct statusblock { 198 u_int32_t status_buflen; 199 u_int32_t extstatus; 200 u_int32_t rxcsum; 201 u_int32_t spare1[9]; 202 u_int32_t txcsuminfo; 203 u_int32_t spare2[3]; 204 }; 205 206 /* bits in txcsuminfo */ 207 #define TXCSUM_LEN_VALID __BIT(31) 208 #define TXCSUM_OFF_SHIFT 16 209 #define TXCSUM_UDP __BIT(15) 210 211 #define GENET_RX_DMA_RING_CFG (GENET_RX_BASE + 0x1040 + 0x00) 212 #define GENET_RX_DMA_CTRL (GENET_RX_BASE + 0x1040 + 0x04) 213 #define GENET_RX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1) 214 #define GENET_RX_DMA_CTRL_EN __BIT(0) 215 #define GENET_RX_SCB_BURST_SIZE (GENET_RX_BASE + 0x1040 + 0x0c) 216 217 #define GENET_TX_DMA_RING_CFG (GENET_TX_BASE + 0x1040 + 0x00) 218 #define GENET_TX_DMA_CTRL (GENET_TX_BASE + 0x1040 + 0x04) 219 #define GENET_TX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1) 220 #define GENET_TX_DMA_CTRL_EN __BIT(0) 221 #define GENET_TX_SCB_BURST_SIZE (GENET_TX_BASE + 0x1040 + 0x0c) 222 223 #endif /* !_BCMGENETREG_H */
Cache object: ac03cdc99b49b2a1dac425a155acedc5
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]