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sys/arm64/include/cmn600_reg.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 ARM Ltd 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _MACHINE_CMN600_REG_H_ 31 #define _MACHINE_CMN600_REG_H_ 32 33 #define CMN600_COUNTERS_N 8 34 #define CMN600_UNIT_MAX 4 35 #define CMN600_PMU_DEFAULT_UNITS_N 2 36 #define CMN600_COMMON_PMU_EVENT_SEL 0x2000 /* rw */ 37 #define CMN600_COMMON_PMU_EVENT_SEL_OCC_SHIFT 32 38 #define CMN600_COMMON_PMU_EVENT_SEL_OCC_MASK (0x7UL << 32) 39 40 struct cmn600_pmc { 41 void *arg; 42 int domain; 43 }; 44 45 int cmn600_pmc_nunits(void); 46 int cmn600_pmc_getunit(int unit, void **arg, int *domain); 47 48 int cmn600_pmu_intr_cb(void *arg, int (*handler)(struct trapframe *tf, 49 int unit, int i)); 50 51 int pmu_cmn600_alloc_localpmc(void *arg, int nodeid, int node_type, 52 int *local_counter); 53 int pmu_cmn600_free_localpmc(void *arg, int nodeid, int node_type, 54 int local_counter); 55 int pmu_cmn600_rev(void *arg); 56 uint32_t pmu_cmn600_rd4(void *arg, int nodeid, int node_type, off_t reg); 57 int pmu_cmn600_wr4(void *arg, int nodeid, int node_type, off_t reg, 58 uint32_t val); 59 uint64_t pmu_cmn600_rd8(void *arg, int nodeid, int node_type, off_t reg); 60 int pmu_cmn600_wr8(void *arg, int nodeid, int node_type, off_t reg, 61 uint64_t val); 62 int pmu_cmn600_set8(void *arg, int nodeid, int node_type, off_t reg, 63 uint64_t val); 64 int pmu_cmn600_clr8(void *arg, int nodeid, int node_type, off_t reg, 65 uint64_t val); 66 int pmu_cmn600_md8(void *arg, int nodeid, int node_type, off_t reg, 67 uint64_t mask, uint64_t val); 68 69 /* Configuration master registers */ 70 #define POR_CFGM_NODE_INFO 0x0000 /* ro */ 71 #define POR_CFGM_NODE_INFO_LOGICAL_ID_MASK 0xffff00000000UL 72 #define POR_CFGM_NODE_INFO_LOGICAL_ID_SHIFT 32 73 #define POR_CFGM_NODE_INFO_NODE_ID_MASK 0xffff0000 74 #define POR_CFGM_NODE_INFO_NODE_ID_SHIFT 16 75 #define POR_CFGM_NODE_INFO_NODE_TYPE_MASK 0xffff 76 #define POR_CFGM_NODE_INFO_NODE_TYPE_SHIFT 0 77 78 #define NODE_ID_SUB_MASK 0x3 79 #define NODE_ID_SUB_SHIFT 0 80 #define NODE_ID_PORT_MASK 0x4 81 #define NODE_ID_PORT_SHIFT 2 82 #define NODE_ID_X2B_MASK (0x3 << 3) 83 #define NODE_ID_X2B_SHIFT 3 84 #define NODE_ID_Y2B_MASK (0x3 << 5) 85 #define NODE_ID_Y2B_SHIFT 5 86 #define NODE_ID_X3B_MASK (0x7 << 3) 87 #define NODE_ID_X3B_SHIFT 3 88 #define NODE_ID_Y3B_MASK (0x7 << 6) 89 #define NODE_ID_Y3B_SHIFT 6 90 91 #define NODE_TYPE_INVALID 0x000 92 #define NODE_TYPE_DVM 0x001 93 #define NODE_TYPE_CFG 0x002 94 #define NODE_TYPE_DTC 0x003 95 #define NODE_TYPE_HN_I 0x004 96 #define NODE_TYPE_HN_F 0x005 97 #define NODE_TYPE_XP 0x006 98 #define NODE_TYPE_SBSX 0x007 99 #define NODE_TYPE_RN_I 0x00A 100 #define NODE_TYPE_RN_D 0x00D 101 #define NODE_TYPE_RN_SAM 0x00F 102 #define NODE_TYPE_CXRA 0x100 103 #define NODE_TYPE_CXHA 0x101 104 #define NODE_TYPE_CXLA 0x102 105 106 #define POR_CFGM_PERIPH_ID_0_PERIPH_ID_1 0x0008 /* ro */ 107 #define POR_CFGM_PERIPH_ID_2_PERIPH_ID_3 0x0010 /* ro */ 108 #define POR_CFGM_PERIPH_ID_2_REV_SHIFT 4 109 #define POR_CFGM_PERIPH_ID_2_REV_MASK 0xf0 110 #define POR_CFGM_PERIPH_ID_2_REV_R1P0 0 111 #define POR_CFGM_PERIPH_ID_2_REV_R1P1 1 112 #define POR_CFGM_PERIPH_ID_2_REV_R1P2 2 113 #define POR_CFGM_PERIPH_ID_2_REV_R1P3 3 114 #define POR_CFGM_PERIPH_ID_2_REV_R2P0 4 115 #define POR_CFGM_PERIPH_ID_4_PERIPH_ID_5 0x0018 /* ro */ 116 #define POR_CFGM_PERIPH_ID_6_PERIPH_ID_7 0x0020 /* ro */ 117 #define POR_CFGM_PERIPH_ID_32(x) (0x0008 + ((x) * 4)) /* ro 32 */ 118 #define POR_CFGM_COMPONENT_ID_0_COMPONENT_ID_1 0x0028 /* ro */ 119 #define POR_CFGM_COMPONENT_ID_2_COMPONENT_ID_3 0x0030 /* ro */ 120 #define POR_CFGM_CHILD_INFO 0x0080 /* ro */ 121 #define POR_CFGM_CHILD_INFO_CHILD_PTR_OFFSET_MASK 0xffff0000 122 #define POR_CFGM_CHILD_INFO_CHILD_PTR_OFFSET_SHIFT 16 123 #define POR_CFGM_CHILD_INFO_CHILD_COUNT_MASK 0x0000ffff 124 #define POR_CFGM_CHILD_INFO_CHILD_COUNT_SHIFT 0 125 #define POR_CFGM_SECURE_ACCESS 0x0980 /* rw */ 126 #define POR_CFGM_ERRGSR0 0x3000 /* ro */ 127 #define POR_CFGM_ERRGSR1 0x3008 /* ro */ 128 #define POR_CFGM_ERRGSR2 0x3010 /* ro */ 129 #define POR_CFGM_ERRGSR3 0x3018 /* ro */ 130 #define POR_CFGM_ERRGSR4 0x3020 /* ro */ 131 #define POR_CFGM_ERRGSR5 0x3080 /* ro */ 132 #define POR_CFGM_ERRGSR6 0x3088 /* ro */ 133 #define POR_CFGM_ERRGSR7 0x3090 /* ro */ 134 #define POR_CFGM_ERRGSR8 0x3098 /* ro */ 135 #define POR_CFGM_ERRGSR9 0x30a0 /* ro */ 136 #define POR_CFGM_ERRGSR(x) (0x3000 + ((x) * 8)) /* ro */ 137 #define POR_CFGM_ERRGSR0_ns 0x3100 /* ro */ 138 #define POR_CFGM_ERRGSR1_ns 0x3108 /* ro */ 139 #define POR_CFGM_ERRGSR2_ns 0x3110 /* ro */ 140 #define POR_CFGM_ERRGSR3_ns 0x3118 /* ro */ 141 #define POR_CFGM_ERRGSR4_ns 0x3120 /* ro */ 142 #define POR_CFGM_ERRGSR5_ns 0x3180 /* ro */ 143 #define POR_CFGM_ERRGSR6_ns 0x3188 /* ro */ 144 #define POR_CFGM_ERRGSR7_ns 0x3190 /* ro */ 145 #define POR_CFGM_ERRGSR8_ns 0x3198 /* ro */ 146 #define POR_CFGM_ERRGSR9_ns 0x31a0 /* ro */ 147 #define POR_CFGM_ERRGSR_ns(x) (0x3100 + ((x) * 8)) /* ro */ 148 #define POR_CFGM_ERRDEVAFF 0x3fa8 /* ro */ 149 #define POR_CFGM_ERRDEVARCH 0x3fb8 /* ro */ 150 #define POR_CFGM_ERRIDR 0x3fc8 /* ro */ 151 #define POR_CFGM_ERRPIDR45 0x3fd0 /* ro */ 152 #define POR_CFGM_ERRPIDR67 0x3fd8 /* ro */ 153 #define POR_CFGM_ERRPIDR01 0x3fe0 /* ro */ 154 #define POR_CFGM_ERRPIDR23 0x3fe8 /* ro */ 155 #define POR_CFGM_ERRCIDR01 0x3ff0 /* ro */ 156 #define POR_CFGM_ERRCIDR23 0x3ff8 /* ro */ 157 #define POR_INFO_GLOBAL 0x0900 /* ro */ 158 #define POR_INFO_GLOBAL_CHIC_MODE_EN (1UL << 49) /* CHI-C mode enable */ 159 #define POR_INFO_GLOBAL_R2_ENABLE (1UL << 48) /* CMN R2 feature enable */ 160 #define POR_INFO_GLOBAL_RNSAM_NUM_ADD_HASHED_TGT_SHIFT 36 /* Number of additional hashed target ID's supported by the RN SAM, beyond the local HNF count */ 161 #define POR_INFO_GLOBAL_RNSAM_NUM_ADD_HASHED_TGT_MASK (0x3fUL << 36) 162 #define POR_INFO_GLOBAL_NUM_REMOTE_RNF_SHIFT 28 /* Number of remote RN-F devices in the system when the CML feature is enabled */ 163 #define POR_INFO_GLOBAL_NUM_REMOTE_RNF_MASK (0xffUL << 28) 164 #define POR_INFO_GLOBAL_FLIT_PARITY_EN (1 << 25) /* Indicates whether parity checking is enabled in the transport layer on all flits sent on the interconnect */ 165 #define POR_INFO_GLOBAL_DATACHECK_EN (1 << 24) /* Indicates whether datacheck feature is enabled for CHI DAT flit */ 166 #define POR_INFO_GLOBAL_PHYSICAL_ADDRESS_WIDTH_SHIFT 16 /* Physical address width */ 167 #define POR_INFO_GLOBAL_PHYSICAL_ADDRESS_WIDTH_MASK (0xff << 16) 168 #define POR_INFO_GLOBAL_CHI_REQ_ADDR_WIDTH_SHIFT 8 /* REQ address width */ 169 #define POR_INFO_GLOBAL_CHI_REQ_ADDR_WIDTH_MASK (0xff << 8) 170 #define POR_INFO_GLOBAL_CHI_REQ_RSVDC_WIDTH_SHIFT 0 /* RSVDC field width in CHI REQ flit */ 171 #define POR_INFO_GLOBAL_CHI_REQ_RSVDC_WIDTH_MASK 0xff 172 173 #define POR_PPU_INT_ENABLE 0x1000 /* rw */ 174 #define POR_PPU_INT_STATUS 0x1008 /* w1c */ 175 #define POR_PPU_QACTIVE_HYST 0x1010 /* rw */ 176 #define POR_CFGM_CHILD_POINTER_0 0x0100 /* ro */ 177 #define POR_CFGM_CHILD_POINTER(x) (POR_CFGM_CHILD_POINTER_0 + ((x) * 8)) 178 #define POR_CFGM_CHILD_POINTER_EXT (1 << 31) 179 #define POR_CFGM_CHILD_POINTER_BASE_MASK 0x0fffffffUL 180 181 /* DN registers */ 182 #define POR_DN_NODE_INFO 0x0000 /* ro */ 183 #define POR_DN_CHILD_INFO 0x0080 /* ro */ 184 #define POR_DN_BUILD_INFO 0x0900 /* ro */ 185 #define POR_DN_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */ 186 #define POR_DN_AUX_CTL 0x0a00 /* rw */ 187 #define POR_DN_VMF0_CTRL 0x0c00 /* rw */ 188 #define POR_DN_VMF0_RNF0 0x0c08 /* rw */ 189 #define POR_DN_VMF0_RND 0x0c10 /* rw */ 190 #define POR_DN_VMF0_CXRA 0x0c18 /* rw */ 191 #define POR_DN_VMF1_CTRL 0x0c20 /* rw */ 192 #define POR_DN_VMF1_RNF0 0x0c28 /* rw */ 193 #define POR_DN_VMF1_RND 0x0c30 /* rw */ 194 #define POR_DN_VMF1_CXRA 0x0c38 /* rw */ 195 #define POR_DN_VMF2_CTRL 0x0c40 /* rw */ 196 #define POR_DN_VMF2_RNF0 0x0c48 /* rw */ 197 #define POR_DN_VMF2_RND 0x0c50 /* rw */ 198 #define POR_DN_VMF2_CXRA 0x0c58 /* rw */ 199 #define POR_DN_VMF3_CTRL 0x0c60 /* rw */ 200 #define POR_DN_VMF3_RNF0 0x0c68 /* rw */ 201 #define POR_DN_VMF3_RND 0x0c70 /* rw */ 202 #define POR_DN_VMF3_CXRA 0x0c78 /* rw */ 203 #define POR_DN_VMF4_CTRL 0x0c80 /* rw */ 204 #define POR_DN_VMF4_RNF0 0x0c88 /* rw */ 205 #define POR_DN_VMF4_RND 0x0c90 /* rw */ 206 #define POR_DN_VMF4_CXRA 0x0c98 /* rw */ 207 #define POR_DN_VMF5_CTRL 0x0ca0 /* rw */ 208 #define POR_DN_VMF5_RNF0 0x0ca8 /* rw */ 209 #define POR_DN_VMF5_RND 0x0cb0 /* rw */ 210 #define POR_DN_VMF5_CXRA 0x0cb8 /* rw */ 211 #define POR_DN_VMF6_CTRL 0x0cc0 /* rw */ 212 #define POR_DN_VMF6_RNF0 0x0cc8 /* rw */ 213 #define POR_DN_VMF6_RND 0x0cd0 /* rw */ 214 #define POR_DN_VMF6_CXRA 0x0cd8 /* rw */ 215 #define POR_DN_VMF7_CTRL 0x0ce0 /* rw */ 216 #define POR_DN_VMF7_RNF0 0x0ce8 /* rw */ 217 #define POR_DN_VMF7_RND 0x0cf0 /* rw */ 218 #define POR_DN_VMF7_CXRA 0x0cf8 /* rw */ 219 #define POR_DN_VMF8_CTRL 0x0d00 /* rw */ 220 #define POR_DN_VMF8_RNF0 0x0d08 /* rw */ 221 #define POR_DN_VMF8_RND 0x0d10 /* rw */ 222 #define POR_DN_VMF8_CXRA 0x0d18 /* rw */ 223 #define POR_DN_VMF9_CTRL 0x0d20 /* rw */ 224 #define POR_DN_VMF9_RNF0 0x0d28 /* rw */ 225 #define POR_DN_VMF9_RND 0x0d30 /* rw */ 226 #define POR_DN_VMF9_CXRA 0x0d38 /* rw */ 227 #define POR_DN_VMF10_CTRL 0x0d40 /* rw */ 228 #define POR_DN_VMF10_RNF0 0x0d48 /* rw */ 229 #define POR_DN_VMF10_RND 0x0d50 /* rw */ 230 #define POR_DN_VMF10_CXRA 0x0d58 /* rw */ 231 #define POR_DN_VMF11_CTRL 0x0d60 /* rw */ 232 #define POR_DN_VMF11_RNF0 0x0d68 /* rw */ 233 #define POR_DN_VMF11_RND 0x0d70 /* rw */ 234 #define POR_DN_VMF11_CXRA 0x0d78 /* rw */ 235 #define POR_DN_VMF12_CTRL 0x0d80 /* rw */ 236 #define POR_DN_VMF12_RNF0 0x0d88 /* rw */ 237 #define POR_DN_VMF12_RND 0x0d90 /* rw */ 238 #define POR_DN_VMF12_CXRA 0x0d98 /* rw */ 239 #define POR_DN_VMF13_CTRL 0x0da0 /* rw */ 240 #define POR_DN_VMF13_RNF0 0x0da8 /* rw */ 241 #define POR_DN_VMF13_RND 0x0db0 /* rw */ 242 #define POR_DN_VMF13_CXRA 0x0db8 /* rw */ 243 #define POR_DN_VMF14_CTRL 0x0dc0 /* rw */ 244 #define POR_DN_VMF14_RNF0 0x0dc8 /* rw */ 245 #define POR_DN_VMF14_RND 0x0dd0 /* rw */ 246 #define POR_DN_VMF14_CXRA 0x0dd8 /* rw */ 247 #define POR_DN_VMF15_CTRL 0x0de0 /* rw */ 248 #define POR_DN_VMF15_RNF0 0x0de8 /* rw */ 249 #define POR_DN_VMF15_RND 0x0df0 /* rw */ 250 #define POR_DN_VMF15_CXRA 0x0df8 /* rw */ 251 #define POR_DN_PMU_EVENT_SEL 0x2000 /* rw */ 252 #define POR_DN_PMU_EVENT_SEL_OCCUP1_ID_SHIFT 32 253 #define POR_DN_PMU_EVENT_SEL_OCCUP1_ID_MASK (0xf << 32) 254 #define POR_DN_PMU_EVENT_SEL_OCCUP1_ID_ALL 0 255 #define POR_DN_PMU_EVENT_SEL_OCCUP1_ID_DVM_OPS 1 256 #define POR_DN_PMU_EVENT_SEL_OCCUP1_ID_DVM_SYNCS 2 257 #define POR_DN_PMU_EVENT_SEL_EVENT_ID3_SHIFT 24 258 #define POR_DN_PMU_EVENT_SEL_EVENT_ID3_MASK (0x3f << 24) 259 #define POR_DN_PMU_EVENT_SEL_EVENT_ID2_SHIFT 16 260 #define POR_DN_PMU_EVENT_SEL_EVENT_ID2_MASK (0x3f << 16) 261 #define POR_DN_PMU_EVENT_SEL_EVENT_ID1_SHIFT 8 262 #define POR_DN_PMU_EVENT_SEL_EVENT_ID1_MASK (0x3f << 8) 263 #define POR_DN_PMU_EVENT_SEL_EVENT_ID0_SHIFT 0 264 #define POR_DN_PMU_EVENT_SEL_EVENT_ID0_MASK 0x3f 265 266 /* Debug and trace register */ 267 #define POR_DT_NODE_INFO 0x0000 /* ro */ 268 #define POR_DT_CHILD_INFO 0x0080 /* ro */ 269 #define POR_DT_SECURE_ACCESS 0x0980 /* rw */ 270 #define POR_DT_DTC_CTL 0x0a00 /* rw */ 271 #define POR_DT_DTC_CTL_DT_EN (1 << 0) 272 #define POR_DT_TRIGGER_STATUS 0x0a10 /* ro */ 273 #define POR_DT_TRIGGER_STATUS_CLR 0x0a20 /* wo */ 274 #define POR_DT_TRACE_CONTROL 0x0a30 /* rw */ 275 #define POR_DT_TRACEID 0x0a48 /* rw */ 276 #define POR_DT_PMEVCNTAB 0x2000 /* rw */ 277 #define POR_DT_PMEVCNTCD 0x2010 /* rw */ 278 #define POR_DT_PMEVCNTEF 0x2020 /* rw */ 279 #define POR_DT_PMEVCNTGH 0x2030 /* rw */ 280 #define POR_DT_PMEVCNT(x) (0x2000 + ((x) * 0x10)) 281 #define POR_DT_PMEVCNT_EVENCNT_SHIFT 0 282 #define POR_DT_PMEVCNT_ODDCNT_SHIFT 32 283 #define POR_DT_PMCCNTR 0x2040 /* rw */ 284 #define POR_DT_PMEVCNTSRAB 0x2050 /* rw */ 285 #define POR_DT_PMEVCNTSRCD 0x2060 /* rw */ 286 #define POR_DT_PMEVCNTSREF 0x2070 /* rw */ 287 #define POR_DT_PMEVCNTSRGH 0x2080 /* rw */ 288 #define POR_DT_PMCCNTRSR 0x2090 /* rw */ 289 #define POR_DT_PMCR 0x2100 /* rw */ 290 #define POR_DT_PMCR_OVFL_INTR_EN (1 << 6) 291 #define POR_DT_PMCR_CNTR_RST (1 << 5) 292 #define POR_DT_PMCR_CNTCFG_SHIFT 1 293 #define POR_DT_PMCR_CNTCFG_MASK (0xf << POR_DT_PMCR_CNTCFG_SHIFT) 294 #define POR_DT_PMCR_PMU_EN (1 << 0) 295 #define POR_DT_PMOVSR 0x2118 /* ro */ 296 #define POR_DT_PMOVSR_CLR 0x2120 /* wo */ 297 #define POR_DT_PMOVSR_EVENT_COUNTERS 0xffUL 298 #define POR_DT_PMOVSR_CYCLE_COUNTER 0x100UL 299 #define POR_DT_PMOVSR_ALL \ 300 (POR_DT_PMOVSR_EVENT_COUNTERS | POR_DT_PMOVSR_CYCLE_COUNTER) 301 #define POR_DT_PMSSR 0x2128 /* ro */ 302 #define POR_DT_PMSRR 0x2130 /* wo */ 303 #define POR_DT_CLAIM 0x2da0 /* rw */ 304 #define POR_DT_DEVAFF 0x2da8 /* ro */ 305 #define POR_DT_LSR 0x2db0 /* ro */ 306 #define POR_DT_AUTHSTATUS_DEVARCH 0x2db8 /* ro */ 307 #define POR_DT_DEVID 0x2dc0 /* ro */ 308 #define POR_DT_DEVTYPE 0x2dc8 /* ro */ 309 #define POR_DT_PIDR45 0x2dd0 /* ro */ 310 #define POR_DT_PIDR67 0x2dd8 /* ro */ 311 #define POR_DT_PIDR01 0x2de0 /* ro */ 312 #define POR_DT_PIDR23 0x2de8 /* ro */ 313 #define POR_DT_CIDR01 0x2df0 /* ro */ 314 #define POR_DT_CIDR23 0x2df8 /* ro */ 315 316 /* HN-F registers */ 317 #define POR_HNF_NODE_INFO 0x0000 /* ro */ 318 #define POR_HNF_CHILD_INFO 0x0080 /* ro */ 319 #define POR_HNF_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */ 320 #define POR_HNF_UNIT_INFO 0x0900 /* ro */ 321 #define POR_HNF_CFG_CTL 0x0a00 /* rw */ 322 #define POR_HNF_AUX_CTL 0x0a08 /* rw */ 323 #define POR_HNF_R2_AUX_CTL 0x0a10 /* rw */ 324 #define POR_HNF_PPU_PWPR 0x1000 /* rw */ 325 #define POR_HNF_PPU_PWSR 0x1008 /* ro */ 326 #define POR_HNF_PPU_MISR 0x1014 /* ro */ 327 #define POR_HNF_PPU_IDR0 0x1fb0 /* ro */ 328 #define POR_HNF_PPU_IDR1 0x1fb4 /* ro */ 329 #define POR_HNF_PPU_IIDR 0x1fc8 /* ro */ 330 #define POR_HNF_PPU_AIDR 0x1fcc /* ro */ 331 #define POR_HNF_PPU_DYN_RET_THRESHOLD 0x1100 /* rw */ 332 #define POR_HNF_QOS_BAND 0x0a80 /* ro */ 333 #define POR_HNF_QOS_RESERVATION 0x0a88 /* rw */ 334 #define POR_HNF_RN_STARVATION 0x0a90 /* rw */ 335 #define POR_HNF_ERRFR 0x3000 /* ro */ 336 #define POR_HNF_ERRCTLR 0x3008 /* rw */ 337 #define POR_HNF_ERRSTATUS 0x3010 /* w1c */ 338 #define POR_HNF_ERRADDR 0x3018 /* rw */ 339 #define POR_HNF_ERRMISC 0x3020 /* rw */ 340 #define POR_HNF_ERR_INJ 0x3030 /* rw */ 341 #define POR_HNF_BYTE_PAR_ERR_INJ 0x3038 /* wo */ 342 #define POR_HNF_ERRFR_NS 0x3100 /* ro */ 343 #define POR_HNF_ERRCTLR_NS 0x3108 /* rw */ 344 #define POR_HNF_ERRSTATUS_NS 0x3110 /* w1c */ 345 #define POR_HNF_ERRADDR_NS 0x3118 /* rw */ 346 #define POR_HNF_ERRMISC_NS 0x3120 /* rw */ 347 #define POR_HNF_SLC_LOCK_WAYS 0x0c00 /* rw */ 348 #define POR_HNF_SLC_LOCK_BASE0 0x0c08 /* rw */ 349 #define POR_HNF_SLC_LOCK_BASE1 0x0c10 /* rw */ 350 #define POR_HNF_SLC_LOCK_BASE2 0x0c18 /* rw */ 351 #define POR_HNF_SLC_LOCK_BASE3 0x0c20 /* rw */ 352 #define POR_HNF_RNF_REGION_VEC1 0x0c28 /* rw */ 353 #define POR_HNF_RNI_REGION_VEC 0x0c30 /* rw */ 354 #define POR_HNF_RNF_REGION_VEC 0x0c38 /* rw */ 355 #define POR_HNF_RND_REGION_VEC 0x0c40 /* rw */ 356 #define POR_HNF_SLCWAY_PARTITION0_RNF_VEC 0x0c48 /* rw */ 357 #define POR_HNF_SLCWAY_PARTITION1_RNF_VEC 0x0c50 /* rw */ 358 #define POR_HNF_SLCWAY_PARTITION2_RNF_VEC 0x0c58 /* rw */ 359 #define POR_HNF_SLCWAY_PARTITION3_RNF_VEC 0x0c60 /* rw */ 360 #define POR_HNF_SLCWAY_PARTITION0_RNF_VEC1 0x0cb0 /* rw */ 361 #define POR_HNF_SLCWAY_PARTITION1_RNF_VEC1 0x0cb8 /* rw */ 362 #define POR_HNF_SLCWAY_PARTITION2_RNF_VEC1 0x0cc0 /* rw */ 363 #define POR_HNF_SLCWAY_PARTITION3_RNF_VEC1 0x0cc8 /* rw */ 364 #define POR_HNF_SLCWAY_PARTITION0_RNI_VEC 0x0c68 /* rw */ 365 #define POR_HNF_SLCWAY_PARTITION1_RNI_VEC 0x0c70 /* rw */ 366 #define POR_HNF_SLCWAY_PARTITION2_RNI_VEC 0x0c78 /* rw */ 367 #define POR_HNF_SLCWAY_PARTITION3_RNI_VEC 0x0c80 /* rw */ 368 #define POR_HNF_SLCWAY_PARTITION0_RND_VEC 0x0c88 /* rw */ 369 #define POR_HNF_SLCWAY_PARTITION1_RND_VEC 0x0c90 /* rw */ 370 #define POR_HNF_SLCWAY_PARTITION2_RND_VEC 0x0c98 /* rw */ 371 #define POR_HNF_SLCWAY_PARTITION3_RND_VEC 0x0ca0 /* rw */ 372 #define POR_HNF_RN_REGION_LOCK 0x0ca8 /* rw */ 373 #define POR_HNF_SAM_CONTROL 0x0d00 /* rw */ 374 #define POR_HNF_SAM_MEMREGION0 0x0d08 /* rw */ 375 #define POR_HNF_SAM_MEMREGION1 0x0d10 /* rw */ 376 #define POR_HNF_SAM_SN_PROPERTIES 0x0d18 /* rw */ 377 #define POR_HNF_SAM_6SN_NODEID 0x0d20 /* rw */ 378 #define POR_HNF_RN_PHYS_ID(x) (0x0d28 + 8 * (x)) /* rw */ 379 #define POR_HNF_RN_PHYS_ID63 0x0f90 /* rw */ 380 #define POR_HNF_SF_CXG_BLOCKED_WAYS 0x0f00 /* rw */ 381 #define POR_HNF_CML_PORT_AGGR_GRP0_ADD_MASK 0x0f10 /* rw */ 382 #define POR_HNF_CML_PORT_AGGR_GRP1_ADD_MASK 0x0f18 /* rw */ 383 #define POR_HNF_CML_PORT_AGGR_GRP0_REG 0x0f28 /* rw */ 384 #define POR_HNF_CML_PORT_AGGR_GRP1_REG 0x0f30 /* rw */ 385 #define HN_SAM_HASH_ADDR_MASK_REG 0x0f40 /* rw */ 386 #define HN_SAM_REGION_CMP_ADDR_MASK_REG 0x0f48 /* rw */ 387 #define POR_HNF_ABF_LO_ADDR 0x0f50 /* rw */ 388 #define POR_HNF_ABF_HI_ADDR 0x0f58 /* rw */ 389 #define POR_HNF_ABF_PR 0x0f60 /* rw */ 390 #define POR_HNF_ABF_SR 0x0f68 /* ro */ 391 #define POR_HNF_LDID_MAP_TABLE_REG0 0x0f98 /* rw */ 392 #define POR_HNF_LDID_MAP_TABLE_REG1 0x0fa0 /* rw */ 393 #define POR_HNF_LDID_MAP_TABLE_REG2 0x0fa8 /* rw */ 394 #define POR_HNF_LDID_MAP_TABLE_REG3 0x0fb0 /* rw */ 395 #define POR_HNF_CFG_SLCSF_DBGRD 0x0b80 /* wo */ 396 #define POR_HNF_SLC_CACHE_ACCESS_SLC_TAG 0x0b88 /* ro */ 397 #define POR_HNF_SLC_CACHE_ACCESS_SLC_DATA 0x0b90 /* ro */ 398 #define POR_HNF_SLC_CACHE_ACCESS_SF_TAG 0x0b98 /* ro */ 399 #define POR_HNF_SLC_CACHE_ACCESS_SF_TAG1 0x0ba0 /* ro */ 400 #define POR_HNF_SLC_CACHE_ACCESS_SF_TAG2 0x0ba8 /* ro */ 401 #define POR_HNF_PMU_EVENT_SEL 0x2000 /* rw */ 402 403 /* HN-I registers */ 404 #define POR_HNI_NODE_INFO 0x0000 /* ro */ 405 #define POR_HNI_CHILD_INFO 0x0080 /* ro */ 406 #define POR_HNI_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */ 407 #define POR_HNI_UNIT_INFO 0x0900 /* ro */ 408 #define POR_HNI_SAM_ADDRREGION0_CFG 0x0c00 /* rw */ 409 #define POR_HNI_SAM_ADDRREGION1_CFG 0x0c08 /* rw */ 410 #define POR_HNI_SAM_ADDRREGION2_CFG 0x0c10 /* rw */ 411 #define POR_HNI_SAM_ADDRREGION3_CFG 0x0c18 /* rw */ 412 #define POR_HNI_CFG_CTL 0x0a00 /* rw */ 413 #define POR_HNI_AUX_CTL 0x0a08 /* rw */ 414 #define POR_HNI_ERRFR 0x3000 /* ro */ 415 #define POR_HNI_ERRCTLR 0x3008 /* rw */ 416 #define POR_HNI_ERRSTATUS 0x3010 /* w1c */ 417 #define POR_HNI_ERRADDR 0x3018 /* rw */ 418 #define POR_HNI_ERRMISC 0x3020 /* rw */ 419 #define POR_HNI_ERRFR_NS 0x3100 /* ro */ 420 #define POR_HNI_ERRCTLR_NS 0x3108 /* rw */ 421 #define POR_HNI_ERRSTATUS_NS 0x3110 /* w1c */ 422 #define POR_HNI_ERRADDR_NS 0x3118 /* rw */ 423 #define POR_HNI_ERRMISC_NS 0x3120 /* rw */ 424 #define POR_HNI_PMU_EVENT_SEL 0x2000 /* rw */ 425 426 /* XP registers */ 427 #define POR_MXP_NODE_INFO 0x0000 /* ro */ 428 #define POR_MXP_DEVICE_PORT_CONNECT_INFO_P0 0x0008 /* ro */ 429 #define POR_MXP_DEVICE_PORT_CONNECT_INFO_P1 0x0010 /* ro */ 430 #define POR_MXP_MESH_PORT_CONNECT_INFO_EAST 0x0018 /* ro */ 431 #define POR_MXP_MESH_PORT_CONNECT_INFO_NORTH 0x0020 /* ro */ 432 #define POR_MXP_CHILD_INFO 0x0080 /* ro */ 433 #define POR_MXP_CHILD_POINTER_0 0x0100 /* ro */ 434 #define POR_MXP_CHILD_POINTER_1 0x0108 /* ro */ 435 #define POR_MXP_CHILD_POINTER_2 0x0110 /* ro */ 436 #define POR_MXP_CHILD_POINTER_3 0x0118 /* ro */ 437 #define POR_MXP_CHILD_POINTER_4 0x0120 /* ro */ 438 #define POR_MXP_CHILD_POINTER_5 0x0128 /* ro */ 439 #define POR_MXP_CHILD_POINTER_6 0x0130 /* ro */ 440 #define POR_MXP_CHILD_POINTER_7 0x0138 /* ro */ 441 #define POR_MXP_CHILD_POINTER_8 0x0140 /* ro */ 442 #define POR_MXP_CHILD_POINTER_9 0x0148 /* ro */ 443 #define POR_MXP_CHILD_POINTER_10 0x0150 /* ro */ 444 #define POR_MXP_CHILD_POINTER_11 0x0158 /* ro */ 445 #define POR_MXP_CHILD_POINTER_12 0x0160 /* ro */ 446 #define POR_MXP_CHILD_POINTER_13 0x0168 /* ro */ 447 #define POR_MXP_CHILD_POINTER_14 0x0170 /* ro */ 448 #define POR_MXP_CHILD_POINTER_15 0x0178 /* ro */ 449 #define POR_MXP_P0_INFO 0x0900 /* ro */ 450 #define POR_MXP_P1_INFO 0x0908 /* ro */ 451 #define POR_MXP_PX_INFO_DEV_TYPE_RN_I 0x01 452 #define POR_MXP_PX_INFO_DEV_TYPE_RN_D 0x02 453 #define POR_MXP_PX_INFO_DEV_TYPE_RN_F_CHIB 0x04 454 #define POR_MXP_PX_INFO_DEV_TYPE_RN_F_CHIB_ESAM 0x05 455 #define POR_MXP_PX_INFO_DEV_TYPE_RN_F_CHIA 0x06 456 #define POR_MXP_PX_INFO_DEV_TYPE_RN_F_CHIA_ESAM 0x07 457 #define POR_MXP_PX_INFO_DEV_TYPE_HN_T 0x08 458 #define POR_MXP_PX_INFO_DEV_TYPE_HN_I 0x09 459 #define POR_MXP_PX_INFO_DEV_TYPE_HN_D 0x0a 460 #define POR_MXP_PX_INFO_DEV_TYPE_SN_F 0x0c 461 #define POR_MXP_PX_INFO_DEV_TYPE_SBSX 0x0d 462 #define POR_MXP_PX_INFO_DEV_TYPE_HN_F 0x0e 463 #define POR_MXP_PX_INFO_DEV_TYPE_CXHA 0x11 464 #define POR_MXP_PX_INFO_DEV_TYPE_CXRA 0x12 465 #define POR_MXP_PX_INFO_DEV_TYPE_CXRH 0x13 466 467 #define POR_MXP_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */ 468 #define POR_MXP_AUX_CTL 0x0a00 /* rw */ 469 #define POR_MXP_P0_QOS_CONTROL 0x0a80 /* rw */ 470 #define POR_MXP_P0_QOS_LAT_TGT 0x0a88 /* rw */ 471 #define POR_MXP_P0_QOS_LAT_SCALE 0x0a90 /* rw */ 472 #define POR_MXP_P0_QOS_LAT_RANGE 0x0a98 /* rw */ 473 #define POR_MXP_P1_QOS_CONTROL 0x0aa0 /* rw */ 474 #define POR_MXP_P1_QOS_LAT_TGT 0x0aa8 /* rw */ 475 #define POR_MXP_P1_QOS_LAT_SCALE 0x0ab0 /* rw */ 476 #define POR_MXP_P1_QOS_LAT_RANGE 0x0ab8 /* rw */ 477 #define POR_MXP_PMU_EVENT_SEL 0x2000 /* rw */ 478 479 #define POR_MXP_ERRFR 0x3000 /* ro */ 480 #define POR_MXP_ERRCTLR 0x3008 /* rw */ 481 #define POR_MXP_ERRSTATUS 0x3010 /* w1c */ 482 #define POR_MXP_ERRMISC 0x3028 /* rw */ 483 #define POR_MXP_P0_BYTE_PAR_ERR_INJ 0x3030 /* wo */ 484 #define POR_MXP_P1_BYTE_PAR_ERR_INJ 0x3038 /* wo */ 485 #define POR_MXP_ERRFR_NS 0x3100 /* ro */ 486 #define POR_MXP_ERRCTLR_NS 0x3108 /* rw */ 487 #define POR_MXP_ERRSTATUS_NS 0x3110 /* w1c */ 488 #define POR_MXP_ERRMISC_NS 0x3128 /* rw */ 489 #define POR_MXP_P0_SYSCOREQ_CTL 0x1000 /* rw */ 490 #define POR_MXP_P1_SYSCOREQ_CTL 0x1008 /* rw */ 491 #define POR_MXP_P0_SYSCOACK_STATUS 0x1010 /* ro */ 492 #define POR_MXP_P1_SYSCOACK_STATUS 0x1018 /* ro */ 493 #define POR_DTM_CONTROL 0x2100 /* rw */ 494 #define POR_DTM_CONTROL_TRACE_NO_ATB (1 << 3) 495 #define POR_DTM_CONTROL_SAMPLE_PROFILE_ENABLE (1 << 2) 496 #define POR_DTM_CONTROL_TRACE_TAG_ENABLE (1 << 1) 497 #define POR_DTM_CONTROL_DTM_ENABLE (1 << 0) 498 #define POR_DTM_FIFO_ENTRY_READY 0x2118 /* w1c */ 499 #define POR_DTM_FIFO_ENTRY0_0 0x2120 /* ro */ 500 #define POR_DTM_FIFO_ENTRY0_1 0x2128 /* ro */ 501 #define POR_DTM_FIFO_ENTRY0_2 0x2130 /* ro */ 502 #define POR_DTM_FIFO_ENTRY1_0 0x2138 /* ro */ 503 #define POR_DTM_FIFO_ENTRY1_1 0x2140 /* ro */ 504 #define POR_DTM_FIFO_ENTRY1_2 0x2148 /* ro */ 505 #define POR_DTM_FIFO_ENTRY2_0 0x2150 /* ro */ 506 #define POR_DTM_FIFO_ENTRY2_1 0x2158 /* ro */ 507 #define POR_DTM_FIFO_ENTRY2_2 0x2160 /* ro */ 508 #define POR_DTM_FIFO_ENTRY3_0 0x2168 /* ro */ 509 #define POR_DTM_FIFO_ENTRY3_1 0x2170 /* ro */ 510 #define POR_DTM_FIFO_ENTRY3_2 0x2178 /* ro */ 511 #define POR_DTM_WP0_CONFIG 0x21a0 /* rw */ 512 #define POR_DTM_WP0_VAL 0x21a8 /* rw */ 513 #define POR_DTM_WP0_MASK 0x21b0 /* rw */ 514 #define POR_DTM_WP1_CONFIG 0x21b8 /* rw */ 515 #define POR_DTM_WP1_VAL 0x21c0 /* rw */ 516 #define POR_DTM_WP1_MASK 0x21c8 /* rw */ 517 #define POR_DTM_WP2_CONFIG 0x21d0 /* rw */ 518 #define POR_DTM_WP2_VAL 0x21d8 /* rw */ 519 #define POR_DTM_WP2_MASK 0x21e0 /* rw */ 520 #define POR_DTM_WP3_CONFIG 0x21e8 /* rw */ 521 #define POR_DTM_WP3_VAL 0x21f0 /* rw */ 522 #define POR_DTM_WP3_MASK 0x21f8 /* rw */ 523 #define POR_DTM_PMSICR 0x2200 /* rw */ 524 #define POR_DTM_PMSIRR 0x2208 /* rw */ 525 #define POR_DTM_PMU_CONFIG 0x2210 /* rw */ 526 #define POR_DTM_PMU_CONFIG_PMU_EN (1 << 0) 527 #define POR_DTM_PMU_CONFIG_VCNT_INPUT_SEL_SHIFT 32 528 #define POR_DTM_PMU_CONFIG_VCNT_INPUT_SEL_WIDTH 8 529 #define POR_DTM_PMEVCNT 0x2220 /* rw */ 530 #define POR_DTM_PMEVCNT_CNTR_WIDTH 16 531 #define POR_DTM_PMEVCNTSR 0x2240 /* rw */ 532 533 /* RN-D registers */ 534 #define POR_RND_NODE_INFO 0x0000 /* ro */ 535 #define POR_RND_CHILD_INFO 0x0080 /* ro */ 536 #define POR_RND_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */ 537 #define POR_RND_UNIT_INFO 0x0900 /* ro */ 538 #define POR_RND_CFG_CTL 0x0a00 /* rw */ 539 #define POR_RND_AUX_CTL 0x0a08 /* rw */ 540 #define POR_RND_S0_PORT_CONTROL 0x0a10 /* rw */ 541 #define POR_RND_S1_PORT_CONTROL 0x0a18 /* rw */ 542 #define POR_RND_S2_PORT_CONTROL 0x0a20 /* rw */ 543 #define POR_RND_S0_QOS_CONTROL 0x0a80 /* rw */ 544 #define POR_RND_S0_QOS_LAT_TGT 0x0a88 /* rw */ 545 #define POR_RND_S0_QOS_LAT_SCALE 0x0a90 /* rw */ 546 #define POR_RND_S0_QOS_LAT_RANGE 0x0a98 /* rw */ 547 #define POR_RND_S1_QOS_CONTROL 0x0aa0 /* rw */ 548 #define POR_RND_S1_QOS_LAT_TGT 0x0aa8 /* rw */ 549 #define POR_RND_S1_QOS_LAT_SCALE 0x0ab0 /* rw */ 550 #define POR_RND_S1_QOS_LAT_RANGE 0x0ab8 /* rw */ 551 #define POR_RND_S2_QOS_CONTROL 0x0ac0 /* rw */ 552 #define POR_RND_S2_QOS_LAT_TGT 0x0ac8 /* rw */ 553 #define POR_RND_S2_QOS_LAT_SCALE 0x0ad0 /* rw */ 554 #define POR_RND_S2_QOS_LAT_RANGE 0x0ad8 /* rw */ 555 #define POR_RND_PMU_EVENT_SEL 0x2000 /* rw */ 556 #define POR_RND_SYSCOREQ_CTL 0x1000 /* rw */ 557 #define POR_RND_SYSCOACK_STATUS 0x1008 /* ro */ 558 559 /* RN-I registers */ 560 #define POR_RNI_NODE_INFO 0x0000 /* ro */ 561 #define POR_RNI_CHILD_INFO 0x0080 /* ro */ 562 #define POR_RNI_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */ 563 #define POR_RNI_UNIT_INFO 0x0900 /* ro */ 564 #define POR_RNI_CFG_CTL 0x0a00 /* rw */ 565 #define POR_RNI_AUX_CTL 0x0a08 /* rw */ 566 #define POR_RNI_S0_PORT_CONTROL 0x0a10 /* rw */ 567 #define POR_RNI_S1_PORT_CONTROL 0x0a18 /* rw */ 568 #define POR_RNI_S2_PORT_CONTROL 0x0a20 /* rw */ 569 #define POR_RNI_S0_QOS_CONTROL 0x0a80 /* rw */ 570 #define POR_RNI_S0_QOS_LAT_TGT 0x0a88 /* rw */ 571 #define POR_RNI_S0_QOS_LAT_SCALE 0x0a90 /* rw */ 572 #define POR_RNI_S0_QOS_LAT_RANGE 0x0a98 /* rw */ 573 #define POR_RNI_S1_QOS_CONTROL 0x0aa0 /* rw */ 574 #define POR_RNI_S1_QOS_LAT_TGT 0x0aa8 /* rw */ 575 #define POR_RNI_S1_QOS_LAT_SCALE 0x0ab0 /* rw */ 576 #define POR_RNI_S1_QOS_LAT_RANGE 0x0ab8 /* rw */ 577 #define POR_RNI_S2_QOS_CONTROL 0x0ac0 /* rw */ 578 #define POR_RNI_S2_QOS_LAT_TGT 0x0ac8 /* rw */ 579 #define POR_RNI_S2_QOS_LAT_SCALE 0x0ad0 /* rw */ 580 #define POR_RNI_S2_QOS_LAT_RANGE 0x0ad8 /* rw */ 581 #define POR_RNI_PMU_EVENT_SEL 0x2000 /* rw */ 582 583 /* RN SAM registers */ 584 #define POR_RNSAM_NODE_INFO 0x0000 /* ro */ 585 #define POR_RNSAM_CHILD_INFO 0x0080 /* ro */ 586 #define POR_RNSAM_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */ 587 #define POR_RNSAM_UNIT_INFO 0x0900 /* ro */ 588 #define RNSAM_STATUS 0x0c00 /* rw */ 589 #define NON_HASH_MEM_REGION_REG0 0x0c08 /* rw */ 590 #define NON_HASH_MEM_REGION_REG1 0x0c10 /* rw */ 591 #define NON_HASH_MEM_REGION_REG2 0x0c18 /* rw */ 592 #define NON_HASH_MEM_REGION_REG3 0x0c20 /* rw */ 593 #define NON_HASH_TGT_NODEID0 0x0c30 /* rw */ 594 #define NON_HASH_TGT_NODEID1 0x0c38 /* rw */ 595 #define NON_HASH_TGT_NODEID2 0x0c40 /* rw */ 596 #define SYS_CACHE_GRP_REGION0 0x0c48 /* rw */ 597 #define SYS_CACHE_GRP_REGION1 0x0c50 /* rw */ 598 #define SYS_CACHE_GRP_HN_NODEID_REG0 0x0c58 /* rw */ 599 #define SYS_CACHE_GRP_HN_NODEID_REG1 0x0c60 /* rw */ 600 #define SYS_CACHE_GRP_HN_NODEID_REG2 0x0c68 /* rw */ 601 #define SYS_CACHE_GRP_HN_NODEID_REG3 0x0c70 /* rw */ 602 #define SYS_CACHE_GRP_HN_NODEID_REG4 0x0c78 /* rw */ 603 #define SYS_CACHE_GRP_HN_NODEID_REG5 0x0c80 /* rw */ 604 #define SYS_CACHE_GRP_HN_NODEID_REG6 0x0c88 /* rw */ 605 #define SYS_CACHE_GRP_HN_NODEID_REG7 0x0c90 /* rw */ 606 #define SYS_CACHE_GRP_NONHASH_NODEID 0x0c98 /* rw */ 607 #define SYS_CACHE_GROUP_HN_COUNT 0x0d00 /* rw */ 608 #define SYS_CACHE_GRP_SN_NODEID_REG0 0x0d08 /* rw */ 609 #define SYS_CACHE_GRP_SN_NODEID_REG1 0x0d10 /* rw */ 610 #define SYS_CACHE_GRP_SN_NODEID_REG2 0x0d18 /* rw */ 611 #define SYS_CACHE_GRP_SN_NODEID_REG3 0x0d20 /* rw */ 612 #define SYS_CACHE_GRP_SN_NODEID_REG4 0x0d28 /* rw */ 613 #define SYS_CACHE_GRP_SN_NODEID_REG5 0x0d30 /* rw */ 614 #define SYS_CACHE_GRP_SN_NODEID_REG6 0x0d38 /* rw */ 615 #define SYS_CACHE_GRP_SN_NODEID_REG7 0x0d40 /* rw */ 616 #define SYS_CACHE_GRP_SN_SAM_CFG0 0x0d48 /* rw */ 617 #define SYS_CACHE_GRP_SN_SAM_CFG1 0x0d50 /* rw */ 618 #define GIC_MEM_REGION_REG 0x0d58 /* rw */ 619 #define SYS_CACHE_GRP_SN_ATTR 0x0d60 /* rw */ 620 #define SYS_CACHE_GRP_HN_CPA_EN_REG 0x0d68 /* rw */ 621 #define SYS_CACHE_GRP_HN_CPA_GRP_REG 0x0d70 /* rw */ 622 #define CML_PORT_AGGR_MODE_CTRL_REG 0x0e00 /* rw */ 623 #define CML_PORT_AGGR_GRP0_ADD_MASK 0x0e08 /* rw */ 624 #define CML_PORT_AGGR_GRP1_ADD_MASK 0x0e10 /* rw */ 625 #define CML_PORT_AGGR_GRP0_REG 0x0e40 /* rw */ 626 #define CML_PORT_AGGR_GRP1_REG 0x0e48 /* rw */ 627 #define SYS_CACHE_GRP_SECONDARY_REG0 0x0f00 /* rw */ 628 #define SYS_CACHE_GRP_SECONDARY_REG1 0x0f08 /* rw */ 629 #define SYS_CACHE_GRP_CAL_MODE_REG 0x0f10 /* rw */ 630 #define RNSAM_HASH_ADDR_MASK_REG 0x0f18 /* rw */ 631 #define RNSAM_REGION_CMP_ADDR_MASK_REG 0x0f20 /* rw */ 632 #define SYS_CACHE_GRP_HN_NODEID_REG8 0x0f58 /* rw */ 633 #define SYS_CACHE_GRP_HN_NODEID_REG9 0x0f60 /* rw */ 634 #define SYS_CACHE_GRP_HN_NODEID_REG10 0x0f68 /* rw */ 635 #define SYS_CACHE_GRP_HN_NODEID_REG11 0x0f70 /* rw */ 636 #define SYS_CACHE_GRP_HN_NODEID_REG12 0x0f78 /* rw */ 637 #define SYS_CACHE_GRP_HN_NODEID_REG13 0x0f80 /* rw */ 638 #define SYS_CACHE_GRP_HN_NODEID_REG14 0x0f88 /* rw */ 639 #define SYS_CACHE_GRP_HN_NODEID_REG15 0x0f90 /* rw */ 640 #define SYS_CACHE_GRP_SN_NODEID_REG8 0x1008 /* rw */ 641 #define SYS_CACHE_GRP_SN_NODEID_REG9 0x1010 /* rw */ 642 #define SYS_CACHE_GRP_SN_NODEID_REG10 0x1018 /* rw */ 643 #define SYS_CACHE_GRP_SN_NODEID_REG11 0x1020 /* rw */ 644 #define SYS_CACHE_GRP_SN_NODEID_REG12 0x1028 /* rw */ 645 #define SYS_CACHE_GRP_SN_NODEID_REG13 0x1030 /* rw */ 646 #define SYS_CACHE_GRP_SN_NODEID_REG14 0x1038 /* rw */ 647 #define SYS_CACHE_GRP_SN_NODEID_REG15 0x1040 /* rw */ 648 649 /* SBSX registers */ 650 #define POR_SBSX_NODE_INFO 0x0000 /* ro */ 651 #define POR_SBSX_CHILD_INFO 0x0080 /* ro */ 652 #define POR_SBSX_UNIT_INFO 0x0900 /* ro */ 653 #define POR_SBSX_AUX_CTL 0x0a08 /* rw */ 654 #define POR_SBSX_ERRFR 0x3000 /* ro */ 655 #define POR_SBSX_ERRCTLR 0x3008 /* rw */ 656 #define POR_SBSX_ERRSTATUS 0x3010 /* w1c */ 657 #define POR_SBSX_ERRADDR 0x3018 /* rw */ 658 #define POR_SBSX_ERRMISC 0x3020 /* rw */ 659 #define POR_SBSX_ERRFR_NS 0x3100 /* ro */ 660 #define POR_SBSX_ERRCTLR_NS 0x3108 /* rw */ 661 #define POR_SBSX_ERRSTATUS_NS 0x3110 /* w1c */ 662 #define POR_SBSX_ERRADDR_NS 0x3118 /* rw */ 663 #define POR_SBSX_ERRMISC_NS 0x3120 /* rw */ 664 #define POR_SBSX_PMU_EVENT_SEL 0x2000 /* rw */ 665 666 /* CXHA registers */ 667 #define POR_CXG_HA_NODE_INFO 0x0000 /* ro */ 668 #define POR_CXG_HA_ID 0x0008 /* rw */ 669 #define POR_CXG_HA_CHILD_INFO 0x0080 /* ro */ 670 #define POR_CXG_HA_AUX_CTL 0x0a08 /* rw */ 671 #define POR_CXG_HA_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */ 672 #define POR_CXG_HA_UNIT_INFO 0x0900 /* ro */ 673 #define POR_CXG_HA_RNF_RAID_TO_LDID_REG0 0x0c00 /* rw */ 674 #define POR_CXG_HA_RNF_RAID_TO_LDID_REG1 0x0c08 /* rw */ 675 #define POR_CXG_HA_RNF_RAID_TO_LDID_REG2 0x0c10 /* rw */ 676 #define POR_CXG_HA_RNF_RAID_TO_LDID_REG3 0x0c18 /* rw */ 677 #define POR_CXG_HA_RNF_RAID_TO_LDID_REG4 0x0c20 /* rw */ 678 #define POR_CXG_HA_RNF_RAID_TO_LDID_REG5 0x0c28 /* rw */ 679 #define POR_CXG_HA_RNF_RAID_TO_LDID_REG6 0x0c30 /* rw */ 680 #define POR_CXG_HA_RNF_RAID_TO_LDID_REG7 0x0c38 /* rw */ 681 #define POR_CXG_HA_AGENTID_TO_LINKID_REG0 0x0c40 /* rw */ 682 #define POR_CXG_HA_AGENTID_TO_LINKID_REG1 0x0c48 /* rw */ 683 #define POR_CXG_HA_AGENTID_TO_LINKID_REG2 0x0c50 /* rw */ 684 #define POR_CXG_HA_AGENTID_TO_LINKID_REG3 0x0c58 /* rw */ 685 #define POR_CXG_HA_AGENTID_TO_LINKID_REG4 0x0c60 /* rw */ 686 #define POR_CXG_HA_AGENTID_TO_LINKID_REG5 0x0c68 /* rw */ 687 #define POR_CXG_HA_AGENTID_TO_LINKID_REG6 0x0c70 /* rw */ 688 #define POR_CXG_HA_AGENTID_TO_LINKID_REG7 0x0c78 /* rw */ 689 #define POR_CXG_HA_AGENTID_TO_LINKID_VAL 0x0d00 /* rw */ 690 #define POR_CXG_HA_RNF_RAID_TO_LDID_VAL 0x0d08 /* rw */ 691 #define POR_CXG_HA_PMU_EVENT_SEL 0x2000 /* rw */ 692 #define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID3_SHIFT 24 693 #define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID3_MASK (0x3f << 24) 694 #define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID2_SHIFT 16 695 #define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID2_MASK (0x3f << 16) 696 #define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID1_SHIFT 8 697 #define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID1_MASK (0x3f << 8) 698 #define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID0_SHIFT 0 699 #define POR_CXG_HA_PMU_EVENT_SEL_EVENT_ID0_MASK 0x3f 700 701 #define POR_CXG_HA_CXPRTCL_LINK0_CTL 0x1000 /* rw */ 702 #define POR_CXG_HA_CXPRTCL_LINK0_STATUS 0x1008 /* ro */ 703 #define POR_CXG_HA_CXPRTCL_LINK1_CTL 0x1010 /* rw */ 704 #define POR_CXG_HA_CXPRTCL_LINK1_STATUS 0x1018 /* ro */ 705 #define POR_CXG_HA_CXPRTCL_LINK2_CTL 0x1020 /* rw */ 706 #define POR_CXG_HA_CXPRTCL_LINK2_STATUS 0x1028 /* ro */ 707 #define POR_CXG_HA_ERRFR 0x3000 /* ro */ 708 #define POR_CXG_HA_ERRCTLR 0x3008 /* rw */ 709 #define POR_CXG_HA_ERRSTATUS 0x3010 /* w1c */ 710 #define POR_CXG_HA_ERRADDR 0x3018 /* rw */ 711 #define POR_CXG_HA_ERRMISC 0x3020 /* rw */ 712 #define POR_CXG_HA_ERRFR_NS 0x3100 /* ro */ 713 #define POR_CXG_HA_ERRCTLR_NS 0x3108 /* rw */ 714 #define POR_CXG_HA_ERRSTATUS_NS 0x3110 /* w1c */ 715 #define POR_CXG_HA_ERRADDR_NS 0x3118 /* rw */ 716 #define POR_CXG_HA_ERRMISC_NS 0x3120 /* rw */ 717 718 /* CXRA registers */ 719 #define POR_CXG_RA_NODE_INFO 0x0000 /* ro */ 720 #define POR_CXG_RA_CHILD_INFO 0x0080 /* ro */ 721 #define POR_CXG_RA_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */ 722 #define POR_CXG_RA_UNIT_INFO 0x0900 /* ro */ 723 #define POR_CXG_RA_CFG_CTL 0x0a00 /* rw */ 724 #define EN_CXLA_PMUCMD_PROP (1 << 8) 725 #define POR_CXG_RA_AUX_CTL 0x0a08 /* rw */ 726 #define POR_CXG_RA_SAM_ADDR_REGION_REG0 0x0da8 /* rw */ 727 #define POR_CXG_RA_SAM_ADDR_REGION_REG1 0x0db0 /* rw */ 728 #define POR_CXG_RA_SAM_ADDR_REGION_REG2 0x0db8 /* rw */ 729 #define POR_CXG_RA_SAM_ADDR_REGION_REG3 0x0dc0 /* rw */ 730 #define POR_CXG_RA_SAM_ADDR_REGION_REG4 0x0dc8 /* rw */ 731 #define POR_CXG_RA_SAM_ADDR_REGION_REG5 0x0dd0 /* rw */ 732 #define POR_CXG_RA_SAM_ADDR_REGION_REG6 0x0dd8 /* rw */ 733 #define POR_CXG_RA_SAM_ADDR_REGION_REG7 0x0de0 /* rw */ 734 #define POR_CXG_RA_SAM_MEM_REGION0_LIMIT_REG 0x0e00 /* rw */ 735 #define POR_CXG_RA_SAM_MEM_REGION1_LIMIT_REG 0x0e08 /* rw */ 736 #define POR_CXG_RA_SAM_MEM_REGION2_LIMIT_REG 0x0e10 /* rw */ 737 #define POR_CXG_RA_SAM_MEM_REGION3_LIMIT_REG 0x0e18 /* rw */ 738 #define POR_CXG_RA_SAM_MEM_REGION4_LIMIT_REG 0x0e20 /* rw */ 739 #define POR_CXG_RA_SAM_MEM_REGION5_LIMIT_REG 0x0e28 /* rw */ 740 #define POR_CXG_RA_SAM_MEM_REGION6_LIMIT_REG 0x0e30 /* rw */ 741 #define POR_CXG_RA_SAM_MEM_REGION7_LIMIT_REG 0x0e38 /* rw */ 742 #define POR_CXG_RA_AGENTID_TO_LINKID_REG0 0x0e60 /* rw */ 743 #define POR_CXG_RA_AGENTID_TO_LINKID_REG1 0x0e68 /* rw */ 744 #define POR_CXG_RA_AGENTID_TO_LINKID_REG2 0x0e70 /* rw */ 745 #define POR_CXG_RA_AGENTID_TO_LINKID_REG3 0x0e78 /* rw */ 746 #define POR_CXG_RA_AGENTID_TO_LINKID_REG4 0x0e80 /* rw */ 747 #define POR_CXG_RA_AGENTID_TO_LINKID_REG5 0x0e88 /* rw */ 748 #define POR_CXG_RA_AGENTID_TO_LINKID_REG6 0x0e90 /* rw */ 749 #define POR_CXG_RA_AGENTID_TO_LINKID_REG7 0x0e98 /* rw */ 750 #define POR_CXG_RA_RNF_LDID_TO_RAID_REG0 0x0ea0 /* rw */ 751 #define POR_CXG_RA_RNF_LDID_TO_RAID_REG1 0x0ea8 /* rw */ 752 #define POR_CXG_RA_RNF_LDID_TO_RAID_REG2 0x0eb0 /* rw */ 753 #define POR_CXG_RA_RNF_LDID_TO_RAID_REG3 0x0eb8 /* rw */ 754 #define POR_CXG_RA_RNF_LDID_TO_RAID_REG4 0x0ec0 /* rw */ 755 #define POR_CXG_RA_RNF_LDID_TO_RAID_REG5 0x0ec8 /* rw */ 756 #define POR_CXG_RA_RNF_LDID_TO_RAID_REG6 0x0ed0 /* rw */ 757 #define POR_CXG_RA_RNF_LDID_TO_RAID_REG7 0x0ed8 /* rw */ 758 #define POR_CXG_RA_RNI_LDID_TO_RAID_REG0 0x0ee0 /* rw */ 759 #define POR_CXG_RA_RNI_LDID_TO_RAID_REG1 0x0ee8 /* rw */ 760 #define POR_CXG_RA_RNI_LDID_TO_RAID_REG2 0x0ef0 /* rw */ 761 #define POR_CXG_RA_RNI_LDID_TO_RAID_REG3 0x0ef8 /* rw */ 762 #define POR_CXG_RA_RND_LDID_TO_RAID_REG0 0x0f00 /* rw */ 763 #define POR_CXG_RA_RND_LDID_TO_RAID_REG1 0x0f08 /* rw */ 764 #define POR_CXG_RA_RND_LDID_TO_RAID_REG2 0x0f10 /* rw */ 765 #define POR_CXG_RA_RND_LDID_TO_RAID_REG3 0x0f18 /* rw */ 766 #define POR_CXG_RA_AGENTID_TO_LINKID_VAL 0x0f20 /* rw */ 767 #define POR_CXG_RA_RNF_LDID_TO_RAID_VAL 0x0f28 /* rw */ 768 #define POR_CXG_RA_RNI_LDID_TO_RAID_VAL 0x0f30 /* rw */ 769 #define POR_CXG_RA_RND_LDID_TO_RAID_VAL 0x0f38 /* rw */ 770 #define POR_CXG_RA_PMU_EVENT_SEL 0x2000 /* rw */ 771 #define POR_CXG_RA_CXPRTCL_LINK0_CTL 0x1000 /* rw */ 772 #define POR_CXG_RA_CXPRTCL_LINK0_STATUS 0x1008 /* ro */ 773 #define POR_CXG_RA_CXPRTCL_LINK1_CTL 0x1010 /* rw */ 774 #define POR_CXG_RA_CXPRTCL_LINK1_STATUS 0x1018 /* ro */ 775 #define POR_CXG_RA_CXPRTCL_LINK2_CTL 0x1020 /* rw */ 776 #define POR_CXG_RA_CXPRTCL_LINK2_STATUS 0x1028 /* ro */ 777 778 /* CXLA registers */ 779 #define POR_CXLA_NODE_INFO 0x0000 /* ro */ 780 #define POR_CXLA_CHILD_INFO 0x0080 /* ro */ 781 #define POR_CXLA_SECURE_REGISTER_GROUPS_OVERRIDE 0x0980 /* rw */ 782 #define POR_CXLA_UNIT_INFO 0x0900 /* ro */ 783 #define POR_CXLA_AUX_CTL 0x0a08 /* rw */ 784 #define POR_CXLA_CCIX_PROP_CAPABILITIES 0x0c00 /* ro */ 785 #define POR_CXLA_CCIX_PROP_CONFIGURED 0x0c08 /* rw */ 786 #define POR_CXLA_TX_CXS_ATTR_CAPABILITIES 0x0c10 /* ro */ 787 #define POR_CXLA_RX_CXS_ATTR_CAPABILITIES 0x0c18 /* ro */ 788 #define POR_CXLA_AGENTID_TO_LINKID_REG0 0x0c30 /* rw */ 789 #define POR_CXLA_AGENTID_TO_LINKID_REG1 0x0c38 /* rw */ 790 #define POR_CXLA_AGENTID_TO_LINKID_REG2 0x0c40 /* rw */ 791 #define POR_CXLA_AGENTID_TO_LINKID_REG3 0x0c48 /* rw */ 792 #define POR_CXLA_AGENTID_TO_LINKID_REG4 0x0c50 /* rw */ 793 #define POR_CXLA_AGENTID_TO_LINKID_REG5 0x0c58 /* rw */ 794 #define POR_CXLA_AGENTID_TO_LINKID_REG6 0x0c60 /* rw */ 795 #define POR_CXLA_AGENTID_TO_LINKID_REG7 0x0c68 /* rw */ 796 #define POR_CXLA_AGENTID_TO_LINKID_VAL 0x0c70 /* rw */ 797 #define POR_CXLA_LINKID_TO_PCIE_BUS_NUM 0x0c78 /* rw */ 798 #define POR_CXLA_PERMSG_PYLD_0_63 0x0d00 /* rw */ 799 #define POR_CXLA_PERMSG_PYLD_64_127 0x0d08 /* rw */ 800 #define POR_CXLA_PERMSG_PYLD_128_191 0x0d10 /* rw */ 801 #define POR_CXLA_PERMSG_PYLD_192_255 0x0d18 /* rw */ 802 #define POR_CXLA_PERMSG_CTL 0x0d20 /* rw */ 803 #define POR_CXLA_ERR_AGENT_ID 0x0d28 /* rw */ 804 #define POR_CXLA_PMU_EVENT_SEL 0x2000 /* rw */ 805 #define POR_CXLA_PMU_CONFIG 0x2210 /* rw */ 806 #define POR_CXLA_PMEVCNT 0x2220 /* rw */ 807 #define POR_CXLA_PMEVCNTSR 0x2240 /* rw */ 808 809 #endif /* _MACHINE_CMN600_REG_H_ */
Cache object: 5d64b9abef3c16742e079efdb40e0470
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