Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm64/nvidia/tegra210/max77620.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2020 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _MAX77620_H_ 31 32 #include <sys/clock.h> 33 34 #define MAX77620_REG_CNFGGLBL1 0x00 35 #define MAX77620_REG_CNFGGLBL2 0x01 36 #define MAX77620_REG_CNFGGLBL3 0x02 37 #define MAX77620_REG_CNFG1_32K 0x03 38 #define MAX77620_REG_CNFGBBC 0x04 39 #define MAX77620_REG_IRQTOP 0x05 40 #define MAX77620_REG_INTLBT 0x06 41 #define MAX77620_REG_IRQSD 0x07 42 #define MAX77620_REG_IRQ_LVL2_L0_7 0x08 43 #define MAX77620_REG_IRQ_LVL2_L8 0x09 44 #define MAX77620_REG_IRQ_LVL2_GPIO 0x0A 45 #define MAX77620_REG_ONOFFIRQ 0x0B 46 #define MAX77620_REG_NVERC 0x0C 47 #define MAX77620_REG_IRQTOPM 0x0D 48 #define MAX77620_REG_INTENLBT 0x0E 49 #define MAX77620_REG_IRQMASKSD 0x0F 50 #define MAX77620_REG_IRQ_MSK_L0_7 0x10 51 #define MAX77620_REG_IRQ_MSK_L8 0x11 52 #define MAX77620_REG_ONOFFIRQM 0x12 53 #define MAX77620_REG_STATLBT 0x13 54 #define MAX77620_REG_STATSD 0x14 55 #define MAX77620_REG_ONOFFSTAT 0x15 56 #define MAX77620_REG_SD0 0x16 57 #define MAX77620_SD0_VSEL_MASK 0x3F 58 59 #define MAX77620_REG_SD1 0x17 60 #define MAX77620_SD1_VSEL_MASK 0x7F 61 62 #define MAX77620_REG_SD2 0x18 63 #define MAX77620_REG_SD3 0x19 64 #define MAX77620_REG_SD4 0x1A 65 #define MAX77620_SDX_VSEL_MASK 0xFF 66 67 #define MAX77620_REG_DVSSD0 0x1B 68 #define MAX77620_REG_DVSSD1 0x1C 69 #define MAX77620_REG_CFG_SD0 0x1D 70 #define MAX77620_REG_CFG_SD1 0x1E 71 #define MAX77620_REG_CFG_SD2 0x1F 72 #define MAX77620_REG_CFG_SD3 0x20 73 #define MAX77620_REG_CFG_SD4 0x21 74 #define MAX77620_SD_SR_MASK 0xC0 75 #define MAX77620_SD_SR_SHIFT 6 76 #define MAX77620_SD_POWER_MODE_MASK 0x30 77 #define MAX77620_SD_POWER_MODE_SHIFT 4 78 #define MAX77620_SD_FPWM_MASK 0x04 79 #define MAX77620_SD_FPWM_SHIFT 2 80 #define MAX77620_SD_FSRADE_MASK 0x01 81 #define MAX77620_SD_FSRADE_SHIFT 0 82 83 #define MAX77620_REG_CFG2_SD 0x22 84 #define MAX77620_REG_CFG_LDO0 0x23 85 #define MAX77620_REG_CFG2_LDO0 0x24 86 #define MAX77620_REG_CFG_LDO1 0x25 87 #define MAX77620_REG_CFG2_LDO1 0x26 88 #define MAX77620_REG_CFG_LDO2 0x27 89 #define MAX77620_REG_CFG2_LDO2 0x28 90 #define MAX77620_REG_CFG_LDO3 0x29 91 #define MAX77620_REG_CFG2_LDO3 0x2A 92 #define MAX77620_REG_CFG_LDO4 0x2B 93 #define MAX77620_REG_CFG2_LDO4 0x2C 94 #define MAX77620_REG_CFG_LDO5 0x2D 95 #define MAX77620_REG_CFG2_LDO5 0x2E 96 #define MAX77620_REG_CFG_LDO6 0x2F 97 #define MAX77620_REG_CFG2_LDO6 0x30 98 #define MAX77620_REG_CFG_LDO7 0x31 99 #define MAX77620_REG_CFG2_LDO7 0x32 100 #define MAX77620_REG_CFG_LDO8 0x33 101 #define MAX77620_LDO_POWER_MODE_MASK 0xC0 102 #define MAX77620_LDO_POWER_MODE_SHIFT 6 103 #define MAX77620_LDO_VSEL_MASK 0x3F 104 105 #define MAX77620_REG_CFG2_LDO8 0x34 106 #define MAX77620_LDO_SLEW_RATE_MASK 0x1 107 #define MAX77620_LDO_SLEW_RATE_SHIFT 0x0 108 109 #define MAX77620_REG_CFG3_LDO 0x35 110 111 #define MAX77620_REG_GPIO0 0x36 112 #define MAX77620_REG_GPIO1 0x37 113 #define MAX77620_REG_GPIO2 0x38 114 #define MAX77620_REG_GPIO3 0x39 115 #define MAX77620_REG_GPIO4 0x3A 116 #define MAX77620_REG_GPIO5 0x3B 117 #define MAX77620_REG_GPIO6 0x3C 118 #define MAX77620_REG_GPIO7 0x3D 119 #define MAX77620_REG_GPIO_INT_GET(x) (((x) >> 5) & 0x3) 120 #define MAX77620_REG_GPIO_INT(x) (((x) & 0x3) << 5) 121 #define MAX77620_REG_GPIO_INT_NONE 0 122 #define MAX77620_REG_GPIO_INT_FALLING 1 123 #define MAX77620_REG_GPIO_INT_RISING 2 124 #define MAX77620_REG_GPIO_INT_BOTH 3 125 #define MAX77620_REG_GPIO_OUTPUT_VAL_GET(x) (((x) >> 3) & 0x1) 126 #define MAX77620_REG_GPIO_OUTPUT_VAL(x) (((x) & 0x1) << 3) 127 #define MAX77620_REG_GPIO_INPUT_VAL_GET(x) (((x) << 2) & 0x1) 128 #define MAX77620_REG_GPIO_INPUT_VAL (1 << 2) 129 #define MAX77620_REG_GPIO_DRV_GET(x) (((x) >> 0) & 0x1) 130 #define MAX77620_REG_GPIO_DRV(x) (((x) & 0x1) << 0) 131 #define MAX77620_REG_GPIO_DRV_PUSHPULL 1 132 #define MAX77620_REG_GPIO_DRV_OPENDRAIN 0 133 134 #define MAX77620_REG_PUE_GPIO 0x3E 135 #define MAX77620_REG_PDE_GPIO 0x3F 136 #define MAX77620_REG_AME_GPIO 0x40 137 #define MAX77620_REG_ONOFFCNFG1 0x41 138 #define MAX77620_REG_ONOFFCNFG2 0x42 139 140 #define MAX77620_REG_FPS_CFG0 0x43 141 #define MAX77620_REG_FPS_CFG1 0x44 142 #define MAX77620_REG_FPS_CFG2 0x45 143 #define MAX77620_FPS_TIME_PERIOD_MASK 0x38 144 #define MAX77620_FPS_TIME_PERIOD_SHIFT 3 145 #define MAX77620_FPS_EN_SRC_MASK 0x06 146 #define MAX77620_FPS_EN_SRC_SHIFT 1 147 #define MAX77620_FPS_ENFPS_SW_MASK 0x01 148 #define MAX77620_FPS_ENFPS_SW 0x01 149 150 #define MAX77620_REG_FPS_LDO0 0x46 151 #define MAX77620_REG_FPS_LDO1 0x47 152 #define MAX77620_REG_FPS_LDO2 0x48 153 #define MAX77620_REG_FPS_LDO3 0x49 154 #define MAX77620_REG_FPS_LDO4 0x4A 155 #define MAX77620_REG_FPS_LDO5 0x4B 156 #define MAX77620_REG_FPS_LDO6 0x4C 157 #define MAX77620_REG_FPS_LDO7 0x4D 158 #define MAX77620_REG_FPS_LDO8 0x4E 159 #define MAX77620_REG_FPS_SD0 0x4F 160 #define MAX77620_REG_FPS_SD1 0x50 161 #define MAX77620_REG_FPS_SD2 0x51 162 #define MAX77620_REG_FPS_SD3 0x52 163 #define MAX77620_REG_FPS_SD4 0x53 164 #define MAX77620_REG_FPS_GPIO1 0x54 165 #define MAX77620_REG_FPS_GPIO2 0x55 166 #define MAX77620_REG_FPS_GPIO3 0x56 167 #define MAX77620_REG_FPS_RSO 0x57 168 #define MAX77620_FPS_SRC_MASK 0xC0 169 #define MAX77620_FPS_SRC_SHIFT 6 170 #define MAX77620_FPS_PU_PERIOD_MASK 0x38 171 #define MAX77620_FPS_PU_PERIOD_SHIFT 3 172 #define MAX77620_FPS_PD_PERIOD_MASK 0x07 173 #define MAX77620_FPS_PD_PERIOD_SHIFT 0 174 175 #define MAX77620_REG_CID0 0x58 176 #define MAX77620_REG_CID1 0x59 177 #define MAX77620_REG_CID2 0x5A 178 #define MAX77620_REG_CID3 0x5B 179 #define MAX77620_REG_CID4 0x5C 180 #define MAX77620_REG_CID5 0x5D 181 #define MAX77620_REG_DVSSD4 0x5E 182 #define MAX20024_REG_MAX_ADD 0x70 183 184 /* MIsc FPS definitions. */ 185 #define MAX77620_FPS_COUNT 3 186 #define MAX77620_FPS_PERIOD_MIN_US 40 187 #define MAX77620_FPS_PERIOD_MAX_US 2560 188 189 /* Power modes */ 190 #define MAX77620_POWER_MODE_NORMAL 3 191 #define MAX77620_POWER_MODE_LPM 2 192 #define MAX77620_POWER_MODE_GLPM 1 193 #define MAX77620_POWER_MODE_DISABLE 0 194 195 196 struct max77620_reg_sc; 197 struct max77620_gpio_pin; 198 199 struct max77620_softc { 200 device_t dev; 201 struct sx lock; 202 int bus_addr; 203 struct resource *irq_res; 204 void *irq_h; 205 206 int shutdown_fps[MAX77620_FPS_COUNT]; 207 int suspend_fps[MAX77620_FPS_COUNT]; 208 int event_source[MAX77620_FPS_COUNT]; 209 210 /* Regulators. */ 211 struct max77620_reg_sc **regs; 212 int nregs; 213 214 /* GPIO */ 215 device_t gpio_busdev; 216 struct max77620_gpio_pin **gpio_pins; 217 int gpio_npins; 218 struct sx gpio_lock; 219 uint8_t gpio_reg_pue; /* pull-up enables */ 220 uint8_t gpio_reg_pde; /* pull-down enables */ 221 uint8_t gpio_reg_ame; /* alternate fnc */ 222 223 224 }; 225 226 #define RD1(sc, reg, val) max77620_read(sc, reg, val) 227 #define WR1(sc, reg, val) max77620_write(sc, reg, val) 228 #define RM1(sc, reg, clr, set) max77620_modify(sc, reg, clr, set) 229 230 int max77620_read(struct max77620_softc *sc, uint8_t reg, uint8_t *val); 231 int max77620_write(struct max77620_softc *sc, uint8_t reg, uint8_t val); 232 int max77620_modify(struct max77620_softc *sc, uint8_t reg, uint8_t clear, 233 uint8_t set); 234 int max77620_read_buf(struct max77620_softc *sc, uint8_t reg, uint8_t *buf, 235 size_t size); 236 int max77620_write_buf(struct max77620_softc *sc, uint8_t reg, uint8_t *buf, 237 size_t size); 238 239 /* Regulators */ 240 int max77620_regulator_attach(struct max77620_softc *sc, phandle_t node); 241 int max77620_regulator_map(device_t dev, phandle_t xref, int ncells, 242 pcell_t *cells, intptr_t *num); 243 244 /* RTC */ 245 int max77620_rtc_create(struct max77620_softc *sc, phandle_t node); 246 247 /* GPIO */ 248 device_t max77620_gpio_get_bus(device_t dev); 249 int max77620_gpio_pin_max(device_t dev, int *maxpin); 250 int max77620_gpio_pin_getname(device_t dev, uint32_t pin, char *name); 251 int max77620_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags); 252 int max77620_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps); 253 int max77620_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags); 254 int max77620_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value); 255 int max77620_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val); 256 int max77620_gpio_pin_toggle(device_t dev, uint32_t pin); 257 int max77620_gpio_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent, 258 int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags); 259 int max77620_gpio_attach(struct max77620_softc *sc, phandle_t node); 260 int max77620_pinmux_configure(device_t dev, phandle_t cfgxref); 261 262 #endif /* _MAX77620_H_ */
Cache object: 9439826a334fe812f880884003ff0209
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