Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/arm64/nvidia/tegra210/tegra210_clk_per.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2020 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/rman.h> 37 38 #include <machine/bus.h> 39 40 #include <dev/extres/clk/clk.h> 41 42 #include <dt-bindings/clock/tegra210-car.h> 43 #include <dt-bindings/reset/tegra210-car.h> 44 45 #include "tegra210_car.h" 46 47 /* Bits in base register. */ 48 #define PERLCK_AMUX_MASK 0x0F 49 #define PERLCK_AMUX_SHIFT 16 50 #define PERLCK_AMUX_DIS (1 << 20) 51 #define PERLCK_UDIV_DIS (1 << 24) 52 #define PERLCK_ENA_MASK (1 << 28) 53 #define PERLCK_MUX_SHIFT 29 54 #define PERLCK_MUX_MASK 0x07 55 56 57 struct periph_def { 58 struct clknode_init_def clkdef; 59 uint32_t base_reg; 60 uint32_t div_width; 61 uint32_t div_mask; 62 uint32_t div_f_width; 63 uint32_t div_f_mask; 64 uint32_t flags; 65 }; 66 67 struct pgate_def { 68 struct clknode_init_def clkdef; 69 uint32_t idx; 70 uint32_t flags; 71 }; 72 #define PLIST(x) static const char *x[] 73 74 #define GATE(_id, cname, plist, _idx) \ 75 { \ 76 .clkdef.id = TEGRA210_CLK_##_id, \ 77 .clkdef.name = cname, \ 78 .clkdef.parent_names = (const char *[]){plist}, \ 79 .clkdef.parent_cnt = 1, \ 80 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 81 .idx = _idx, \ 82 .flags = 0, \ 83 } 84 /* Sources for multiplexors. */ 85 PLIST(mux_N_N_c_N_p_N_a) = 86 {"bogus", NULL, "pllC_out0", NULL, 87 "pllP_out0", NULL, "pllA_out0", NULL}; 88 PLIST(mux_N_N_p_N_N_N_clkm) = 89 {NULL, NULL, "pllP_out0", NULL, 90 NULL, NULL, "clk_m", NULL}; 91 PLIST(mux_N_c_p_a1_c2_c3_clkm) = 92 {NULL, "pllC_out0", "pllP_out0", "pllA1_out0", 93 "pllC2_out0", "pllC3_out0", "clk_m", NULL}; 94 PLIST(mux_N_c_p_a1_c2_c3_clkm_c4) = 95 {NULL, "pllC_out0", "pllP_out0", "pllA1_out0", 96 "pllC2_out0", "pllC3_out0", "clk_m", "pllC4_out0"}; 97 PLIST(mux_N_c_p_clkm_N_c4_c4o1_c4o1) = 98 {NULL, "pllC_out0", "pllP_out0", "clk_m", 99 NULL, "pllC4_out0", "pllC4_out1", "pllC4_out1"}; 100 PLIST(mux_N_c_p_clkm_N_c4_c4o1_c4o2) = 101 {NULL, "pllC_out0", "pllP_out0", "clk_m", 102 NULL, "pllC4_out0", "pllC4_out1", "pllC4_out2"}; 103 104 PLIST(mux_N_c2_c_c3_p_N_a) = 105 {NULL, "pllC2_out0", "pllC_out0", "pllC3_out0", 106 "pllP_out0", NULL, "pllA_out0", NULL}; 107 PLIST(mux_N_c2_c_c3_p_clkm_a1_c4) = 108 {NULL, "pllC2_out0", "pllC_out0", "pllC3_out0", 109 "pllP_out0", "clk_m", "pllA1_out0", "pllC4_out0"}; 110 PLIST(mux_N_c2_c_c3_p_N_a1_clkm) = 111 {NULL, "pllC2_out0", "pllC_out0", "pllC3_out0", 112 "pllP_out0", NULL, "pllA1_out0", "clk_m"}; 113 114 PLIST(mux_a_N_audio_N_p_N_clkm) = 115 {"pllA_out0", NULL, "audio", NULL, 116 "pllP_out0", NULL, "clk_m"}; 117 PLIST(mux_a_N_audio0_N_p_N_clkm) = 118 {"pllA_out0", NULL, "audio0", NULL, 119 "pllP_out0", NULL, "clk_m"}; 120 PLIST(mux_a_N_audio1_N_p_N_clkm) = 121 {"pllA_out0", NULL, "audio1", NULL, 122 "pllP_out0", NULL, "clk_m"}; 123 PLIST(mux_a_N_audio2_N_p_N_clkm) = 124 {"pllA_out0", NULL, "audio2", NULL, 125 "pllP_out0", NULL, "clk_m"}; 126 PLIST(mux_a_N_audio3_N_p_N_clkm) = 127 {"pllA_out0", NULL, "audio3", NULL, 128 "pllP_out0", NULL, "clk_m"}; 129 PLIST(mux_a_N_audio4_N_p_N_clkm) = 130 {"pllA_out0", NULL, "audio4", NULL, 131 "pllP_out0", NULL, "clk_m"}; 132 PLIST(mux_a_audiod1_p_clkm) = 133 {"pllA_out0", "audiod1", "pllP_out0", "clk_m", 134 NULL, NULL, NULL, NULL}; 135 PLIST(mux_a_audiod2_p_clkm) = 136 {"pllA_out0", "audiod2", "pllP_out0", "clk_m", 137 NULL, NULL, NULL, NULL}; 138 PLIST(mux_a_audiod3_p_clkm) = 139 {"pllA_out0", "audiod3", "pllP_out0", "clk_m", 140 NULL, NULL, NULL, NULL}; 141 PLIST(mux_a_c4_c_c4o1_p_N_clkm_c4o2) = 142 {"pllA_out0", "pllC4_out0", "pllC_out0", "pllC4_out1", 143 "pllP_out0", NULL, "clk_m", "pllC4_out2"}; 144 145 PLIST(mux_a_clks_p_clkm_e) = 146 {"pllA_out0", "clk_s", "pllP_out0", "clk_m", 147 "pllE_out0"}; 148 PLIST(mux_c4o1_c2_c_c4_p_clkm_a_c4) = 149 {"pllC4_out1", "pllC2_out0", "pllC_out0", "pllC4_out0", 150 "pllP_out0", "clk_m","pllA_out0", "pllC4_out0", }; 151 152 PLIST(mux_m_c_p_clkm_mud_mbud_mb_pud) = 153 {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m", 154 "pllM_UD", "pllMB_UD", "pllMB_out0", "pllP_UD"}; 155 PLIST(mux_p_N_N_c4o2_c4o1_N_clkm_c4) = 156 {"pllP_out0", NULL, NULL, "pllC4_out2", 157 "pllC4_out1", NULL, "clk_m", "pllC4_out0"}; 158 PLIST(mux_p_N_c_c4_c4o1_c4o2_clkm) = 159 {"pllP_out0", NULL, "pllC_out0", "pllC4_out0", 160 "pllC4_out1", "pllC4_out2", "clk_m"}; 161 PLIST(mux_p_N_c_c4_N_c4o1_clkm_c4o2) = 162 {"pllP_out0", NULL, "pllC_out0", "pllC4_out0", 163 NULL, "pllC4_out1", "clk_m", "pllC4_out2"}; 164 PLIST(mux_p_N_d_N_N_d2_clkm) = 165 {"pllP_out0", NULL, "pllD_out0", NULL, 166 NULL, "pllD2_out0", "clk_m"}; 167 PLIST(mux_p_N_clkm_N_clks_N_E) = 168 {"pllP_out0", NULL, "clk_m", NULL, 169 NULL, "clk_s", NULL, "pllE_out0"}; 170 PLIST(mux_p_c_c2_N_c2_N_clkm) = 171 {"pllP_out0", "pllC_out0", "pllC2_out0", NULL, 172 "pllC2_out0", NULL, "clk_m", NULL}; 173 PLIST(mux_p_co1_c_N_c4o2_c4o1_clkm_c4) = 174 {"pllP_out0", "pllC_out1", "pllC_out0", NULL, 175 "pllC4_out2", "pllC4_out1" ,"clk_m", "pllC4_out0"}; 176 PLIST(mux_p_c2_c_c3_N_a1_clkm_c4) = 177 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 178 NULL, "pllA1_out0", "clk_m", "pllC4_out0"}; 179 PLIST(mux_p_c2_c_c3_N_N_clkm) = 180 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 181 NULL, NULL, "clk_m", NULL}; 182 PLIST(mux_p_c2_c_c3_m_e_clkm) = 183 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0", 184 "pllM_out0", "pllE_out0", "clk_m"}; 185 PLIST(mux_p_c2_c_c4_N_c4o1_clkm_c4o2) = 186 {"pllP_out0", "pllC2_out0", "pllC4_out0", 187 NULL, "pllC4_out1", "clk_m", "pllC4_out2"}; 188 PLIST(mux_p_c2_c_c4_a_c4o1_clkm_c4o2) = 189 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0", 190 "pllA_out0", "pllC4_out1", "clk_m", "pllC4_out2"}; 191 PLIST(mux_p_c2_c_c4o2_c4o1_clks_clkm_c4) = 192 {"pllP_out0", "pllC2_out0", "pllC4_out2", 193 "pllC4_out1", "clk_s", "clk_m", "pllC4_out0"}; 194 195 PLIST(mux_p_c2_c_c4_c4o1_clkm_c4o2) = 196 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0", 197 "pllC4_out1", "clk_m", "pllC4_out2"}; 198 PLIST(mux_p_c2_c_c4_clkm_c4o1_c4o2) = 199 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0", 200 "clk_m", "pllC4_out1", "pllC4_out2"}; 201 PLIST(mux_p_c2_c_c4_clks_c4o1_clkm_c4o2) = 202 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0", 203 "clk_s", "pllC4_out1", "clk_m", "pllC4_out2"}; 204 PLIST(mux_p_c2_c_c4_clkm_c4o1_clks_c4o2) = 205 {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0", 206 "clk_m", "pllC4_out1", "clk_s", "pllC4_out2"}; 207 PLIST(mux_p_c2_refe1_c3_m_a1_clkm_C4) = 208 {"pllP_out0", "pllC2_out0", "pllREFE_out1", "pllC3_out0", 209 "pllM_out0", "pllA1_out0", "clk_m", "pllC4_out0"}; 210 PLIST(mux_p_c4_c_c4o1_N_c4o2_clkm) = 211 {"pllP_out0", "pllC4_out0", "pllC_out0", "pllC4_out1", 212 NULL, "pllC4_out2", "clk_m", NULL}; 213 PLIST(mux_p_m_d_a_c_d2_clkm) = 214 {"pllP_out0", "pllM_out0", "pllD_out0", "pllA_out0", 215 "pllC_out0", "pllD2_out0", "clk_m"}; 216 PLIST(mux_p_po3_clkm_clks_a) = 217 {"pllP_out0", "pllP_out3", "clk_m", "clk_s", 218 "pllA_out0", NULL, NULL, NULL}; 219 220 PLIST(mux_po3_c_c2_clkm_p_c4_c4o1_c4o2) = 221 {"pllP_out3", "pllC_out0", "pllC2_out0", "clk_m", 222 "pllP_out0", "pllC4_out0", "pllC4_out1", "pllC4_out2"}; 223 224 PLIST(mux_clkm_p_N_N_N_refre) = 225 {"clk_m", "pllP_xusb", NULL, NULL, 226 NULL, "pllREFE_out0", NULL, NULL}; 227 PLIST(mux_clkm_N_u48_N_p_N_u480) = 228 {"clk_m", NULL, "pllU_48", NULL, 229 "pllP_out0", NULL, "pllU_480"}; 230 PLIST(mux_clkm_refe_clks_u480) = 231 {"clk_m", "pllREFE_out0", "clk_s", "pllU_480", 232 NULL, NULL, NULL, NULL}; 233 234 PLIST(mux_sep_audio) = 235 {"pllA_out0", "pllC4_out0", "pllC_out0", "pllC4_out0", 236 "pllP_out0", "pllC4_out0", "clk_m", NULL, 237 "spdif_in", "i2s1", "i2s2", "i2s3", 238 "i2s4", "i2s5", "pllA_out0", "ext_vimclk"}; 239 240 static uint32_t clk_enable_reg[] = { 241 CLK_OUT_ENB_L, 242 CLK_OUT_ENB_H, 243 CLK_OUT_ENB_U, 244 CLK_OUT_ENB_V, 245 CLK_OUT_ENB_W, 246 CLK_OUT_ENB_X, 247 CLK_OUT_ENB_Y, 248 }; 249 250 static uint32_t clk_reset_reg[] = { 251 RST_DEVICES_L, 252 RST_DEVICES_H, 253 RST_DEVICES_U, 254 RST_DEVICES_V, 255 RST_DEVICES_W, 256 RST_DEVICES_X, 257 RST_DEVICES_Y, 258 }; 259 260 #define L(n) ((0 * 32) + (n)) 261 #define H(n) ((1 * 32) + (n)) 262 #define U(n) ((2 * 32) + (n)) 263 #define V(n) ((3 * 32) + (n)) 264 #define W(n) ((4 * 32) + (n)) 265 #define X(n) ((5 * 32) + (n)) 266 #define Y(n) ((6 * 32) + (n)) 267 268 /* Clock IDs not yet defined in binding header file. */ 269 #define TEGRA210_CLK_STAT_MON H(5) 270 #define TEGRA210_CLK_IRAMA U(20) 271 #define TEGRA210_CLK_IRAMB U(21) 272 #define TEGRA210_CLK_IRAMC U(22) 273 #define TEGRA210_CLK_IRAMD U(23) 274 #define TEGRA210_CLK_CRAM2 U(24) 275 #define TEGRA210_CLK_M_DOUBLER U(26) 276 #define TEGRA210_CLK_DEVD2_OUT U(29) 277 #define TEGRA210_CLK_DEVD1_OUT U(30) 278 #define TEGRA210_CLK_CPUG V(0) 279 #define TEGRA210_CLK_ATOMICS V(16) 280 #define TEGRA210_CLK_PCIERX0 W(2) 281 #define TEGRA210_CLK_PCIERX1 W(3) 282 #define TEGRA210_CLK_PCIERX2 W(4) 283 #define TEGRA210_CLK_PCIERX3 W(5) 284 #define TEGRA210_CLK_PCIERX4 W(6) 285 #define TEGRA210_CLK_PCIERX5 W(7) 286 #define TEGRA210_CLK_PCIE2_IOBIST W(9) 287 #define TEGRA210_CLK_EMC_IOBIST W(10) 288 #define TEGRA210_CLK_SATA_IOBIST W(12) 289 #define TEGRA210_CLK_MIPI_IOBIST W(13) 290 #define TEGRA210_CLK_EMC_LATENCY W(29) 291 #define TEGRA210_CLK_MC1 W(30) 292 #define TEGRA210_CLK_ETR X(3) 293 #define TEGRA210_CLK_CAM_MCLK X(4) 294 #define TEGRA210_CLK_CAM_MCLK2 X(5) 295 #define TEGRA210_CLK_MC_CAPA X(7) 296 #define TEGRA210_CLK_MC_CBPA X(8) 297 #define TEGRA210_CLK_MC_CPU X(9) 298 #define TEGRA210_CLK_MC_BBC X(10) 299 #define TEGRA210_CLK_EMC_DLL X(14) 300 #define TEGRA210_CLK_UART_FST_MIPI_CAL X(17) 301 #define TEGRA210_CLK_HPLL_ADSP X(26) 302 #define TEGRA210_CLK_PLLP_ADSP X(27) 303 #define TEGRA210_CLK_PLLA_ADSP X(28) 304 #define TEGRA210_CLK_PLLG_REF X(29) 305 #define TEGRA210_CLK_AXIAP Y(4) 306 #define TEGRA210_CLK_MC_CDPA Y(8) 307 #define TEGRA210_CLK_MC_CCPA Y(9) 308 309 310 static struct pgate_def pgate_def[] = { 311 /* bank L -> 0-31 */ 312 GATE(ISPB, "ispb", "clk_m", L(3)), 313 GATE(RTC, "rtc", "clk_s", L(4)), 314 GATE(TIMER, "timer", "clk_m", L(5)), 315 GATE(UARTA, "uarta", "pc_uarta" , L(6)), 316 GATE(UARTB, "uartb", "pc_uartb", L(7)), 317 GATE(GPIO, "gpio", "clk_m", L(8)), 318 GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)), 319 GATE(SPDIF_OUT, "spdif_out", "pc_spdif_out", L(10)), 320 GATE(SPDIF_IN, "spdif_in", "pc_spdif_in", L(10)), 321 GATE(I2S1, "i2s2", "pc_i2s2", L(11)), 322 GATE(I2C1, "i2c1", "pc_i2c1", L(12)), 323 GATE(SDMMC1, "sdmmc1", "pc_sdmmc1", L(14)), 324 GATE(SDMMC4, "sdmmc4", "pc_sdmmc4", L(15)), 325 GATE(PWM, "pwm", "pc_pwm", L(17)), 326 GATE(I2S2, "i2s3", "pc_i2s3", L(18)), 327 GATE(VI, "vi", "pc_vi", L(20)), 328 GATE(USBD, "usbd", "clk_m", L(22)), 329 GATE(ISP, "isp", "pc_isp", L(23)), 330 GATE(DISP2, "disp2", "pc_disp2", L(26)), 331 GATE(DISP1, "disp1", "pc_disp1", L(27)), 332 GATE(HOST1X, "host1x", "pc_host1x", L(28)), 333 GATE(I2S0, "i2s1", "pc_i2s1", L(30)), 334 335 /* bank H -> 32-63 */ 336 GATE(MC, "mem", "clk_m", H(0)), 337 GATE(AHBDMA, "ahbdma", "clk_m", H(1)), 338 GATE(APBDMA, "apbdma", "clk_m", H(2)), 339 GATE(STAT_MON, "stat_mon", "clk_s", H(5)), 340 GATE(PMC, "pmc", "clk_s", H(6)), 341 GATE(FUSE, "fuse", "clk_m", H(7)), 342 GATE(KFUSE, "kfuse", "clk_m", H(8)), 343 GATE(SBC1, "spi1", "pc_spi1", H(9)), 344 GATE(SBC2, "spi2", "pc_spi2", H(12)), 345 GATE(SBC3, "spi3", "pc_spi3", H(14)), 346 GATE(I2C5, "i2c5", "pc_i2c5", H(15)), 347 GATE(DSIA, "dsia", "pllD_dsi_csi", H(16)), 348 GATE(CSI, "csi", "pllP_out3", H(20)), 349 GATE(I2C2, "i2c2", "pc_i2c2", H(22)), 350 GATE(UARTC, "uartc", "pc_uartc", H(23)), 351 GATE(MIPI_CAL, "mipi_cal", "clk_m", H(24)), 352 GATE(EMC, "emc", "pc_emc", H(25)), 353 GATE(USB2, "usb2", "clk_m", H(26)), 354 GATE(BSEV, "bsev", "clk_m", H(31)), 355 356 /* bank U -> 64-95 */ 357 GATE(UARTD, "uartd", "pc_uartd", U(1)), 358 GATE(I2C3, "i2c3", "pc_i2c3", U(3)), 359 GATE(SBC4, "spi4", "pc_spi4", U(4)), 360 GATE(SDMMC3, "sdmmc3", "pc_sdmmc3", U(5)), 361 GATE(PCIE, "pcie", "clk_m", U(6)), 362 GATE(AFI, "afi", "clk_m", U(8)), 363 GATE(CSITE, "csite", "pc_csite", U(9)), 364 GATE(SOC_THERM, "soc_therm", "pc_soc_therm", U(14)), 365 GATE(DTV, "dtv", "clk_m", U(15)), 366 GATE(I2CSLOW, "i2c_slow", "pc_i2c_slow", U(17)), 367 GATE(DSIB, "dsib", "pllD_dsi_csi", U(18)), 368 GATE(TSEC, "tsec", "pc_tsec", U(19)), 369 GATE(IRAMA, "irama", "clk_m", U(20)), 370 GATE(IRAMB, "iramb", "clk_m", U(21)), 371 GATE(IRAMC, "iramc", "clk_m", U(22)), 372 GATE(IRAMD, "iramd", "clk_m", U(23)), 373 GATE(CRAM2, "cram2", "clk_m", U(24)), 374 GATE(XUSB_HOST, "xusb_host", "pc_xusb_core_host", U(25)), 375 GATE(M_DOUBLER, "m_doubler", "clk_m", U(26)), 376 GATE(CSUS, "sus_out", "clk_m", U(28)), 377 GATE(DEVD2_OUT, "devd2_out", "clk_m", U(29)), 378 GATE(DEVD1_OUT, "devd1_out", "clk_m", U(30)), 379 GATE(XUSB_DEV, "xusb_core_dev", "pc_xusb_core_dev", U(31)), 380 381 /* bank V -> 96-127 */ 382 GATE(CPUG, "cpug", "clk_m", V(0)), 383 GATE(MSELECT, "mselect", "pc_mselect", V(3)), 384 GATE(TSENSOR, "tsensor", "pc_tsensor", V(4)), 385 GATE(I2S4, "i2s5", "pc_i2s5", V(5)), 386 GATE(I2S3, "i2s4", "pc_i2s4", V(6)), 387 GATE(I2C4, "i2c4", "pc_i2c4", V(7)), 388 GATE(D_AUDIO, "ahub", "pc_ahub", V(10)), 389 GATE(APB2APE, "apb2ape", "clk_m", V(11)), 390 GATE(HDA2CODEC_2X, "hda2codec_2x", "pc_hda2codec_2x", V(15)), 391 GATE(ATOMICS, "atomics", "clk_m", V(16)), 392 GATE(SPDIF_2X, "spdif_doubler", "clk_m", V(22)), 393 GATE(ACTMON, "actmon", "pc_actmon", V(23)), 394 GATE(EXTERN1, "extperiph1", "pc_extperiph1", V(24)), 395 GATE(EXTERN2, "extperiph2", "pc_extperiph2", V(25)), 396 GATE(EXTERN3, "extperiph3", "pc_extperiph3", V(26)), 397 GATE(SATA_OOB, "sata_oob", "pc_sata_oob", V(27)), 398 GATE(SATA, "sata", "pc_sata", V(28)), 399 GATE(HDA, "hda", "pc_hda", V(29)), 400 401 /* bank W -> 128-159*/ 402 GATE(HDA2HDMI, "hda2hdmi", "clk_m", W(0)), 403 /* GATE(SATA_COLD, "sata_cold", "clk_m", W(1)),*/ /* Reset only */ 404 GATE(PCIERX0, "pcierx0", "clk_m", W(2)), 405 GATE(PCIERX1, "pcierx1", "clk_m", W(3)), 406 GATE(PCIERX2, "pcierx2", "clk_m", W(4)), 407 GATE(PCIERX3, "pcierx3", "clk_m", W(5)), 408 GATE(PCIERX4, "pcierx4", "clk_m", W(6)), 409 GATE(PCIERX5, "pcierx5", "clk_m", W(7)), 410 GATE(CEC, "cec", "clk_m", W(8)), 411 GATE(PCIE2_IOBIST, "pcie2_iobist", "clk_m", W(9)), 412 GATE(EMC_IOBIST, "emc_iobist", "clk_m", W(10)), 413 GATE(SATA_IOBIST, "sata_iobist", "clk_m", W(12)), 414 GATE(MIPI_IOBIST, "mipi_iobist", "clk_m", W(13)), 415 GATE(XUSB_GATE, "xusb_gate", "clk_m", W(15)), 416 GATE(CILAB, "cilab", "pc_cilab", W(16)), 417 GATE(CILCD, "cilcd", "pc_cilcd", W(17)), 418 GATE(CILE, "cilef", "pc_cilef", W(18)), 419 GATE(DSIALP, "dsia_lp", "pc_dsia_lp", W(19)), 420 GATE(DSIBLP, "dsib_lp", "pc_dsib_lp", W(20)), 421 GATE(ENTROPY, "entropy", "pc_entropy", W(21)), 422 GATE(DFLL_REF, "dvfs_ref", "pc_dvfs_ref", W(27)), 423 GATE(DFLL_SOC, "dvfs_soc", "pc_dvfs_soc", W(27)), 424 GATE(XUSB_SS, "xusb_ss", "pc_xusb_ss", W(28)), 425 GATE(EMC_LATENCY, "emc_latency", "pc_emc_latency", W(29)), 426 GATE(MC1, "mc1", "clk_m", W(30)), 427 428 /* bank X -> 160-191*/ 429 /*GATE(SPARE, "spare", "clk_m", X(0)), */ 430 GATE(DMIC1, "dmic1", "clk_m", X(1)), 431 GATE(DMIC2, "dmic2", "clk_m", X(2)), 432 GATE(ETR, "etr", "clk_m", X(3)), 433 GATE(CAM_MCLK, "CAM_MCLK", "clk_m", X(4)), 434 GATE(CAM_MCLK2, "CAM_MCLK2", "clk_m", X(5)), 435 GATE(I2C6, "i2c6", "pc_i2c6", X(6)), 436 GATE(MC_CAPA, "mc_capa", "clk_m", X(7)), 437 GATE(MC_CBPA, "mc_cbpa", "clk_m", X(8)), 438 GATE(MC_CPU, "mc_cpu", "clk_m", X(9)), 439 GATE(MC_BBC, "mc_bbc", "clk_m", X(10)), 440 GATE(VIM2_CLK, "vim2_clk", "clk_m", X(11)), 441 GATE(MIPIBIF, "mipibif", "clk_m", X(13)), 442 GATE(EMC_DLL, "emc_dll", "pc_emc_dll", X(14)), 443 GATE(UART_FST_MIPI_CAL, "uart_fst_mipi_cal", "clk_m", X(17)), 444 GATE(VIC03, "vic", "pc_vic", X(18)), 445 GATE(DPAUX, "dpaux", "dpaux_div", X(21)), 446 GATE(SOR0, "sor0", "pc_sor0", X(22)), 447 GATE(SOR1, "sor1", "pc_sor1", X(23)), 448 GATE(GPU, "gpu", "osc_div_clk", X(24)), 449 GATE(DBGAPB, "dbgapb", "clk_m", X(25)), 450 GATE(HPLL_ADSP, "hpll_adsp", "clk_m", X(26)), 451 GATE(PLLP_ADSP, "pllp_adsp", "clk_m", X(27)), 452 GATE(PLLA_ADSP, "plla_adsp", "clk_m", X(28)), 453 GATE(PLLG_REF, "pllg_ref", "clk_m", X(29)), 454 455 /* bank Y -> 192-224*/ 456 /* GATE(SPARE1, "spare1", "clk_m", Y(0)), */ 457 GATE(SDMMC_LEGACY, "sdmmc_legacy_tm", "pc_sdmmc_legacy_tm", Y(1)), 458 GATE(NVDEC, "nvdec", "pc_nvdec", Y(2)), 459 GATE(NVJPG, "nvjpg", "clk_m", Y(3)), 460 GATE(AXIAP, "axiap", "clk_m", Y(4)), 461 GATE(DMIC3, "dmic3", "clk_m", Y(5)), 462 GATE(APE, "ape", "clk_m", Y(6)), 463 GATE(ADSP, "adsp", "clk_m", Y(7)), 464 GATE(MC_CDPA, "mc_cdpa", "clk_m", Y(8)), 465 GATE(MC_CCPA, "mc_ccpa", "clk_m", Y(9)), 466 GATE(MAUD, "mc_maud", "clk_m", Y(10)), 467 GATE(TSECB, "tsecb", "clk_m", Y(14)), 468 GATE(DPAUX1, "dpaux1", "dpaux1_div", Y(15)), 469 GATE(VI_I2C, "vi_i2c", "clk_m", Y(16)), 470 GATE(HSIC_TRK, "hsic_trk", "clk_m", Y(17)), 471 GATE(USB2_TRK, "usb2_trk", "clk_m", Y(18)), 472 GATE(QSPI, "qspi", "clk_m", Y(19)), 473 GATE(UARTAPE, "uarape", "clk_m", Y(20)), 474 GATE(ADSP_NEON, "adspneon", "clk_m", Y(26)), 475 GATE(NVENC, "nvenc", "clk_m", Y(27)), 476 GATE(IQC2, "iqc2", "clk_m", Y(28)), 477 GATE(IQC1, "iqc1", "clk_m", Y(29)), 478 GATE(SOR_SAFE, "sor_safe", "sor_safe_div", Y(30)), 479 GATE(PLL_P_OUT_CPU, "pllp_out_cpu", "clk_m", Y(31)), 480 }; 481 482 /* Peripheral clock clock */ 483 #define DCF_HAVE_MUX 0x0100 /* Block with multipexor */ 484 #define DCF_HAVE_ENA 0x0200 /* Block with enable bit */ 485 #define DCF_HAVE_DIV 0x0400 /* Block with divider */ 486 487 /* Mark block with additional bits / functionality. */ 488 #define DCF_IS_MASK 0x00FF 489 #define DCF_IS_UART 0x0001 490 #define DCF_IS_VI 0x0002 491 #define DCF_IS_HOST1X 0x0003 492 #define DCF_IS_XUSB_SS 0x0004 493 #define DCF_IS_EMC_DLL 0x0005 494 #define DCF_IS_SATA 0x0006 495 #define DCF_IS_VIC 0x0007 496 #define DCF_IS_AHUB 0x0008 497 #define DCF_IS_SOR0 0x0009 498 #define DCF_IS_EMC 0x000A 499 #define DCF_IS_QSPI 0x000B 500 #define DCF_IS_EMC_SAFE 0x000C 501 /* Basic pheripheral clock */ 502 #define PER_CLK(_id, cn, pl, r, diw, fiw, f) \ 503 { \ 504 .clkdef.id = _id, \ 505 .clkdef.name = cn, \ 506 .clkdef.parent_names = pl, \ 507 .clkdef.parent_cnt = nitems(pl), \ 508 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 509 .base_reg = r, \ 510 .div_width = diw, \ 511 .div_f_width = fiw, \ 512 .flags = f, \ 513 } 514 515 /* Mux with fractional 8.1 divider. */ 516 #define CLK_8_1(id, cn, pl, r, f) \ 517 PER_CLK(id, cn, pl, r, 8, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) 518 /* Mux with integer 8bits divider. */ 519 #define CLK_8_0(id, cn, pl, r, f) \ 520 PER_CLK(id, cn, pl, r, 8, 0, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) 521 522 /* Mux with fractional 16.1 divider. */ 523 #define CLK16_1(id, cn, pl, r, f) \ 524 PER_CLK(id, cn, pl, r, 16, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) 525 /* Mux with integer 16bits divider. */ 526 #define CLK16_0(id, cn, pl, r, f) \ 527 PER_CLK(id, cn, pl, r, 16, 0, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV) 528 /* Mux wihout divider. */ 529 #define CLK_0_0(id, cn, pl, r, f) \ 530 PER_CLK(id, cn, pl, r, 0, 0, (f) | DCF_HAVE_MUX) 531 532 static struct periph_def periph_def[] = { 533 CLK_8_1(0, "pc_i2s2", mux_a_N_audio1_N_p_N_clkm, CLK_SOURCE_I2S2, DCF_HAVE_ENA), 534 CLK_8_1(0, "pc_i2s3", mux_a_N_audio2_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA), 535 CLK_8_1(0, "pc_spdif_out", mux_a_N_audio_N_p_N_clkm, CLK_SOURCE_SPDIF_OUT, 0), 536 CLK_8_1(0, "pc_spdif_in", mux_p_c2_c_c4_clkm_c4o1_c4o2, CLK_SOURCE_SPDIF_IN, 0), 537 CLK_8_1(0, "pc_pwm", mux_p_c2_c_c4_clks_c4o1_clkm_c4o2, CLK_SOURCE_PWM, 0), 538 CLK_8_1(0, "pc_spi2", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SPI2, 0), 539 CLK_8_1(0, "pc_spi3", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SPI3, 0), 540 CLK16_0(0, "pc_i2c1", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C1, 0), 541 CLK16_0(0, "pc_i2c5", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C5, 0), 542 CLK_8_1(0, "pc_spi1", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SPI1, 0), 543 CLK_0_0(0, "pc_disp1", mux_p_N_d_N_N_d2_clkm, CLK_SOURCE_DISP1, 0), 544 CLK_0_0(0, "pc_disp2", mux_p_N_d_N_N_d2_clkm, CLK_SOURCE_DISP2, 0), 545 CLK_8_1(0, "pc_isp", mux_N_c_p_a1_c2_c3_clkm_c4, CLK_SOURCE_ISP, 0), 546 CLK_8_1(0, "pc_vi", mux_N_c2_c_c3_p_clkm_a1_c4, CLK_SOURCE_VI, DCF_IS_VI), 547 CLK_8_1(0, "pc_sdmmc1", mux_p_N_N_c4o2_c4o1_N_clkm_c4, CLK_SOURCE_SDMMC1, 0), 548 CLK_8_1(0, "pc_sdmmc2", mux_p_N_N_c4o2_c4o1_N_clkm_c4, CLK_SOURCE_SDMMC2, 0), 549 CLK_8_1(0, "pc_sdmmc4", mux_p_N_N_c4o2_c4o1_N_clkm_c4, CLK_SOURCE_SDMMC4, 0), 550 CLK16_1(0, "pc_uarta", mux_p_c2_c_c4_c4o1_clkm_c4o2, CLK_SOURCE_UARTA, DCF_IS_UART), 551 CLK16_1(0, "pc_uartb", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_UARTB, DCF_IS_UART), 552 CLK_8_1(0, "pc_host1x", mux_c4o1_c2_c_c4_p_clkm_a_c4, CLK_SOURCE_HOST1X, DCF_IS_HOST1X), 553 CLK16_0(0, "pc_i2c2", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C2, 0), 554 CLK_8_1(0, "pc_emc", mux_m_c_p_clkm_mud_mbud_mb_pud, CLK_SOURCE_EMC, DCF_IS_EMC), 555 CLK16_1(0, "pc_uartc", mux_p_c2_c_c4_c4o1_clkm_c4o2, CLK_SOURCE_UARTC, DCF_IS_UART), 556 CLK_8_1(0, "pc_vi_sensor", mux_N_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR, 0), 557 CLK_8_1(0, "pc_spi4", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SPI4, 0), 558 CLK16_0(0, "pc_i2c3", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C3, 0), 559 CLK_8_1(0, "pc_sdmmc3", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC3, 0), 560 CLK16_1(0, "pc_uartd", mux_p_c2_c_c4_c4o1_clkm_c4o2, CLK_SOURCE_UARTD, DCF_IS_UART), 561 CLK_8_1(0, "pc_csite", mux_p_c2_refe1_c3_m_a1_clkm_C4, CLK_SOURCE_CSITE, 0), 562 CLK_8_1(0, "pc_i2s1", mux_a_N_audio0_N_p_N_clkm, CLK_SOURCE_I2S1, 0), 563 /* DTV xxx */ 564 CLK_8_1(0, "pc_tsec", mux_p_c2_c_c3_N_a1_clkm_c4, CLK_SOURCE_TSEC, 0), 565 /* SPARE2 */ 566 CLK_8_1(0, "pc_mselect", mux_p_c2_c_c4o2_c4o1_clks_clkm_c4, CLK_SOURCE_MSELECT, 0), 567 CLK_8_1(0, "pc_tsensor", mux_p_c2_c_c4_clkm_c4o1_clks_c4o2, CLK_SOURCE_TSENSOR, 0), 568 CLK_8_1(0, "pc_i2s4", mux_a_N_audio3_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA), 569 CLK_8_1(0, "pc_i2s5", mux_a_N_audio4_N_p_N_clkm, CLK_SOURCE_I2S4, DCF_HAVE_ENA), 570 CLK16_0(0, "pc_i2c4", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C4, 0), 571 CLK_8_1(0, "pc_ahub", mux_sep_audio, CLK_SOURCE_AHUB, DCF_IS_AHUB), 572 CLK_8_1(0, "pc_hda2codec_2x", mux_p_c2_c_c4_a_c4o1_clkm_c4o2, CLK_SOURCE_HDA2CODEC_2X, 0), 573 CLK_8_1(0, "pc_actmon", mux_p_c2_c_c4_clks_c4o1_clkm_c4o2, CLK_SOURCE_ACTMON, 0), 574 CLK_8_1(0, "pc_extperiph1", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH1, 0), 575 CLK_8_1(0, "pc_extperiph2", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH2, 0), 576 CLK_8_1(0, "pc_extperiph3", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH3, 0), 577 CLK_8_1(0, "pc_i2c_slow", mux_p_c2_c_c4_clks_c4o1_clkm_c4o2, CLK_SOURCE_I2C_SLOW, 0), 578 /* SYS */ 579 CLK_8_1(0, "pc_ispb", mux_N_N_c_N_p_N_a, CLK_SOURCE_ISPB, 0), 580 CLK_8_1(0, "pc_sor1", mux_p_N_d_N_N_d2_clkm, CLK_SOURCE_SOR1, DCF_IS_SOR0), 581 CLK_8_1(0, "pc_sor0", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_SOR0, DCF_IS_SOR0), 582 CLK_8_1(0, "pc_sata_oob", mux_p_c4_c_c4o1_N_c4o2_clkm, CLK_SOURCE_SATA_OOB, 0), 583 CLK_8_1(0, "pc_sata", mux_p_N_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SATA, DCF_IS_SATA), 584 CLK_8_1(0, "pc_hda", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_HDA, 0), 585 CLK_8_1(TEGRA210_CLK_XUSB_HOST_SRC, 586 "pc_xusb_core_host", mux_clkm_p_N_N_N_refre, CLK_SOURCE_XUSB_CORE_HOST, 0), 587 CLK_8_1(TEGRA210_CLK_XUSB_FALCON_SRC, 588 "pc_xusb_falcon", mux_clkm_p_N_N_N_refre, CLK_SOURCE_XUSB_FALCON, 0), 589 CLK_8_1(TEGRA210_CLK_XUSB_FS_SRC, 590 "pc_xusb_fs", mux_clkm_N_u48_N_p_N_u480, CLK_SOURCE_XUSB_FS, 0), 591 CLK_8_1(TEGRA210_CLK_XUSB_DEV_SRC, 592 "pc_xusb_core_dev", mux_clkm_p_N_N_N_refre, CLK_SOURCE_XUSB_CORE_DEV, 0), 593 CLK_8_1(TEGRA210_CLK_XUSB_SS_SRC, 594 "pc_xusb_ss", mux_clkm_refe_clks_u480, CLK_SOURCE_XUSB_SS, DCF_IS_XUSB_SS), 595 CLK_8_1(0, "pc_cilab", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_CILAB, 0), 596 CLK_8_1(0, "pc_cilcd", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_CILCD, 0), 597 CLK_8_1(0, "pc_cilef", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_CILEF, 0), 598 CLK_8_1(0, "pc_dsia_lp", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_DSIA_LP, 0), 599 CLK_8_1(0, "pc_dsib_lp", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_DSIB_LP, 0), 600 CLK_8_1(0, "pc_entropy", mux_p_N_clkm_N_clks_N_E, CLK_SOURCE_ENTROPY, 0), 601 CLK_8_1(0, "pc_dvfs_ref", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_DVFS_REF, DCF_HAVE_ENA), 602 CLK_8_1(0, "pc_dvfs_soc", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_DVFS_SOC, DCF_HAVE_ENA), 603 CLK_8_1(0, "pc_emc_latency", mux_N_c_p_clkm_N_c4_c4o1_c4o2, CLK_SOURCE_EMC_LATENCY, 0), 604 CLK_8_1(0, "pc_soc_therm", mux_N_c_p_clkm_N_c4_c4o1_c4o1, CLK_SOURCE_SOC_THERM, 0), 605 CLK_8_1(0, "pc_dmic1", mux_a_audiod1_p_clkm, CLK_SOURCE_DMIC1, 0), 606 CLK_8_1(0, "pc_dmic2", mux_a_audiod2_p_clkm, CLK_SOURCE_DMIC2, 0), 607 CLK_8_1(0, "pc_vi_sensor2", mux_N_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR2, 0), 608 CLK16_0(0, "pc_i2c6", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C6, 0), 609 /* MIPIBIF */ 610 CLK_8_1(0, "pc_emc_dll", mux_m_c_p_clkm_mud_mbud_mb_pud, CLK_SOURCE_EMC_DLL, DCF_IS_EMC_DLL), 611 CLK_8_1(0, "pc_uart_fst_mipi_cal", mux_p_c_c2_N_c2_N_clkm, CLK_SOURCE_UART_FST_MIPI_CAL, 0), 612 CLK_8_1(0, "pc_vic", mux_N_c_p_a1_c2_c3_clkm, CLK_SOURCE_VIC, DCF_IS_VIC), 613 614 CLK_8_1(0, "pc_sdmmc_legacy_tm", mux_po3_c_c2_clkm_p_c4_c4o1_c4o2, CLK_SOURCE_SDMMC_LEGACY_TM, 0), 615 CLK_8_1(0, "pc_nvdec", mux_N_c2_c_c3_p_N_a1_clkm, CLK_SOURCE_NVDEC, 0), 616 CLK_8_1(0, "pc_nvjpg", mux_N_c2_c_c3_p_N_a1_clkm, CLK_SOURCE_NVJPG, 0), 617 CLK_8_1(0, "pc_nvenc", mux_N_c2_c_c3_p_N_a1_clkm, CLK_SOURCE_NVENC, 0), 618 CLK_8_1(0, "pc_dmic3", mux_a_audiod3_p_clkm, CLK_SOURCE_DMIC3, 0), 619 CLK_8_1(0, "pc_ape", mux_a_c4_c_c4o1_p_N_clkm_c4o2, CLK_SOURCE_APE, 0), 620 CLK_8_1(0, "pc_qspi", mux_p_co1_c_N_c4o2_c4o1_clkm_c4, CLK_SOURCE_QSPI, DCF_IS_QSPI), 621 CLK_8_1(0, "pc_vi_i2c", mux_p_c2_c_c3_N_N_clkm, CLK_SOURCE_VI_I2C, 0), 622 /* USB2_HSIC_TRK */ 623 CLK_8_0(0, "pc_maud", mux_p_po3_clkm_clks_a, CLK_SOURCE_MAUD, 0), 624 CLK_8_1(0, "pc_tsecb", mux_p_c2_c_c3_N_a1_clkm_c4, CLK_SOURCE_TSECB, 0), 625 CLK_8_1(0, "pc_uartape", mux_p_c2_c_c3_N_N_clkm, CLK_SOURCE_UARTAPE, 0), 626 CLK_8_1(0, "pc_dbgapb", mux_N_N_p_N_N_N_clkm, CLK_SOURCE_DBGAPB, 0), 627 CLK_8_1(0, "pc_emc_safe", mux_m_c_p_clkm_mud_mbud_mb_pud, CLK_SOURCE_EMC_SAFE, DCF_IS_EMC_SAFE), 628 }; 629 630 static int periph_init(struct clknode *clk, device_t dev); 631 static int periph_recalc(struct clknode *clk, uint64_t *freq); 632 static int periph_set_freq(struct clknode *clk, uint64_t fin, 633 uint64_t *fout, int flags, int *stop); 634 static int periph_set_mux(struct clknode *clk, int idx); 635 636 struct periph_sc { 637 device_t clkdev; 638 uint32_t base_reg; 639 uint32_t div_shift; 640 uint32_t div_width; 641 uint32_t div_mask; 642 uint32_t div_f_width; 643 uint32_t div_f_mask; 644 uint32_t flags; 645 646 uint32_t divider; 647 int mux; 648 }; 649 650 static clknode_method_t periph_methods[] = { 651 /* Device interface */ 652 CLKNODEMETHOD(clknode_init, periph_init), 653 CLKNODEMETHOD(clknode_recalc_freq, periph_recalc), 654 CLKNODEMETHOD(clknode_set_freq, periph_set_freq), 655 CLKNODEMETHOD(clknode_set_mux, periph_set_mux), 656 CLKNODEMETHOD_END 657 }; 658 DEFINE_CLASS_1(tegra210_periph, tegra210_periph_class, periph_methods, 659 sizeof(struct periph_sc), clknode_class); 660 661 static int 662 periph_init(struct clknode *clk, device_t dev) 663 { 664 struct periph_sc *sc; 665 uint32_t reg; 666 sc = clknode_get_softc(clk); 667 668 DEVICE_LOCK(sc); 669 if (sc->flags & DCF_HAVE_ENA) 670 MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK); 671 672 RD4(sc, sc->base_reg, ®); 673 DEVICE_UNLOCK(sc); 674 675 /* Stnadard mux. */ 676 if (sc->flags & DCF_HAVE_MUX) 677 sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK; 678 else 679 sc->mux = 0; 680 if (sc->flags & DCF_HAVE_DIV) 681 sc->divider = (reg & sc->div_mask) + 2; 682 else 683 sc->divider = 1; 684 if ((sc->flags & DCF_IS_MASK) == DCF_IS_UART) { 685 if (!(reg & PERLCK_UDIV_DIS)) 686 sc->divider = 2; 687 } 688 689 /* AUDIO MUX */ 690 if ((sc->flags & DCF_IS_MASK) == DCF_IS_AHUB) { 691 if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) { 692 sc->mux = 8 + 693 ((reg >> PERLCK_AMUX_SHIFT) & PERLCK_MUX_MASK); 694 } 695 } 696 clknode_init_parent_idx(clk, sc->mux); 697 return(0); 698 } 699 700 static int 701 periph_set_mux(struct clknode *clk, int idx) 702 { 703 struct periph_sc *sc; 704 uint32_t reg; 705 706 707 sc = clknode_get_softc(clk); 708 if (!(sc->flags & DCF_HAVE_MUX)) 709 return (ENXIO); 710 711 sc->mux = idx; 712 DEVICE_LOCK(sc); 713 RD4(sc, sc->base_reg, ®); 714 reg &= ~(PERLCK_MUX_MASK << PERLCK_MUX_SHIFT); 715 if ((sc->flags & DCF_IS_MASK) == DCF_IS_AHUB) { 716 reg &= ~PERLCK_AMUX_DIS; 717 reg &= ~(PERLCK_MUX_MASK << PERLCK_AMUX_SHIFT); 718 719 if (idx <= 7) { 720 reg |= idx << PERLCK_MUX_SHIFT; 721 } else { 722 reg |= 7 << PERLCK_MUX_SHIFT; 723 reg |= (idx - 8) << PERLCK_AMUX_SHIFT; 724 } 725 } else { 726 reg |= idx << PERLCK_MUX_SHIFT; 727 } 728 WR4(sc, sc->base_reg, reg); 729 DEVICE_UNLOCK(sc); 730 731 return(0); 732 } 733 734 static int 735 periph_recalc(struct clknode *clk, uint64_t *freq) 736 { 737 struct periph_sc *sc; 738 uint32_t reg; 739 740 sc = clknode_get_softc(clk); 741 742 if (sc->flags & DCF_HAVE_DIV) { 743 DEVICE_LOCK(sc); 744 RD4(sc, sc->base_reg, ®); 745 DEVICE_UNLOCK(sc); 746 *freq = (*freq << sc->div_f_width) / sc->divider; 747 } 748 return (0); 749 } 750 751 static int 752 periph_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, 753 int flags, int *stop) 754 { 755 struct periph_sc *sc; 756 uint64_t tmp, divider; 757 758 sc = clknode_get_softc(clk); 759 if (!(sc->flags & DCF_HAVE_DIV)) { 760 *stop = 0; 761 return (0); 762 } 763 764 tmp = fin << sc->div_f_width; 765 divider = tmp / *fout; 766 if ((tmp % *fout) != 0) 767 divider++; 768 769 if (divider < (1 << sc->div_f_width)) 770 divider = 1 << (sc->div_f_width - 1); 771 772 if (flags & CLK_SET_DRYRUN) { 773 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 774 (*fout != (tmp / divider))) 775 return (ERANGE); 776 } else { 777 DEVICE_LOCK(sc); 778 MD4(sc, sc->base_reg, sc->div_mask, 779 (divider - (1 << sc->div_f_width))); 780 DEVICE_UNLOCK(sc); 781 sc->divider = divider; 782 } 783 *fout = tmp / divider; 784 *stop = 1; 785 return (0); 786 } 787 788 static int 789 periph_register(struct clkdom *clkdom, struct periph_def *clkdef) 790 { 791 struct clknode *clk; 792 struct periph_sc *sc; 793 794 clk = clknode_create(clkdom, &tegra210_periph_class, &clkdef->clkdef); 795 if (clk == NULL) 796 return (1); 797 798 sc = clknode_get_softc(clk); 799 sc->clkdev = clknode_get_device(clk); 800 sc->base_reg = clkdef->base_reg; 801 sc->div_width = clkdef->div_width; 802 sc->div_mask = (1 <<clkdef->div_width) - 1; 803 sc->div_f_width = clkdef->div_f_width; 804 sc->div_f_mask = (1 <<clkdef->div_f_width) - 1; 805 sc->flags = clkdef->flags; 806 807 clknode_register(clkdom, clk); 808 return (0); 809 } 810 811 /* -------------------------------------------------------------------------- */ 812 static int pgate_init(struct clknode *clk, device_t dev); 813 static int pgate_set_gate(struct clknode *clk, bool enable); 814 static int pgate_get_gate(struct clknode *clk, bool *enabled); 815 816 struct pgate_sc { 817 device_t clkdev; 818 uint32_t idx; 819 uint32_t flags; 820 uint32_t enabled; 821 822 }; 823 824 static clknode_method_t pgate_methods[] = { 825 /* Device interface */ 826 CLKNODEMETHOD(clknode_init, pgate_init), 827 CLKNODEMETHOD(clknode_set_gate, pgate_set_gate), 828 CLKNODEMETHOD(clknode_get_gate, pgate_get_gate), 829 CLKNODEMETHOD_END 830 }; 831 DEFINE_CLASS_1(tegra210_pgate, tegra210_pgate_class, pgate_methods, 832 sizeof(struct pgate_sc), clknode_class); 833 834 static uint32_t 835 get_enable_reg(int idx) 836 { 837 KASSERT(idx / 32 < nitems(clk_enable_reg), 838 ("Invalid clock index for enable: %d", idx)); 839 return (clk_enable_reg[idx / 32]); 840 } 841 842 static uint32_t 843 get_reset_reg(int idx) 844 { 845 KASSERT(idx / 32 < nitems(clk_reset_reg), 846 ("Invalid clock index for reset: %d", idx)); 847 return (clk_reset_reg[idx / 32]); 848 } 849 850 static int 851 pgate_init(struct clknode *clk, device_t dev) 852 { 853 struct pgate_sc *sc; 854 uint32_t ena_reg, rst_reg, mask; 855 856 sc = clknode_get_softc(clk); 857 mask = 1 << (sc->idx % 32); 858 859 DEVICE_LOCK(sc); 860 RD4(sc, get_enable_reg(sc->idx), &ena_reg); 861 RD4(sc, get_reset_reg(sc->idx), &rst_reg); 862 DEVICE_UNLOCK(sc); 863 864 sc->enabled = ena_reg & mask ? 1 : 0; 865 clknode_init_parent_idx(clk, 0); 866 867 return(0); 868 } 869 870 static int 871 pgate_set_gate(struct clknode *clk, bool enable) 872 { 873 struct pgate_sc *sc; 874 uint32_t reg, mask, base_reg; 875 876 sc = clknode_get_softc(clk); 877 mask = 1 << (sc->idx % 32); 878 sc->enabled = enable; 879 base_reg = get_enable_reg(sc->idx); 880 881 DEVICE_LOCK(sc); 882 MD4(sc, base_reg, mask, enable ? mask : 0); 883 RD4(sc, base_reg, ®); 884 DEVICE_UNLOCK(sc); 885 886 DELAY(2); 887 return(0); 888 } 889 890 static int 891 pgate_get_gate(struct clknode *clk, bool *enabled) 892 { 893 struct pgate_sc *sc; 894 uint32_t reg, mask, base_reg; 895 896 sc = clknode_get_softc(clk); 897 mask = 1 << (sc->idx % 32); 898 base_reg = get_enable_reg(sc->idx); 899 900 DEVICE_LOCK(sc); 901 RD4(sc, base_reg, ®); 902 DEVICE_UNLOCK(sc); 903 *enabled = reg & mask ? true: false; 904 905 return(0); 906 } 907 908 int 909 tegra210_hwreset_by_idx(struct tegra210_car_softc *sc, intptr_t idx, bool reset) 910 { 911 uint32_t reg, mask, reset_reg; 912 913 CLKDEV_DEVICE_LOCK(sc->dev); 914 if (idx == TEGRA210_RST_DFLL_DVCO) { 915 CLKDEV_MODIFY_4(sc->dev, DFLL_BASE, DFLL_BASE_DVFS_DFLL_RESET, 916 reset ? DFLL_BASE_DVFS_DFLL_RESET : 0); 917 CLKDEV_READ_4(sc->dev, DFLL_BASE, ®); 918 } 919 if (idx == TEGRA210_RST_ADSP) { 920 reset_reg = (reset) ? RST_DEV_Y_SET: RST_DEV_Y_CLR; 921 mask = (0x1F << 22) |(1 << 7); 922 CLKDEV_WRITE_4(sc->dev, reset_reg, mask); 923 CLKDEV_READ_4(sc->dev, reset_reg, ®); 924 } else { 925 mask = 1 << (idx % 32); 926 reset_reg = get_reset_reg(idx); 927 928 CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0); 929 CLKDEV_READ_4(sc->dev, reset_reg, ®); 930 } 931 CLKDEV_DEVICE_UNLOCK(sc->dev); 932 933 return(0); 934 } 935 936 static int 937 pgate_register(struct clkdom *clkdom, struct pgate_def *clkdef) 938 { 939 struct clknode *clk; 940 struct pgate_sc *sc; 941 942 clk = clknode_create(clkdom, &tegra210_pgate_class, &clkdef->clkdef); 943 if (clk == NULL) 944 return (1); 945 946 sc = clknode_get_softc(clk); 947 sc->clkdev = clknode_get_device(clk); 948 sc->idx = clkdef->idx; 949 sc->flags = clkdef->flags; 950 951 clknode_register(clkdom, clk); 952 return (0); 953 } 954 955 void 956 tegra210_periph_clock(struct tegra210_car_softc *sc) 957 { 958 int i, rv; 959 960 for (i = 0; i < nitems(periph_def); i++) { 961 rv = periph_register(sc->clkdom, &periph_def[i]); 962 if (rv != 0) 963 panic("tegra210_periph_register failed"); 964 } 965 for (i = 0; i < nitems(pgate_def); i++) { 966 rv = pgate_register(sc->clkdom, &pgate_def[i]); 967 if (rv != 0) 968 panic("tegra210_pgate_register failed"); 969 } 970 971 }
Cache object: 21b04bae73c98c4e1f2f3ad4e48b90b0
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