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sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright 2020 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/malloc.h> 37 #include <sys/rman.h> 38 39 #include <machine/bus.h> 40 41 #include <dev/extres/clk/clk.h> 42 #include <dev/extres/hwreset/hwreset.h> 43 #include <dev/extres/phy/phy.h> 44 #include <dev/extres/regulator/regulator.h> 45 #include <dev/fdt/fdt_common.h> 46 #include <dev/fdt/fdt_pinctrl.h> 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <arm/nvidia/tegra_efuse.h> 52 53 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 54 55 #include "phynode_if.h" 56 57 /* FUSE calibration data. */ 58 #define FUSE_SKU_CALIB_0 0x0F0 59 #define FUSE_SKU_CALIB_0_HS_CURR_LEVEL_123(x, i) (((x) >> (11 + ((i) - 1) * 6)) & 0x3F); 60 #define FUSE_SKU_CALIB_0_HS_TERM_RANGE_ADJ(x) (((x) >> 7) & 0x0F); 61 #define FUSE_SKU_CALIB_0_HS_CURR_LEVEL_0(x) (((x) >> 0) & 0x3F); 62 63 #define FUSE_USB_CALIB_EXT_0 0x250 64 #define FUSE_USB_CALIB_EXT_0_RPD_CTRL(x) (((x) >> 0) & 0x1F); 65 66 67 /* Registers. */ 68 #define XUSB_PADCTL_USB2_PAD_MUX 0x004 69 70 #define XUSB_PADCTL_USB2_PORT_CAP 0x008 71 #define USB2_PORT_CAP_PORT_REVERSE_ID(p) (1 << (3 + (p) * 4)) 72 #define USB2_PORT_CAP_PORT_INTERNAL(p) (1 << (2 + (p) * 4)) 73 #define USB2_PORT_CAP_PORT_CAP(p, x) (((x) & 3) << ((p) * 4)) 74 #define USB2_PORT_CAP_PORT_CAP_OTG 0x3 75 #define USB2_PORT_CAP_PORT_CAP_DEVICE 0x2 76 #define USB2_PORT_CAP_PORT_CAP_HOST 0x1 77 #define USB2_PORT_CAP_PORT_CAP_DISABLED 0x0 78 79 #define XUSB_PADCTL_SS_PORT_MAP 0x014 80 #define SS_PORT_MAP_PORT_INTERNAL(p) (1 << (3 + (p) * 4)) 81 #define SS_PORT_MAP_PORT_MAP(p, x) (((x) & 7) << ((p) * 4)) 82 83 #define XUSB_PADCTL_ELPG_PROGRAM1 0x024 84 #define ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31) 85 #define ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30) 86 #define ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29) 87 #define ELPG_PROGRAM1_SSP_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3)) 88 #define ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN_EARLY(x) (1 << (1 + (x) * 3)) 89 #define ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN(x) (1 << (0 + (x) * 3)) 90 91 #define XUSB_PADCTL_USB3_PAD_MUX 0x028 92 #define USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) (1 << (8 + (x))) 93 #define USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x))) 94 95 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(x) (0x084 + (x) * 0x40) 96 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPU_OVRD_VAL (1 << 23) 97 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPU_OVRD ( 1 << 22) 98 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPD_OVRD_VAL (1 << 21) 99 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPD_OVRD (1 << 20) 100 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPU_OVRD_VAL (1 << 19) 101 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPU_OVRD (1 << 18) 102 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPD_OVRD_VAL (1 << 17) 103 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPD_OVRD (1 << 16) 104 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_DYN_DLY(x) (((x) & 0x3) << 9) 105 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(x) (((x) & 0x3) << 7) 106 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6) 107 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_DIV_DET_EN (1 << 4) 108 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_VOP_DIV2P7_DET (1 << 3) 109 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_VOP_DIV2P0_DET (1 << 2) 110 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_VON_DIV2P7_DET (1 << 1) 111 #define USB2_BATTERY_CHRG_OTGPAD_CTL1_VON_DIV2P0_DET (1 << 0) 112 113 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0(x) (0x088 + (x) * 0x40) 114 #define USB2_OTG_PAD_CTL0_PD_ZI (1 << 29) 115 #define USB2_OTG_PAD_CTL0_PD2_OVRD_EN (1 << 28) 116 #define USB2_OTG_PAD_CTL0_PD2 (1 << 27) 117 #define USB2_OTG_PAD_CTL0_PD (1 << 26) 118 #define USB2_OTG_PAD_CTL0_TERM_EN (1 << 25) 119 #define USB2_OTG_PAD_CTL0_LS_FSLEW(x) (((x) & 0x0F) << 21) 120 #define USB2_OTG_PAD_CTL0_LS_RSLEW(x) (((x) & 0x0F) << 17) 121 #define USB2_OTG_PAD_CTL0_FS_FSLEW(x) (((x) & 0x0F) << 13) 122 #define USB2_OTG_PAD_CTL0_FS_RSLEW(x) (((x) & 0x0F) << 9) 123 #define USB2_OTG_PAD_CTL0_HS_SLEW(x) (((x) & 0x3F) << 6) 124 #define USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(x) (((x) & 0x3F) << 0) 125 126 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1(x) (0x08C + (x) * 0x40) 127 #define USB2_OTG_PAD_CTL1_RPD_CTRL(x) (((x) & 0x1F) << 26) 128 #define USB2_OTG_PAD_CTL1_RPU_STATUS_HIGH (1 << 25) 129 #define USB2_OTG_PAD_CTL1_RPU_SWITCH_LOW (1 << 24) 130 #define USB2_OTG_PAD_CTL1_RPU_SWITCH_OVRD (1 << 23) 131 #define USB2_OTG_PAD_CTL1_HS_LOOPBACK_OVRD_VAL (1 << 22) 132 #define USB2_OTG_PAD_CTL1_HS_LOOPBACK_OVRD_EN (1 << 21) 133 #define USB2_OTG_PAD_CTL1_PTERM_RANGE_ADJ(x) (((x) & 0x0F) << 17) 134 #define USB2_OTG_PAD_CTL1_PD_DISC_OVRD_VAL (1 << 16) 135 #define USB2_OTG_PAD_CTL1_PD_CHRP_OVRD_VAL (1 << 15) 136 #define USB2_OTG_PAD_CTL1_RPU_RANGE_ADJ(x) (((x) & 0x03) << 13) 137 #define USB2_OTG_PAD_CTL1_HS_COUP_EN(x) (((x) & 0x03) << 11) 138 #define USB2_OTG_PAD_CTL1_SPARE(x) (((x) & 0x0F) << 7) 139 #define USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(x) (((x) & 0x0F) << 3) 140 #define USB2_OTG_PAD_CTL1_PD_DR (1 << 2) 141 #define USB2_OTG_PAD_CTL1_PD_DISC_OVRD (1 << 1) 142 #define USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0) 143 144 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0(x) (0x0C0 + (x) * 0x40) 145 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x0284 146 #define USB2_BIAS_PAD_CTL0_TRK_PWR_ENA (1 << 29) 147 #define USB2_BIAS_PAD_CTL0_SPARE(x) (((x) & 0xF) << 25) 148 #define USB2_BIAS_PAD_CTL0_CHG_DIV(x) (((x) & 0xF) << 21) 149 #define USB2_BIAS_PAD_CTL0_TEMP_COEF(x) (((x) & 0x7) << 18) 150 #define USB2_BIAS_PAD_CTL0_VREF_CTRL(x) (((x) & 0x7) << 15) 151 #define USB2_BIAS_PAD_CTL0_ADJRPU(x) (((x) & 0x7) << 12) 152 #define USB2_BIAS_PAD_CTL0_PD (1 << 11) 153 #define USB2_BIAS_PAD_CTL0_TERM_OFFSETL(x) (((x) & 0x7) << 8) 154 #define USB2_BIAS_PAD_CTL0_HS_CHIRP_LEVEL(x) (((x) & 0x3) << 6) 155 #define USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(x) (((x) & 0x7) << 3) 156 #define USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0) 157 158 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x0288 159 #define USB2_BIAS_PAD_CTL1_FORCE_TRK_CLK_EN (1 << 30) 160 #define USB2_BIAS_PAD_CTL1_TRK_SW_OVRD (1 << 29) 161 #define USB2_BIAS_PAD_CTL1_TRK_DONE (1 << 28) 162 #define USB2_BIAS_PAD_CTL1_TRK_START (1 << 27) 163 #define USB2_BIAS_PAD_CTL1_PD_TRK (1 << 26) 164 #define USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(x) (((x) & 0x7F) << 19) 165 #define USB2_BIAS_PAD_CTL1_TRK_START_TIMER(x) (((x) & 0x7F) << 12) 166 #define USB2_BIAS_PAD_CTL1_PCTRL(x) (((x) & 0x3F) << 6) 167 #define USB2_BIAS_PAD_CTL1_TCTRL(x) (((x) & 0x3F) << 0) 168 169 #define XUSB_PADCTL_HSIC_PAD_CTL0(x) (0x300 + (x) * 0x20) 170 #define HSIC_PAD_CTL0_RPU_STROBE (1 << 18) 171 #define HSIC_PAD_CTL0_RPU_DATA1 (1 << 17) 172 #define HSIC_PAD_CTL0_RPU_DATA0 (1 << 16) 173 #define HSIC_PAD_CTL0_RPD_STROBE (1 << 15) 174 #define HSIC_PAD_CTL0_RPD_DATA1 (1 << 14) 175 #define HSIC_PAD_CTL0_RPD_DATA0 (1 << 13) 176 #define HSIC_PAD_CTL0_LPBK_STROBE (1 << 12) 177 #define HSIC_PAD_CTL0_LPBK_DATA1 (1 << 11) 178 #define HSIC_PAD_CTL0_LPBK_DATA0 (1 << 10) 179 #define HSIC_PAD_CTL0_PD_ZI_STROBE (1 << 9) 180 #define HSIC_PAD_CTL0_PD_ZI_DATA1 (1 << 8) 181 #define HSIC_PAD_CTL0_PD_ZI_DATA0 (1 << 7) 182 #define HSIC_PAD_CTL0_PD_RX_STROBE (1 << 6) 183 #define HSIC_PAD_CTL0_PD_RX_DATA1 (1 << 5) 184 #define HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4) 185 #define HSIC_PAD_CTL0_PD_TX_STROBE (1 << 3) 186 #define HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2) 187 #define HSIC_PAD_CTL0_PD_TX_DATA0 (1 << 1) 188 #define HSIC_PAD_CTL0_IDDQ (1 << 0) 189 190 #define XUSB_PADCTL_HSIC_PAD_CTL1(x) (0x304 + (x) * 0x20) 191 #define HSIC_PAD_CTL1_RTERM(x) (((x) & 0xF) << 12) 192 #define HSIC_PAD_CTL1_HSIC_OPT(x) (((x) & 0xF) << 8) 193 #define HSIC_PAD_CTL1_TX_SLEW(x) (((x) & 0xF) << 4) 194 #define HSIC_PAD_CTL1_TX_RTUNEP(x) (((x) & 0xF) << 0) 195 196 #define XUSB_PADCTL_HSIC_PAD_CTL2(x) (0x308 + (x) * 0x20) 197 #define HSIC_PAD_CTL2_RX_STROBE_TRIM(x) (((x) & 0xF) << 8) 198 #define HSIC_PAD_CTL2_RX_DATA1_TRIM(x) (((x) & 0xF) << 4) 199 #define HSIC_PAD_CTL2_RX_DATA0_TRIM(x) (((x) & 0xF) << 0) 200 201 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL 0x340 202 #define HSIC_PAD_TRK_CTL_AUTO_RTERM_EN (1 << 24) 203 #define HSIC_PAD_TRK_CTL_FORCE_TRK_CLK_EN (1 << 23) 204 #define HSIC_PAD_TRK_CTL_TRK_SW_OVRD (1 << 22) 205 #define HSIC_PAD_TRK_CTL_TRK_DONE (1 << 21) 206 #define HSIC_PAD_TRK_CTL_TRK_START (1 << 20) 207 #define HSIC_PAD_TRK_CTL_PD_TRK (1 << 19) 208 #define HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(x) (((x) & 0x3F) << 12) 209 #define HSIC_PAD_TRK_CTL_TRK_START_TIMER(x) (((x) & 0x7F) << 5) 210 #define HSIC_PAD_TRK_CTL_RTERM_OUT(x) (((x) & 0x1F) << 0) 211 212 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x344 213 214 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360 215 #define UPHY_PLL_P0_CTL1_PLL0_FREQ_PSDIV(x) (((x) & 0x03) << 28) 216 #define UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(x) (((x) & 0xFF) << 20) 217 #define UPHY_PLL_P0_CTL1_PLL0_FREQ_MDIV(x) (((x) & 0x03) << 16) 218 #define UPHY_PLL_P0_CTL1_PLL0_LOCKDET_STATUS (1 << 15) 219 #define UPHY_PLL_P0_CTL1_PLL0_MODE_GET(x) (((x) >> 8) & 0x03) 220 #define UPHY_PLL_P0_CTL1_PLL0_BYPASS_EN (1 << 7) 221 #define UPHY_PLL_P0_CTL1_PLL0_FREERUN_EN (1 << 6) 222 #define UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD (1 << 4) 223 #define UPHY_PLL_P0_CTL1_PLL0_ENABLE (1 << 3) 224 #define UPHY_PLL_P0_CTL1_PLL0_SLEEP(x) (((x) & 0x03) << 1) 225 #define UPHY_PLL_P0_CTL1_PLL0_IDDQ (1 << 0) 226 227 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364 228 #define UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(x) (((x) & 0xFFFFFF) << 4) 229 #define UPHY_PLL_P0_CTL2_PLL0_CAL_RESET (1 << 3) 230 #define UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD (1 << 2) 231 #define UPHY_PLL_P0_CTL2_PLL0_CAL_DONE (1 << 1) 232 #define UPHY_PLL_P0_CTL2_PLL0_CAL_EN (1 << 0) 233 234 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c 235 #define UPHY_PLL_P0_CTL4_PLL0_TCLKOUT_EN (1 << 28) 236 #define UPHY_PLL_P0_CTL4_PLL0_CLKDIST_CTRL(x) (((x) & 0xF) << 20) 237 #define UPHY_PLL_P0_CTL4_PLL0_XDIGCLK_EN (1 << 19) 238 #define UPHY_PLL_P0_CTL4_PLL0_XDIGCLK_SEL(x) (((x) & 0x7) << 16) 239 #define UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_EN (1 << 15) 240 #define UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(x) (((x) & 0x3) << 12) 241 #define UPHY_PLL_P0_CTL4_PLL0_FBCLKBUF_EN (1 << 9) 242 #define UPHY_PLL_P0_CTL4_PLL0_REFCLKBUF_EN (1 << 8) 243 #define UPHY_PLL_P0_CTL4_PLL0_REFCLK_SEL(x) (((x) & 0xF) << 4) 244 #define UPHY_PLL_P0_CTL4_PLL0_REFCLK_TERM100 (1 << 0) 245 246 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370 247 #define UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(x) (((x) & 0xFF) << 16) 248 #define UPHY_PLL_P0_CTL5_PLL0_LPF_CTRL(x) (((x) & 0xFF) << 8) 249 #define UPHY_PLL_P0_CTL5_PLL0_CP_CTRL(x) (((x) & 0x0F) << 4) 250 #define UPHY_PLL_P0_CTL5_PLL0_PFD_CTRL(x) (((x) & 0x03) << 0) 251 252 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c 253 #define UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE (1U << 31) 254 #define UPHY_PLL_P0_CTL8_PLL0_RCAL_VAL(x) (((x) & 0x1F) << 24) 255 #define UPHY_PLL_P0_CTL8_PLL0_RCAL_BYP_EN (1 << 23) 256 #define UPHY_PLL_P0_CTL8_PLL0_RCAL_BYP_CODE(x) (((x) & 0x1F) << 16) 257 #define UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD (1 << 15) 258 #define UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN (1 << 13) 259 #define UPHY_PLL_P0_CTL8_PLL0_RCAL_EN (1 << 12) 260 #define UPHY_PLL_P0_CTL8_PLL0_BGAP_CTRL(x) (((x) & 0xFFF) << 0) 261 262 #define XUSB_PADCTL_UPHY_MISC_PAD_P_CTL1(x) (0x460 + (x) * 0x40) 263 #define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860 264 #define UPHY_PLL_S0_CTL1_PLL0_FREQ_PSDIV(x) (((x) & 0x03) << 28) 265 #define UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(x) (((x) & 0xFF) << 20) 266 #define UPHY_PLL_S0_CTL1_PLL0_FREQ_MDIV(x) (((x) & 0x03) << 16) 267 #define UPHY_PLL_S0_CTL1_PLL0_LOCKDET_STATUS (1 << 15) 268 #define UPHY_PLL_S0_CTL1_PLL0_MODE_GET(x) (((x) >> 8) & 0x03) 269 #define UPHY_PLL_S0_CTL1_PLL0_BYPASS_EN (1 << 7) 270 #define UPHY_PLL_S0_CTL1_PLL0_FREERUN_EN (1 << 6) 271 #define UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD (1 << 4) 272 #define UPHY_PLL_S0_CTL1_PLL0_ENABLE (1 << 3) 273 #define UPHY_PLL_S0_CTL1_PLL0_SLEEP(x) (((x) & 0x03) << 1) 274 #define UPHY_PLL_S0_CTL1_PLL0_IDDQ (1 << 0) 275 276 #define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864 277 #define UPHY_PLL_S0_CTL2_PLL0_CAL_CTRL(x) (((x) & 0xFFFFFF) << 4) 278 #define UPHY_PLL_S0_CTL2_PLL0_CAL_RESET (1 << 3) 279 #define UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD (1 << 2) 280 #define UPHY_PLL_S0_CTL2_PLL0_CAL_DONE (1 << 1) 281 #define UPHY_PLL_S0_CTL2_PLL0_CAL_EN (1 << 0) 282 283 #define XUSB_PADCTL_UPHY_PLL_S0_CTL4 0x86c 284 #define UPHY_PLL_S0_CTL4_PLL0_TCLKOUT_EN (1 << 28) 285 #define UPHY_PLL_S0_CTL4_PLL0_CLKDIST_CTRL(x) (((x) & 0xF) << 20) 286 #define UPHY_PLL_S0_CTL4_PLL0_XDIGCLK_EN (1 << 19) 287 #define UPHY_PLL_S0_CTL4_PLL0_XDIGCLK_SEL(x) (((x) & 0x7) << 16) 288 #define UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_EN (1 << 15) 289 #define UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(x) (((x) & 0x3) << 12) 290 #define UPHY_PLL_S0_CTL4_PLL0_FBCLKBUF_EN (1 << 9) 291 #define UPHY_PLL_S0_CTL4_PLL0_REFCLKBUF_EN (1 << 8) 292 #define UPHY_PLL_S0_CTL4_PLL0_REFCLK_SEL(x) (((x) & 0xF) << 4) 293 #define UPHY_PLL_S0_CTL4_PLL0_REFCLK_TERM100 (1 << 0) 294 295 #define XUSB_PADCTL_UPHY_PLL_S0_CTL5 0x870 296 #define UPHY_PLL_S0_CTL5_PLL0_DCO_CTRL(x) (((x) & 0xFF) << 16) 297 #define UPHY_PLL_S0_CTL5_PLL0_LPF_CTRL(x) (((x) & 0xFF) << 8) 298 #define UPHY_PLL_S0_CTL5_PLL0_CP_CTRL(x) (((x) & 0x0F) << 4) 299 #define UPHY_PLL_S0_CTL5_PLL0_PFD_CTRL(x) (((x) & 0x03) << 0) 300 301 #define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c 302 #define UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE (1U << 31) 303 #define UPHY_PLL_S0_CTL8_PLL0_RCAL_VAL(x) (((x) & 0x1F) << 24) 304 #define UPHY_PLL_S0_CTL8_PLL0_RCAL_BYP_EN (1 << 23) 305 #define UPHY_PLL_S0_CTL8_PLL0_RCAL_BYP_CODE(x) (((x) & 0x1F) << 16) 306 #define UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD (1 << 15) 307 #define UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN (1 << 13) 308 #define UPHY_PLL_S0_CTL8_PLL0_RCAL_EN (1 << 12) 309 #define UPHY_PLL_S0_CTL8_PLL0_BGAP_CTRL(x) (((x) & 0xFFF) << 0) 310 311 #define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960 312 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(x) (0xa60 + (x) * 0x40) 313 #define UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(x) (((x) & 0x3) << 16) 314 315 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(x) (0xa64 + (x) * 0x40) 316 #define UPHY_USB3_PAD_ECTL2_RX_IQ_CTRL(x) (((x) & 0x000F) << 16) 317 #define UPHY_USB3_PAD_ECTL2_RX_CTLE(x) (((x) & 0xFFFF) << 0) 318 319 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3(x) (0xa68 + (x) * 0x40) 320 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(x) (0xa6c + (x) * 0x40) 321 #define UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(x) (((x) & 0xFFFF) << 16) 322 #define UPHY_USB3_PAD_ECTL4_RX_PI_CTRL(x) (((x) & 0x00FF) << 0) 323 324 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6(x) (0xa74 + (x) * 0x40) 325 326 327 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 328 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 329 330 331 struct padctl_softc { 332 device_t dev; 333 struct resource *mem_res; 334 hwreset_t rst; 335 int phy_ena_cnt; 336 int pcie_ena_cnt; 337 int sata_ena_cnt; 338 339 /* Fuses calibration data */ 340 /* USB2 */ 341 uint32_t hs_curr_level[4]; 342 uint32_t hs_curr_level_offs; /* Not inited yet, always 0 */ 343 uint32_t hs_term_range_adj; 344 uint32_t rpd_ctrl; 345 346 /* HSIC */ 347 uint32_t rx_strobe_trim; /* Not inited yet, always 0 */ 348 uint32_t rx_data0_trim; /* Not inited yet, always 0 */ 349 uint32_t rx_data1_trim; /* Not inited yet, always 0 */ 350 uint32_t tx_rtune_p; /* Not inited yet, always 0 */ 351 uint32_t strobe_trim; /* Not inited yet, always 0 */ 352 }; 353 354 static struct ofw_compat_data compat_data[] = { 355 {"nvidia,tegra210-xusb-padctl", 1}, 356 {NULL, 0}, 357 }; 358 359 /* Ports. */ 360 enum padctl_port_type { 361 PADCTL_PORT_USB2, 362 PADCTL_PORT_HSIC, 363 PADCTL_PORT_USB3, 364 }; 365 366 struct padctl_lane; 367 struct padctl_port { 368 enum padctl_port_type type; 369 const char *name; 370 const char *base_name; 371 int idx; 372 int (*init)(struct padctl_softc *sc, 373 struct padctl_port *port); 374 375 /* Runtime data. */ 376 phandle_t xref; 377 bool enabled; 378 bool internal; 379 uint32_t companion; 380 regulator_t supply_vbus; 381 struct padctl_lane *lane; 382 }; 383 384 static int usb3_port_init(struct padctl_softc *sc, struct padctl_port *port); 385 386 #define PORT(t, n, p, i) { \ 387 .type = t, \ 388 .name = n "-" #p, \ 389 .base_name = n, \ 390 .idx = p, \ 391 .init = i, \ 392 } 393 static struct padctl_port ports_tbl[] = { 394 PORT(PADCTL_PORT_USB2, "usb2", 0, NULL), 395 PORT(PADCTL_PORT_USB2, "usb2", 1, NULL), 396 PORT(PADCTL_PORT_USB2, "usb2", 2, NULL), 397 PORT(PADCTL_PORT_USB2, "usb2", 3, NULL), 398 PORT(PADCTL_PORT_HSIC, "hsic", 0, NULL), 399 PORT(PADCTL_PORT_HSIC, "hsic", 1, NULL), 400 PORT(PADCTL_PORT_USB3, "usb3", 0, usb3_port_init), 401 PORT(PADCTL_PORT_USB3, "usb3", 1, usb3_port_init), 402 }; 403 404 /* Pads - a group of lannes. */ 405 enum padctl_pad_type { 406 PADCTL_PAD_USB2, 407 PADCTL_PAD_HSIC, 408 PADCTL_PAD_PCIE, 409 PADCTL_PAD_SATA, 410 }; 411 412 struct padctl_lane; 413 struct padctl_pad { 414 const char *name; 415 enum padctl_pad_type type; 416 const char *clock_name; 417 char *reset_name; /* XXX constify !!!!!! */ 418 int (*enable)(struct padctl_softc *sc, 419 struct padctl_lane *lane); 420 int (*disable)(struct padctl_softc *sc, 421 struct padctl_lane *lane); 422 /* Runtime data. */ 423 bool enabled; 424 clk_t clk; 425 hwreset_t reset; 426 int nlanes; 427 struct padctl_lane *lanes[8]; /* Safe maximum value. */ 428 }; 429 430 static int usb2_enable(struct padctl_softc *sc, struct padctl_lane *lane); 431 static int usb2_disable(struct padctl_softc *sc, struct padctl_lane *lane); 432 static int hsic_enable(struct padctl_softc *sc, struct padctl_lane *lane); 433 static int hsic_disable(struct padctl_softc *sc, struct padctl_lane *lane); 434 static int pcie_enable(struct padctl_softc *sc, struct padctl_lane *lane); 435 static int pcie_disable(struct padctl_softc *sc, struct padctl_lane *lane); 436 static int sata_enable(struct padctl_softc *sc, struct padctl_lane *lane); 437 static int sata_disable(struct padctl_softc *sc, struct padctl_lane *lane); 438 439 #define PAD(n, t, cn, rn, e, d) { \ 440 .name = n, \ 441 .type = t, \ 442 .clock_name = cn, \ 443 .reset_name = rn, \ 444 .enable = e, \ 445 .disable = d, \ 446 } 447 static struct padctl_pad pads_tbl[] = { 448 PAD("usb2", PADCTL_PAD_USB2, "trk", NULL, usb2_enable, usb2_disable), 449 PAD("hsic", PADCTL_PAD_HSIC, "trk", NULL, hsic_enable, hsic_disable), 450 PAD("pcie", PADCTL_PAD_PCIE, "pll", "phy", pcie_enable, pcie_disable), 451 PAD("sata", PADCTL_PAD_SATA, "pll", "phy", sata_enable, sata_disable), 452 }; 453 454 /* Lanes. */ 455 static char *usb_mux[] = {"snps", "xusb", "uart", "rsvd"}; 456 static char *hsic_mux[] = {"snps", "xusb"}; 457 static char *pci_mux[] = {"pcie-x1", "usb3-ss", "sata", "pcie-x4"}; 458 459 struct padctl_lane { 460 const char *name; 461 int idx; 462 bus_size_t reg; 463 uint32_t shift; 464 uint32_t mask; 465 char **mux; 466 int nmux; 467 /* Runtime data. */ 468 bool enabled; 469 phandle_t xref; 470 struct padctl_pad *pad; 471 struct padctl_port *port; 472 int mux_idx; 473 474 }; 475 476 #define LANE(n, p, r, s, m, mx) { \ 477 .name = n "-" #p, \ 478 .idx = p, \ 479 .reg = r, \ 480 .shift = s, \ 481 .mask = m, \ 482 .mux = mx, \ 483 .nmux = nitems(mx), \ 484 } 485 static struct padctl_lane lanes_tbl[] = { 486 LANE("usb2", 0, XUSB_PADCTL_USB2_PAD_MUX, 0, 0x3, usb_mux), 487 LANE("usb2", 1, XUSB_PADCTL_USB2_PAD_MUX, 2, 0x3, usb_mux), 488 LANE("usb2", 2, XUSB_PADCTL_USB2_PAD_MUX, 4, 0x3, usb_mux), 489 LANE("usb2", 3, XUSB_PADCTL_USB2_PAD_MUX, 6, 0x3, usb_mux), 490 LANE("hsic", 0, XUSB_PADCTL_USB2_PAD_MUX, 14, 0x1, hsic_mux), 491 LANE("hsic", 1, XUSB_PADCTL_USB2_PAD_MUX, 15, 0x1, hsic_mux), 492 LANE("pcie", 0, XUSB_PADCTL_USB3_PAD_MUX, 12, 0x3, pci_mux), 493 LANE("pcie", 1, XUSB_PADCTL_USB3_PAD_MUX, 14, 0x3, pci_mux), 494 LANE("pcie", 2, XUSB_PADCTL_USB3_PAD_MUX, 16, 0x3, pci_mux), 495 LANE("pcie", 3, XUSB_PADCTL_USB3_PAD_MUX, 18, 0x3, pci_mux), 496 LANE("pcie", 4, XUSB_PADCTL_USB3_PAD_MUX, 20, 0x3, pci_mux), 497 LANE("pcie", 5, XUSB_PADCTL_USB3_PAD_MUX, 22, 0x3, pci_mux), 498 LANE("pcie", 6, XUSB_PADCTL_USB3_PAD_MUX, 24, 0x3, pci_mux), 499 LANE("sata", 0, XUSB_PADCTL_USB3_PAD_MUX, 30, 0x3, pci_mux), 500 }; 501 502 /* Define all possible mappings for USB3 port lanes */ 503 struct padctl_lane_map { 504 int port_idx; 505 enum padctl_pad_type pad_type; 506 int lane_idx; 507 }; 508 509 #define LANE_MAP(pi, pt, li) { \ 510 .port_idx = pi, \ 511 .pad_type = pt, \ 512 .lane_idx = li, \ 513 } 514 static struct padctl_lane_map lane_map_tbl[] = { 515 LANE_MAP(0, PADCTL_PAD_PCIE, 6), /* port USB3-0 -> lane PCIE-0 */ 516 LANE_MAP(1, PADCTL_PAD_PCIE, 5), /* port USB3-1 -> lane PCIE-1 */ 517 LANE_MAP(2, PADCTL_PAD_PCIE, 0), /* port USB3-2 -> lane PCIE-0 */ 518 LANE_MAP(2, PADCTL_PAD_PCIE, 2), /* port USB3-2 -> lane PCIE-2 */ 519 LANE_MAP(3, PADCTL_PAD_PCIE, 4), /* port USB3-3 -> lane PCIE-4 */ 520 }; 521 522 /* Phy class and methods. */ 523 static int xusbpadctl_phy_enable(struct phynode *phy, bool enable); 524 static phynode_method_t xusbpadctl_phynode_methods[] = { 525 PHYNODEMETHOD(phynode_enable, xusbpadctl_phy_enable), 526 PHYNODEMETHOD_END 527 528 }; 529 DEFINE_CLASS_1(xusbpadctl_phynode, xusbpadctl_phynode_class, 530 xusbpadctl_phynode_methods, 0, phynode_class); 531 532 static struct padctl_port *search_lane_port(struct padctl_softc *sc, 533 struct padctl_lane *lane); 534 535 536 static void tegra210_xusb_pll_hw_control_enable(void) {} 537 static void tegra210_xusb_pll_hw_sequence_start(void) {} 538 static void tegra210_sata_pll_hw_control_enable(void) {} 539 static void tegra210_sata_pll_hw_sequence_start(void) {} 540 541 /* ------------------------------------------------------------------------- 542 * 543 * PEX functions 544 */ 545 static int 546 uphy_pex_enable(struct padctl_softc *sc, struct padctl_pad *pad) 547 { 548 uint32_t reg; 549 int rv, i; 550 551 if (sc->pcie_ena_cnt > 0) { 552 sc->pcie_ena_cnt++; 553 return (0); 554 } 555 556 /* 22.8.4 UPHY PLLs, Step 4, page 1346 */ 557 /* 1. Deassert PLL/Lane resets. */ 558 rv = clk_enable(pad->clk); 559 if (rv < 0) { 560 device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n", 561 pad->name, rv); 562 return (rv); 563 } 564 565 rv = hwreset_deassert(pad->reset); 566 if (rv < 0) { 567 device_printf(sc->dev, "Cannot unreset pad '%s': %d\n", 568 pad->name, rv); 569 clk_disable(pad->clk); 570 return (rv); 571 } 572 573 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 574 reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(~0); 575 reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(0x136); 576 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); 577 578 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5); 579 reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0); 580 reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a); 581 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg); 582 583 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 584 reg |= UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD; 585 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); 586 587 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 588 reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD; 589 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); 590 591 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 592 reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD; 593 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg); 594 595 /* 596 * 2. For the following registers, default values 597 * take care of the desired frequency. 598 */ 599 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 600 reg &= ~UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(~0); 601 reg &= ~UPHY_PLL_P0_CTL4_PLL0_REFCLK_SEL(~0); 602 reg |= UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(0x2); 603 reg |= UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_EN; 604 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg); 605 606 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 607 reg &= ~UPHY_PLL_P0_CTL1_PLL0_FREQ_MDIV(~0); 608 reg &= ~UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(~0); 609 reg |= UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(0x19); 610 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); 611 612 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 613 reg &= ~UPHY_PLL_P0_CTL1_PLL0_IDDQ; 614 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); 615 616 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 617 reg &= ~UPHY_PLL_P0_CTL1_PLL0_SLEEP(~0); 618 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); 619 620 /* 3. Wait 100 ns. */ 621 DELAY(10); 622 623 /* XXX This in not in TRM */ 624 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4); 625 reg |= UPHY_PLL_P0_CTL4_PLL0_REFCLKBUF_EN; 626 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg); 627 628 /* 4. Calibration. */ 629 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 630 reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_EN; 631 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); 632 for (i = 30; i > 0; i--) { 633 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 634 if (reg & UPHY_PLL_P0_CTL2_PLL0_CAL_DONE) 635 break; 636 DELAY(10); 637 } 638 if (i <= 0) { 639 device_printf(sc->dev, "Timedout in calibration step 1 " 640 "for pad '%s' (0x%08X).\n", pad->name, reg); 641 rv = ETIMEDOUT; 642 goto err; 643 } 644 645 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 646 reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_EN; 647 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); 648 for (i = 10; i > 0; i--) { 649 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 650 if ((reg & UPHY_PLL_P0_CTL2_PLL0_CAL_DONE) == 0) 651 break; 652 DELAY(10); 653 } 654 if (i <= 0) { 655 device_printf(sc->dev, "Timedout in calibration step 2 " 656 "for pad '%s'.\n", pad->name); 657 rv = ETIMEDOUT; 658 goto err; 659 } 660 661 /* 5. Enable the PLL (20 µs Lock time) */ 662 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 663 reg |= UPHY_PLL_P0_CTL1_PLL0_ENABLE; 664 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); 665 for (i = 10; i > 0; i--) { 666 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 667 if (reg & UPHY_PLL_P0_CTL1_PLL0_LOCKDET_STATUS) 668 break; 669 DELAY(10); 670 } 671 if (i <= 0) { 672 device_printf(sc->dev, "Timedout while enabling PLL " 673 "for pad '%s'.\n", pad->name); 674 rv = ETIMEDOUT; 675 goto err; 676 } 677 678 /* 6. RCAL. */ 679 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 680 reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_EN; 681 reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN; 682 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg); 683 684 for (i = 10; i > 0; i--) { 685 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 686 if (reg & UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE) 687 break; 688 DELAY(10); 689 } 690 if (i <= 0) { 691 device_printf(sc->dev, "Timedout in RX calibration step 1 " 692 "for pad '%s'.\n", pad->name); 693 rv = ETIMEDOUT; 694 goto err; 695 } 696 697 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 698 reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_EN; 699 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg); 700 701 for (i = 10; i > 0; i--) { 702 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 703 if (!(reg & UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE)) 704 break; 705 706 DELAY(10); 707 } 708 if (i <= 0) { 709 device_printf(sc->dev, "Timedout in RX calibration step 2 " 710 "for pad '%s'.\n", pad->name); 711 rv = ETIMEDOUT; 712 goto err; 713 } 714 715 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 716 reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN; 717 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg); 718 719 /* Enable Hardware Power Sequencer. */ 720 tegra210_xusb_pll_hw_control_enable(); 721 722 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); 723 reg &= ~UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD; 724 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); 725 726 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 727 reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD; 728 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); 729 730 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); 731 reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD; 732 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg); 733 734 DELAY(50); 735 736 tegra210_xusb_pll_hw_sequence_start(); 737 738 sc->pcie_ena_cnt++; 739 740 return (0); 741 742 err: 743 hwreset_deassert(pad->reset); 744 clk_disable(pad->clk); 745 return (rv); 746 } 747 748 static void 749 uphy_pex_disable(struct padctl_softc *sc, struct padctl_pad *pad) 750 { 751 int rv; 752 753 sc->pcie_ena_cnt--; 754 if (sc->pcie_ena_cnt <= 0) { 755 rv = hwreset_assert(pad->reset); 756 if (rv != 0) { 757 device_printf(sc->dev, "Cannot reset pad '%s': %d\n", 758 pad->name, rv); 759 } 760 rv = clk_disable(pad->clk); 761 if (rv != 0) { 762 device_printf(sc->dev, 763 "Cannot dicable clock for pad '%s': %d\n", 764 pad->name, rv); 765 } 766 } 767 } 768 769 static int 770 uphy_sata_enable(struct padctl_softc *sc, struct padctl_pad *pad, bool usb) 771 { 772 uint32_t reg; 773 int rv, i; 774 775 /* 22.8.4 UPHY PLLs, Step 4, page 1346 */ 776 /* 1. Deassert PLL/Lane resets. */ 777 if (sc->sata_ena_cnt > 0) { 778 sc->sata_ena_cnt++; 779 return (0); 780 } 781 782 rv = clk_enable(pad->clk); 783 if (rv < 0) { 784 device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n", 785 pad->name, rv); 786 return (rv); 787 } 788 789 rv = hwreset_deassert(pad->reset); 790 if (rv < 0) { 791 device_printf(sc->dev, "Cannot unreset pad '%s': %d\n", 792 pad->name, rv); 793 clk_disable(pad->clk); 794 return (rv); 795 } 796 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); 797 reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(~0); 798 reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(0x136); 799 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); 800 801 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5); 802 reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0); 803 reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a); 804 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg); 805 806 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 807 reg |= UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD; 808 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg); 809 810 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 811 reg |= UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD; 812 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg); 813 814 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 815 reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD; 816 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg); 817 818 /* 819 * 2. For the following registers, default values 820 * take care of the desired frequency. 821 */ 822 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4); 823 reg &= ~UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(~0); 824 reg &= ~UPHY_PLL_S0_CTL4_PLL0_REFCLK_SEL(~0); 825 reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_EN; 826 827 if (usb) 828 reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(0x2); 829 else 830 reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(0x0); 831 832 /* XXX PLL0_XDIGCLK_EN */ 833 /* 834 value &= ~(1 << 19); 835 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4, reg); 836 */ 837 838 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 839 reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_MDIV(~0); 840 reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(~0); 841 if (usb) 842 reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x19); 843 else 844 reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x1e); 845 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg); 846 847 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 848 reg &= ~UPHY_PLL_S0_CTL1_PLL0_IDDQ; 849 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg); 850 851 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 852 reg &= ~UPHY_PLL_S0_CTL1_PLL0_SLEEP(~0); 853 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg); 854 855 /* 3. Wait 100 ns. */ 856 DELAY(1); 857 858 /* XXX This in not in TRM */ 859 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4); 860 reg |= UPHY_PLL_S0_CTL4_PLL0_REFCLKBUF_EN; 861 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4, reg); 862 863 /* 4. Calibration. */ 864 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 865 reg |= UPHY_PLL_S0_CTL2_PLL0_CAL_EN; 866 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg); 867 for (i = 30; i > 0; i--) { 868 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 869 if (reg & UPHY_PLL_S0_CTL2_PLL0_CAL_DONE) 870 break; 871 DELAY(10); 872 } 873 if (i <= 0) { 874 device_printf(sc->dev, "Timedout in calibration step 1 " 875 "for pad '%s'.\n", pad->name); 876 rv = ETIMEDOUT; 877 goto err; 878 } 879 880 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 881 reg &= ~UPHY_PLL_S0_CTL2_PLL0_CAL_EN; 882 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg); 883 for (i = 10; i > 0; i--) { 884 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 885 if ((reg & UPHY_PLL_S0_CTL2_PLL0_CAL_DONE) == 0) 886 break; 887 DELAY(10); 888 } 889 if (i <= 0) { 890 device_printf(sc->dev, "Timedout in calibration step 2 " 891 "for pad '%s'.\n", pad->name); 892 rv = ETIMEDOUT; 893 goto err; 894 } 895 896 /* 5. Enable the PLL (20 µs Lock time) */ 897 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 898 reg |= UPHY_PLL_S0_CTL1_PLL0_ENABLE; 899 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg); 900 for (i = 10; i > 0; i--) { 901 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 902 if (reg & UPHY_PLL_S0_CTL1_PLL0_LOCKDET_STATUS) 903 break; 904 DELAY(10); 905 } 906 if (i <= 0) { 907 device_printf(sc->dev, "Timedout while enabling PLL " 908 "for pad '%s'.\n", pad->name); 909 rv = ETIMEDOUT; 910 goto err; 911 } 912 913 /* 6. RCAL. */ 914 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 915 reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_EN; 916 reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN; 917 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg); 918 for (i = 10; i > 0; i--) { 919 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 920 if (reg & UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE) 921 break; 922 DELAY(10); 923 } 924 if (i <= 0) { 925 device_printf(sc->dev, "Timedout in RX calibration step 1 " 926 "for pad '%s'.\n", pad->name); 927 rv = ETIMEDOUT; 928 goto err; 929 } 930 931 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 932 reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_EN; 933 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg); 934 for (i = 10; i > 0; i--) { 935 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 936 if (!(reg & UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE)) 937 break; 938 DELAY(10); 939 } 940 if (i <= 0) { 941 device_printf(sc->dev, "Timedout in RX calibration step 2 " 942 "for pad '%s'.\n", pad->name); 943 rv = ETIMEDOUT; 944 goto err; 945 } 946 947 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 948 reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN; 949 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg); 950 951 /* Enable Hardware Power Sequencer. */ 952 tegra210_sata_pll_hw_control_enable(); 953 954 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); 955 reg &= ~UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD; 956 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg); 957 958 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2); 959 reg &= ~UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD; 960 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg); 961 962 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8); 963 reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD; 964 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg); 965 966 DELAY(50); 967 968 tegra210_sata_pll_hw_sequence_start(); 969 970 sc->sata_ena_cnt++; 971 972 return (0); 973 974 err: 975 hwreset_deassert(pad->reset); 976 clk_disable(pad->clk); 977 return (rv); 978 } 979 980 static void 981 uphy_sata_disable(struct padctl_softc *sc, struct padctl_pad *pad) 982 { 983 int rv; 984 985 sc->sata_ena_cnt--; 986 if (sc->sata_ena_cnt <= 0) { 987 rv = hwreset_assert(pad->reset); 988 if (rv != 0) { 989 device_printf(sc->dev, "Cannot reset pad '%s': %d\n", 990 pad->name, rv); 991 } 992 rv = clk_disable(pad->clk); 993 if (rv != 0) { 994 device_printf(sc->dev, 995 "Cannot dicable clock for pad '%s': %d\n", 996 pad->name, rv); 997 } 998 } 999 } 1000 1001 1002 static int 1003 usb3_port_init(struct padctl_softc *sc, struct padctl_port *port) 1004 { 1005 uint32_t reg; 1006 struct padctl_pad *pad; 1007 int rv; 1008 1009 pad = port->lane->pad; 1010 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP); 1011 if (port->internal) 1012 reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx); 1013 else 1014 reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx); 1015 reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0); 1016 reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion); 1017 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg); 1018 1019 if (port->supply_vbus != NULL) { 1020 rv = regulator_enable(port->supply_vbus); 1021 if (rv != 0) { 1022 device_printf(sc->dev, 1023 "Cannot enable vbus regulator\n"); 1024 return (rv); 1025 } 1026 } 1027 1028 reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx)); 1029 reg &= ~UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(~0); 1030 reg |= UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(2); 1031 WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx), reg); 1032 1033 reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx)); 1034 reg &= ~UPHY_USB3_PAD_ECTL2_RX_CTLE(~0); 1035 reg |= UPHY_USB3_PAD_ECTL2_RX_CTLE(0x00fc); 1036 WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx), reg); 1037 1038 WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3(port->idx), 0xc0077f1f); 1039 1040 reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx)); 1041 reg &= ~UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(~0); 1042 reg |= UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(0x01c7); 1043 WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx), reg); 1044 1045 WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6(port->idx), 0xfcf01368); 1046 1047 if (pad->type == PADCTL_PAD_SATA) 1048 rv = uphy_sata_enable(sc, pad, true); 1049 else 1050 rv = uphy_pex_enable(sc, pad); 1051 if (rv != 0) 1052 return (rv); 1053 1054 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); 1055 reg &= ~ELPG_PROGRAM1_SSP_ELPG_VCORE_DOWN(port->idx); 1056 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); 1057 DELAY(100); 1058 1059 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); 1060 reg &= ~ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN_EARLY(port->idx); 1061 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); 1062 DELAY(100); 1063 1064 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); 1065 reg &= ~ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN(port->idx); 1066 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); 1067 DELAY(100); 1068 1069 return (0); 1070 } 1071 1072 static int 1073 pcie_enable(struct padctl_softc *sc, struct padctl_lane *lane) 1074 { 1075 uint32_t reg; 1076 int rv; 1077 1078 rv = uphy_pex_enable(sc, lane->pad); 1079 if (rv != 0) 1080 return (rv); 1081 1082 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 1083 reg |= USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx); 1084 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 1085 1086 return (0); 1087 } 1088 1089 static int 1090 pcie_disable(struct padctl_softc *sc, struct padctl_lane *lane) 1091 { 1092 uint32_t reg; 1093 1094 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 1095 reg &= ~USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx); 1096 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 1097 1098 uphy_pex_disable(sc, lane->pad); 1099 1100 return (0); 1101 1102 } 1103 1104 static int 1105 sata_enable(struct padctl_softc *sc, struct padctl_lane *lane) 1106 { 1107 uint32_t reg; 1108 int rv; 1109 1110 rv = uphy_sata_enable(sc, lane->pad, false); 1111 if (rv != 0) 1112 return (rv); 1113 1114 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 1115 reg |= USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->idx); 1116 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 1117 1118 return (0); 1119 } 1120 1121 static int 1122 sata_disable(struct padctl_softc *sc, struct padctl_lane *lane) 1123 { 1124 uint32_t reg; 1125 1126 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 1127 reg &= ~USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->idx); 1128 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 1129 1130 uphy_sata_disable(sc, lane->pad); 1131 1132 return (0); 1133 } 1134 1135 static int 1136 hsic_enable(struct padctl_softc *sc, struct padctl_lane *lane) 1137 { 1138 uint32_t reg; 1139 struct padctl_pad *pad; 1140 struct padctl_port *port; 1141 int rv; 1142 1143 port = search_lane_port(sc, lane); 1144 if (port == NULL) { 1145 device_printf(sc->dev, "Cannot find port for lane: %s\n", 1146 lane->name); 1147 } 1148 pad = lane->pad; 1149 1150 if (port->supply_vbus != NULL) { 1151 rv = regulator_enable(port->supply_vbus); 1152 if (rv != 0) { 1153 device_printf(sc->dev, 1154 "Cannot enable vbus regulator\n"); 1155 return (rv); 1156 } 1157 } 1158 1159 WR4(sc, XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL, sc->strobe_trim); 1160 1161 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx)); 1162 reg &= ~HSIC_PAD_CTL1_TX_RTUNEP(~0); 1163 reg |= HSIC_PAD_CTL1_TX_RTUNEP(sc->tx_rtune_p); 1164 WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg); 1165 1166 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx)); 1167 reg &= ~HSIC_PAD_CTL2_RX_STROBE_TRIM(~0); 1168 reg &= ~HSIC_PAD_CTL2_RX_DATA1_TRIM(~0); 1169 reg &= ~HSIC_PAD_CTL2_RX_DATA0_TRIM(~0); 1170 reg |= HSIC_PAD_CTL2_RX_STROBE_TRIM(sc->rx_strobe_trim); 1171 reg |= HSIC_PAD_CTL2_RX_DATA1_TRIM(sc->rx_data1_trim); 1172 reg |= HSIC_PAD_CTL2_RX_DATA0_TRIM(sc->rx_data0_trim); 1173 WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx), reg); 1174 1175 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx)); 1176 reg &= ~HSIC_PAD_CTL0_RPU_DATA0; 1177 reg &= ~HSIC_PAD_CTL0_RPU_DATA1; 1178 reg &= ~HSIC_PAD_CTL0_RPU_STROBE; 1179 reg &= ~HSIC_PAD_CTL0_PD_RX_DATA0; 1180 reg &= ~HSIC_PAD_CTL0_PD_RX_DATA1; 1181 reg &= ~HSIC_PAD_CTL0_PD_RX_STROBE; 1182 reg &= ~HSIC_PAD_CTL0_PD_ZI_DATA0; 1183 reg &= ~HSIC_PAD_CTL0_PD_ZI_DATA1; 1184 reg &= ~HSIC_PAD_CTL0_PD_ZI_STROBE; 1185 reg &= ~HSIC_PAD_CTL0_PD_TX_DATA0; 1186 reg &= ~HSIC_PAD_CTL0_PD_TX_DATA1; 1187 reg &= ~HSIC_PAD_CTL0_PD_TX_STROBE; 1188 reg |= HSIC_PAD_CTL0_RPD_DATA0; 1189 reg |= HSIC_PAD_CTL0_RPD_DATA1; 1190 reg |= HSIC_PAD_CTL0_RPD_STROBE; 1191 WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx), reg); 1192 1193 rv = clk_enable(pad->clk); 1194 if (rv < 0) { 1195 device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n", 1196 pad->name, rv); 1197 if (port->supply_vbus != NULL) 1198 regulator_disable(port->supply_vbus); 1199 return (rv); 1200 } 1201 1202 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL); 1203 reg &= ~HSIC_PAD_TRK_CTL_TRK_START_TIMER(~0); 1204 reg &= ~HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(~0); 1205 reg |= HSIC_PAD_TRK_CTL_TRK_START_TIMER(0x1e); 1206 reg |= HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(0x0a); 1207 WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg); 1208 1209 DELAY(10); 1210 1211 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL); 1212 reg &= ~HSIC_PAD_TRK_CTL_PD_TRK; 1213 WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg); 1214 1215 DELAY(50); 1216 clk_disable(pad->clk); 1217 return (0); 1218 } 1219 1220 static int 1221 hsic_disable(struct padctl_softc *sc, struct padctl_lane *lane) 1222 { 1223 uint32_t reg; 1224 struct padctl_port *port; 1225 int rv; 1226 1227 port = search_lane_port(sc, lane); 1228 if (port == NULL) { 1229 device_printf(sc->dev, "Cannot find port for lane: %s\n", 1230 lane->name); 1231 } 1232 1233 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx)); 1234 reg |= HSIC_PAD_CTL0_PD_RX_DATA0; 1235 reg |= HSIC_PAD_CTL0_PD_RX_DATA1; 1236 reg |= HSIC_PAD_CTL0_PD_RX_STROBE; 1237 reg |= HSIC_PAD_CTL0_PD_ZI_DATA0; 1238 reg |= HSIC_PAD_CTL0_PD_ZI_DATA1; 1239 reg |= HSIC_PAD_CTL0_PD_ZI_STROBE; 1240 reg |= HSIC_PAD_CTL0_PD_TX_DATA0; 1241 reg |= HSIC_PAD_CTL0_PD_TX_DATA1; 1242 reg |= HSIC_PAD_CTL0_PD_TX_STROBE; 1243 WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg); 1244 1245 if (port->supply_vbus != NULL) { 1246 rv = regulator_disable(port->supply_vbus); 1247 if (rv != 0) { 1248 device_printf(sc->dev, 1249 "Cannot disable vbus regulator\n"); 1250 return (rv); 1251 } 1252 } 1253 1254 return (0); 1255 } 1256 1257 static int 1258 usb2_enable(struct padctl_softc *sc, struct padctl_lane *lane) 1259 { 1260 uint32_t reg; 1261 struct padctl_pad *pad; 1262 struct padctl_port *port; 1263 int rv; 1264 1265 port = search_lane_port(sc, lane); 1266 if (port == NULL) { 1267 device_printf(sc->dev, "Cannot find port for lane: %s\n", 1268 lane->name); 1269 } 1270 pad = lane->pad; 1271 1272 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 1273 reg &= ~USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(~0); 1274 reg &= ~USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(~0); 1275 reg |= USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(0x7); 1276 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); 1277 1278 reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP); 1279 reg &= ~USB2_PORT_CAP_PORT_CAP(lane->idx, ~0); 1280 reg |= USB2_PORT_CAP_PORT_CAP(lane->idx, USB2_PORT_CAP_PORT_CAP_HOST); 1281 WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg); 1282 1283 reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx)); 1284 reg &= ~USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(~0); 1285 reg &= ~USB2_OTG_PAD_CTL0_HS_SLEW(~0); 1286 reg &= ~USB2_OTG_PAD_CTL0_PD; 1287 reg &= ~USB2_OTG_PAD_CTL0_PD2; 1288 reg &= ~USB2_OTG_PAD_CTL0_PD_ZI; 1289 reg |= USB2_OTG_PAD_CTL0_HS_SLEW(14); 1290 reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level[lane->idx] + 1291 sc->hs_curr_level_offs); 1292 WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg); 1293 1294 reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx)); 1295 reg &= ~USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(~0); 1296 reg &= ~USB2_OTG_PAD_CTL1_RPD_CTRL(~0); 1297 reg &= ~USB2_OTG_PAD_CTL1_PD_DR; 1298 reg &= ~USB2_OTG_PAD_CTL1_PD_CHRP_OVRD; 1299 reg &= ~USB2_OTG_PAD_CTL1_PD_DISC_OVRD; 1300 reg |= USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(sc->hs_term_range_adj); 1301 reg |= USB2_OTG_PAD_CTL1_RPD_CTRL(sc->rpd_ctrl); 1302 WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg); 1303 1304 reg = RD4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx)); 1305 reg &= ~USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(~0); 1306 reg |= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18; 1307 WR4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx), reg); 1308 1309 if (port->supply_vbus != NULL) { 1310 rv = regulator_enable(port->supply_vbus); 1311 if (rv != 0) { 1312 device_printf(sc->dev, 1313 "Cannot enable vbus regulator\n"); 1314 return (rv); 1315 } 1316 } 1317 rv = clk_enable(pad->clk); 1318 if (rv < 0) { 1319 device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n", 1320 pad->name, rv); 1321 if (port->supply_vbus != NULL) 1322 regulator_disable(port->supply_vbus); 1323 return (rv); 1324 } 1325 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); 1326 reg &= ~USB2_BIAS_PAD_CTL1_TRK_START_TIMER(~0); 1327 reg &= ~USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(~0); 1328 reg |= USB2_BIAS_PAD_CTL1_TRK_START_TIMER(0x1e); 1329 reg |= USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(0x0a); 1330 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, reg); 1331 1332 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 1333 reg &= ~USB2_BIAS_PAD_CTL0_PD; 1334 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); 1335 return (0); 1336 } 1337 1338 static int 1339 usb2_disable(struct padctl_softc *sc, struct padctl_lane *lane) 1340 { 1341 uint32_t reg; 1342 struct padctl_pad *pad; 1343 struct padctl_port *port; 1344 int rv; 1345 1346 port = search_lane_port(sc, lane); 1347 if (port == NULL) { 1348 device_printf(sc->dev, "Cannot find port for lane: %s\n", 1349 lane->name); 1350 } 1351 pad = lane->pad; 1352 1353 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 1354 reg |= USB2_BIAS_PAD_CTL0_PD; 1355 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); 1356 1357 if (port->supply_vbus != NULL) { 1358 rv = regulator_disable(port->supply_vbus); 1359 if (rv != 0) { 1360 device_printf(sc->dev, 1361 "Cannot disable vbus regulator\n"); 1362 return (rv); 1363 } 1364 } 1365 1366 rv = clk_disable(pad->clk); 1367 if (rv < 0) { 1368 device_printf(sc->dev, "Cannot disable clock for pad '%s': %d\n", 1369 pad->name, rv); 1370 return (rv); 1371 } 1372 1373 return (0); 1374 } 1375 1376 1377 static int 1378 pad_common_enable(struct padctl_softc *sc) 1379 { 1380 uint32_t reg; 1381 1382 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); 1383 reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; 1384 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); 1385 DELAY(100); 1386 1387 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); 1388 reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; 1389 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); 1390 DELAY(100); 1391 1392 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); 1393 reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; 1394 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); 1395 DELAY(100); 1396 1397 return (0); 1398 } 1399 1400 static int 1401 pad_common_disable(struct padctl_softc *sc) 1402 { 1403 uint32_t reg; 1404 1405 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); 1406 reg |= ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; 1407 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); 1408 DELAY(100); 1409 1410 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); 1411 reg |= ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; 1412 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); 1413 DELAY(100); 1414 1415 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); 1416 reg |= ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; 1417 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); 1418 DELAY(100); 1419 1420 return (0); 1421 } 1422 1423 static int 1424 xusbpadctl_phy_enable(struct phynode *phy, bool enable) 1425 { 1426 device_t dev; 1427 intptr_t id; 1428 struct padctl_softc *sc; 1429 struct padctl_lane *lane; 1430 struct padctl_pad *pad; 1431 int rv; 1432 1433 dev = phynode_get_device(phy); 1434 id = phynode_get_id(phy); 1435 sc = device_get_softc(dev); 1436 1437 if (id < 0 || id >= nitems(lanes_tbl)) { 1438 device_printf(dev, "Unknown phy: %d\n", (int)id); 1439 return (ENXIO); 1440 } 1441 1442 lane = lanes_tbl + id; 1443 if (!lane->enabled) { 1444 device_printf(dev, "Lane is not enabled/configured: %s\n", 1445 lane->name); 1446 return (ENXIO); 1447 } 1448 1449 pad = lane->pad; 1450 if (enable) { 1451 if (sc->phy_ena_cnt == 0) { 1452 rv = pad_common_enable(sc); 1453 if (rv != 0) 1454 return (rv); 1455 } 1456 sc->phy_ena_cnt++; 1457 } 1458 1459 if (enable) 1460 rv = pad->enable(sc, lane); 1461 else 1462 rv = pad->disable(sc, lane); 1463 if (rv != 0) 1464 return (rv); 1465 1466 if (!enable) { 1467 if (sc->phy_ena_cnt == 1) { 1468 rv = pad_common_disable(sc); 1469 if (rv != 0) 1470 return (rv); 1471 } 1472 sc->phy_ena_cnt--; 1473 } 1474 1475 return (0); 1476 } 1477 1478 /* ------------------------------------------------------------------------- 1479 * 1480 * FDT processing 1481 */ 1482 static struct padctl_port * 1483 search_port(struct padctl_softc *sc, char *port_name) 1484 { 1485 int i; 1486 1487 for (i = 0; i < nitems(ports_tbl); i++) { 1488 if (strcmp(port_name, ports_tbl[i].name) == 0) 1489 return (&ports_tbl[i]); 1490 } 1491 return (NULL); 1492 } 1493 1494 static struct padctl_port * 1495 search_lane_port(struct padctl_softc *sc, struct padctl_lane *lane) 1496 { 1497 int i; 1498 1499 for (i = 0; i < nitems(ports_tbl); i++) { 1500 if (!ports_tbl[i].enabled) 1501 continue; 1502 if (ports_tbl[i].lane == lane) 1503 return (ports_tbl + i); 1504 } 1505 return (NULL); 1506 } 1507 1508 static struct padctl_lane * 1509 search_lane(struct padctl_softc *sc, char *lane_name) 1510 { 1511 int i; 1512 1513 for (i = 0; i < nitems(lanes_tbl); i++) { 1514 if (strcmp(lane_name, lanes_tbl[i].name) == 0) 1515 return (lanes_tbl + i); 1516 } 1517 return (NULL); 1518 } 1519 1520 static struct padctl_lane * 1521 search_pad_lane(struct padctl_softc *sc, enum padctl_pad_type type, int idx) 1522 { 1523 int i; 1524 1525 for (i = 0; i < nitems(lanes_tbl); i++) { 1526 if (!lanes_tbl[i].enabled) 1527 continue; 1528 if (type == lanes_tbl[i].pad->type && idx == lanes_tbl[i].idx) 1529 return (lanes_tbl + i); 1530 } 1531 return (NULL); 1532 } 1533 1534 static struct padctl_lane * 1535 search_usb3_pad_lane(struct padctl_softc *sc, int idx) 1536 { 1537 int i; 1538 struct padctl_lane *lane, *tmp; 1539 1540 lane = NULL; 1541 for (i = 0; i < nitems(lane_map_tbl); i++) { 1542 if (idx != lane_map_tbl[i].port_idx) 1543 continue; 1544 tmp = search_pad_lane(sc, lane_map_tbl[i].pad_type, 1545 lane_map_tbl[i].lane_idx); 1546 if (tmp == NULL) 1547 continue; 1548 if (strcmp(tmp->mux[tmp->mux_idx], "usb3-ss") != 0) 1549 continue; 1550 if (lane != NULL) { 1551 device_printf(sc->dev, "Duplicated mappings found for" 1552 " lanes: %s and %s\n", lane->name, tmp->name); 1553 return (NULL); 1554 } 1555 lane = tmp; 1556 } 1557 return (lane); 1558 } 1559 1560 static struct padctl_pad * 1561 search_pad(struct padctl_softc *sc, char *pad_name) 1562 { 1563 int i; 1564 1565 for (i = 0; i < nitems(pads_tbl); i++) { 1566 if (strcmp(pad_name, pads_tbl[i].name) == 0) 1567 return (pads_tbl + i); 1568 } 1569 return (NULL); 1570 } 1571 1572 static int 1573 search_mux(struct padctl_softc *sc, struct padctl_lane *lane, char *fnc_name) 1574 { 1575 int i; 1576 1577 for (i = 0; i < lane->nmux; i++) { 1578 if (strcmp(fnc_name, lane->mux[i]) == 0) 1579 return (i); 1580 } 1581 return (-1); 1582 } 1583 1584 static int 1585 config_lane(struct padctl_softc *sc, struct padctl_lane *lane) 1586 { 1587 uint32_t reg; 1588 1589 reg = RD4(sc, lane->reg); 1590 reg &= ~(lane->mask << lane->shift); 1591 reg |= (lane->mux_idx & lane->mask) << lane->shift; 1592 WR4(sc, lane->reg, reg); 1593 return (0); 1594 } 1595 1596 static int 1597 process_lane(struct padctl_softc *sc, phandle_t node, struct padctl_pad *pad) 1598 { 1599 struct padctl_lane *lane; 1600 struct phynode *phynode; 1601 struct phynode_init_def phy_init; 1602 char *name; 1603 char *function; 1604 int rv; 1605 1606 name = NULL; 1607 function = NULL; 1608 rv = OF_getprop_alloc(node, "name", (void **)&name); 1609 if (rv <= 0) { 1610 device_printf(sc->dev, "Cannot read lane name.\n"); 1611 return (ENXIO); 1612 } 1613 1614 lane = search_lane(sc, name); 1615 if (lane == NULL) { 1616 device_printf(sc->dev, "Unknown lane: %s\n", name); 1617 rv = ENXIO; 1618 goto end; 1619 } 1620 1621 /* Read function (mux) settings. */ 1622 rv = OF_getprop_alloc(node, "nvidia,function", (void **)&function); 1623 if (rv <= 0) { 1624 device_printf(sc->dev, "Cannot read lane function.\n"); 1625 rv = ENXIO; 1626 goto end; 1627 } 1628 1629 lane->mux_idx = search_mux(sc, lane, function); 1630 if (lane->mux_idx == ~0) { 1631 device_printf(sc->dev, "Unknown function %s for lane %s\n", 1632 function, name); 1633 rv = ENXIO; 1634 goto end; 1635 } 1636 1637 rv = config_lane(sc, lane); 1638 if (rv != 0) { 1639 device_printf(sc->dev, "Cannot configure lane: %s: %d\n", 1640 name, rv); 1641 rv = ENXIO; 1642 goto end; 1643 } 1644 lane->xref = OF_xref_from_node(node); 1645 lane->pad = pad; 1646 lane->enabled = true; 1647 pad->lanes[pad->nlanes++] = lane; 1648 1649 /* Create and register phy. */ 1650 bzero(&phy_init, sizeof(phy_init)); 1651 phy_init.id = lane - lanes_tbl; 1652 phy_init.ofw_node = node; 1653 phynode = phynode_create(sc->dev, &xusbpadctl_phynode_class, &phy_init); 1654 if (phynode == NULL) { 1655 device_printf(sc->dev, "Cannot create phy\n"); 1656 rv = ENXIO; 1657 goto end; 1658 } 1659 if (phynode_register(phynode) == NULL) { 1660 device_printf(sc->dev, "Cannot create phy\n"); 1661 return (ENXIO); 1662 } 1663 1664 rv = 0; 1665 1666 end: 1667 if (name != NULL) 1668 OF_prop_free(name); 1669 if (function != NULL) 1670 OF_prop_free(function); 1671 return (rv); 1672 } 1673 1674 static int 1675 process_pad(struct padctl_softc *sc, phandle_t node) 1676 { 1677 phandle_t xref; 1678 struct padctl_pad *pad; 1679 char *name; 1680 int rv; 1681 1682 name = NULL; 1683 rv = OF_getprop_alloc(node, "name", (void **)&name); 1684 if (rv <= 0) { 1685 device_printf(sc->dev, "Cannot read pad name.\n"); 1686 return (ENXIO); 1687 } 1688 1689 pad = search_pad(sc, name); 1690 if (pad == NULL) { 1691 device_printf(sc->dev, "Unknown pad: %s\n", name); 1692 rv = ENXIO; 1693 goto end; 1694 } 1695 1696 if (pad->clock_name != NULL) { 1697 rv = clk_get_by_ofw_name(sc->dev, node, pad->clock_name, 1698 &pad->clk); 1699 if (rv != 0) { 1700 device_printf(sc->dev, "Cannot get '%s' clock\n", 1701 pad->clock_name); 1702 return (ENXIO); 1703 } 1704 } 1705 1706 if (pad->reset_name != NULL) { 1707 rv = hwreset_get_by_ofw_name(sc->dev, node, pad->reset_name, 1708 &pad->reset); 1709 if (rv != 0) { 1710 device_printf(sc->dev, "Cannot get '%s' reset\n", 1711 pad->reset_name); 1712 return (ENXIO); 1713 } 1714 } 1715 1716 /* Read and process associated lanes. */ 1717 node = ofw_bus_find_child(node, "lanes"); 1718 if (node <= 0) { 1719 device_printf(sc->dev, "Cannot find 'lanes' subnode\n"); 1720 rv = ENXIO; 1721 goto end; 1722 } 1723 1724 for (node = OF_child(node); node != 0; node = OF_peer(node)) { 1725 if (!ofw_bus_node_status_okay(node)) 1726 continue; 1727 1728 rv = process_lane(sc, node, pad); 1729 if (rv != 0) 1730 goto end; 1731 1732 xref = OF_xref_from_node(node); 1733 OF_device_register_xref(xref, sc->dev); 1734 } 1735 pad->enabled = true; 1736 rv = 0; 1737 end: 1738 if (name != NULL) 1739 OF_prop_free(name); 1740 return (rv); 1741 } 1742 1743 static int 1744 process_port(struct padctl_softc *sc, phandle_t node) 1745 { 1746 1747 struct padctl_port *port; 1748 char *name; 1749 int rv; 1750 1751 name = NULL; 1752 rv = OF_getprop_alloc(node, "name", (void **)&name); 1753 if (rv <= 0) { 1754 device_printf(sc->dev, "Cannot read port name.\n"); 1755 return (ENXIO); 1756 } 1757 1758 port = search_port(sc, name); 1759 if (port == NULL) { 1760 device_printf(sc->dev, "Unknown port: %s\n", name); 1761 rv = ENXIO; 1762 goto end; 1763 } 1764 1765 regulator_get_by_ofw_property(sc->dev, node, 1766 "vbus-supply", &port->supply_vbus); 1767 1768 if (OF_hasprop(node, "nvidia,internal")) 1769 port->internal = true; 1770 1771 /* Find assigned lane */ 1772 if (port->lane == NULL) { 1773 switch(port->type) { 1774 /* Routing is fixed for USB2 AND HSIC. */ 1775 case PADCTL_PORT_USB2: 1776 port->lane = search_pad_lane(sc, PADCTL_PAD_USB2, 1777 port->idx); 1778 break; 1779 case PADCTL_PORT_HSIC: 1780 port->lane = search_pad_lane(sc, PADCTL_PAD_HSIC, 1781 port->idx); 1782 break; 1783 case PADCTL_PORT_USB3: 1784 port->lane = search_usb3_pad_lane(sc, port->idx); 1785 break; 1786 } 1787 } 1788 if (port->lane == NULL) { 1789 device_printf(sc->dev, "Cannot find lane for port: %s\n", name); 1790 rv = ENXIO; 1791 goto end; 1792 } 1793 1794 if (port->type == PADCTL_PORT_USB3) { 1795 rv = OF_getencprop(node, "nvidia,usb2-companion", 1796 &(port->companion), sizeof(port->companion)); 1797 if (rv <= 0) { 1798 device_printf(sc->dev, 1799 "Missing 'nvidia,usb2-companion' property " 1800 "for port: %s\n", name); 1801 rv = ENXIO; 1802 goto end; 1803 } 1804 } 1805 1806 port->enabled = true; 1807 rv = 0; 1808 end: 1809 if (name != NULL) 1810 OF_prop_free(name); 1811 return (rv); 1812 } 1813 1814 static int 1815 parse_fdt(struct padctl_softc *sc, phandle_t base_node) 1816 { 1817 phandle_t node; 1818 int rv; 1819 1820 rv = 0; 1821 node = ofw_bus_find_child(base_node, "pads"); 1822 1823 if (node <= 0) { 1824 device_printf(sc->dev, "Cannot find pads subnode.\n"); 1825 return (ENXIO); 1826 } 1827 for (node = OF_child(node); node != 0; node = OF_peer(node)) { 1828 if (!ofw_bus_node_status_okay(node)) 1829 continue; 1830 rv = process_pad(sc, node); 1831 if (rv != 0) 1832 return (rv); 1833 } 1834 1835 node = ofw_bus_find_child(base_node, "ports"); 1836 if (node <= 0) { 1837 device_printf(sc->dev, "Cannot find ports subnode.\n"); 1838 return (ENXIO); 1839 } 1840 for (node = OF_child(node); node != 0; node = OF_peer(node)) { 1841 if (!ofw_bus_node_status_okay(node)) 1842 continue; 1843 rv = process_port(sc, node); 1844 if (rv != 0) 1845 return (rv); 1846 } 1847 1848 return (0); 1849 } 1850 1851 static void 1852 load_calibration(struct padctl_softc *sc) 1853 { 1854 uint32_t reg; 1855 int i; 1856 1857 reg = tegra_fuse_read_4(FUSE_SKU_CALIB_0); 1858 sc->hs_curr_level[0] = FUSE_SKU_CALIB_0_HS_CURR_LEVEL_0(reg); 1859 for (i = 1; i < nitems(sc->hs_curr_level); i++) { 1860 sc->hs_curr_level[i] = 1861 FUSE_SKU_CALIB_0_HS_CURR_LEVEL_123(reg, i); 1862 } 1863 sc->hs_term_range_adj = FUSE_SKU_CALIB_0_HS_TERM_RANGE_ADJ(reg); 1864 1865 tegra_fuse_read_4(FUSE_USB_CALIB_EXT_0); 1866 sc->rpd_ctrl = FUSE_USB_CALIB_EXT_0_RPD_CTRL(reg); 1867 } 1868 1869 /* ------------------------------------------------------------------------- 1870 * 1871 * BUS functions 1872 */ 1873 static int 1874 xusbpadctl_probe(device_t dev) 1875 { 1876 1877 if (!ofw_bus_status_okay(dev)) 1878 return (ENXIO); 1879 1880 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 1881 return (ENXIO); 1882 1883 device_set_desc(dev, "Tegra XUSB phy"); 1884 return (BUS_PROBE_DEFAULT); 1885 } 1886 1887 static int 1888 xusbpadctl_detach(device_t dev) 1889 { 1890 1891 /* This device is always present. */ 1892 return (EBUSY); 1893 } 1894 1895 static int 1896 xusbpadctl_attach(device_t dev) 1897 { 1898 struct padctl_softc * sc; 1899 int i, rid, rv; 1900 struct padctl_port *port; 1901 phandle_t node; 1902 1903 sc = device_get_softc(dev); 1904 sc->dev = dev; 1905 node = ofw_bus_get_node(dev); 1906 rid = 0; 1907 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1908 RF_ACTIVE); 1909 if (sc->mem_res == NULL) { 1910 device_printf(dev, "Cannot allocate memory resources\n"); 1911 return (ENXIO); 1912 } 1913 1914 rv = hwreset_get_by_ofw_name(dev, 0, "padctl", &sc->rst); 1915 if (rv != 0) { 1916 device_printf(dev, "Cannot get 'padctl' reset: %d\n", rv); 1917 return (rv); 1918 } 1919 rv = hwreset_deassert(sc->rst); 1920 if (rv != 0) { 1921 device_printf(dev, "Cannot unreset 'padctl' reset: %d\n", rv); 1922 return (rv); 1923 } 1924 1925 load_calibration(sc); 1926 1927 rv = parse_fdt(sc, node); 1928 if (rv != 0) { 1929 device_printf(dev, "Cannot parse fdt configuration: %d\n", rv); 1930 return (rv); 1931 } 1932 for (i = 0; i < nitems(ports_tbl); i++) { 1933 port = ports_tbl + i; 1934 if (!port->enabled) 1935 continue; 1936 if (port->init == NULL) 1937 continue; 1938 rv = port->init(sc, port); 1939 if (rv != 0) { 1940 device_printf(dev, "Cannot init port '%s'\n", 1941 port->name); 1942 return (rv); 1943 } 1944 } 1945 return (0); 1946 } 1947 1948 static device_method_t tegra_xusbpadctl_methods[] = { 1949 /* Device interface */ 1950 DEVMETHOD(device_probe, xusbpadctl_probe), 1951 DEVMETHOD(device_attach, xusbpadctl_attach), 1952 DEVMETHOD(device_detach, xusbpadctl_detach), 1953 1954 DEVMETHOD_END 1955 }; 1956 1957 static DEFINE_CLASS_0(xusbpadctl, tegra_xusbpadctl_driver, 1958 tegra_xusbpadctl_methods, sizeof(struct padctl_softc)); 1959 EARLY_DRIVER_MODULE(tegra_xusbpadctl, simplebus, tegra_xusbpadctl_driver, 1960 NULL, NULL, 73);
Cache object: c3b9a918f1685dc26e935d6c58167896
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