1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2020 Alstom Group.
5 * Copyright (c) 2020 Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 *
30 */
31
32 #ifndef _QORIQ_CLKGEN_H_
33 #define _QORIQ_CLKGEN_H_
34
35 #include <dev/extres/clk/clk.h>
36 #include <dev/extres/clk/clk_mux.h>
37
38 #include <arm64/qoriq/clk/qoriq_clk_pll.h>
39
40 #define QORIQ_CLK_NAME_MAX_LEN 32
41
42 #define QORIQ_LITTLE_ENDIAN 0x01
43
44 #define QORIQ_TYPE_SYSCLK 0
45 #define QORIQ_TYPE_CMUX 1
46 #define QORIQ_TYPE_HWACCEL 2
47 #define QORIQ_TYPE_FMAN 3
48 #define QORIQ_TYPE_PLATFORM_PLL 4
49 #define QORIQ_TYPE_CORECLK 5
50 #define QORIQ_TYPE_INTERNAL 6
51
52 #define PLL_DIV1 0
53 #define PLL_DIV2 1
54 #define PLL_DIV3 2
55 #define PLL_DIV4 3
56 #define PLL_DIV5 4
57 #define PLL_DIV6 5
58 #define PLL_DIV7 6
59 #define PLL_DIV8 7
60 #define PLL_DIV9 8
61 #define PLL_DIV10 9
62 #define PLL_DIV11 10
63 #define PLL_DIV12 11
64 #define PLL_DIV13 12
65 #define PLL_DIV14 13
66 #define PLL_DIV15 14
67 #define PLL_DIV16 15
68
69 #define QORIQ_CLK_ID(_type, _index) ((_type << 8) + _index)
70
71 #define QORIQ_SYSCLK_NAME "clockgen_sysclk"
72 #define QORIQ_CORECLK_NAME "clockgen_coreclk"
73
74 typedef int (*qoriq_init_func_t)(device_t);
75
76 struct qoriq_clkgen_softc {
77 device_t dev;
78 struct resource *res;
79 struct clkdom *clkdom;
80 struct mtx mtx;
81 struct qoriq_clk_pll_def *pltfrm_pll_def;
82 struct qoriq_clk_pll_def **cga_pll;
83 int cga_pll_num;
84 struct clk_mux_def **mux;
85 int mux_num;
86 qoriq_init_func_t init_func;
87 uint32_t flags;
88 bool has_coreclk;
89 };
90
91 MALLOC_DECLARE(M_QORIQ_CLKGEN);
92 DECLARE_CLASS(qoriq_clkgen_driver);
93
94 int qoriq_clkgen_attach(device_t);
95
96 #endif /* _QORIQ_CLKGEN_H_ */
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