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sys/arm64/rockchip/clk/rk3328_cru.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018-2021 Emmanuel Vadot <manu@freebsd.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <machine/bus.h> 40 41 #include <dev/fdt/simplebus.h> 42 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 46 #include <dev/extres/clk/clk_div.h> 47 #include <dev/extres/clk/clk_fixed.h> 48 #include <dev/extres/clk/clk_mux.h> 49 50 #include <arm64/rockchip/clk/rk_cru.h> 51 52 #define CRU_CLKSEL_CON(x) (0x100 + (x) * 0x4) 53 54 /* Registers */ 55 #define RK3328_GRF_SOC_CON4 0x410 56 #define RK3328_GRF_MAC_CON1 0x904 57 #define RK3328_GRF_MAC_CON2 0x908 58 59 /* Exported clocks */ 60 61 #define PLL_APLL 1 62 #define PLL_DPLL 2 63 #define PLL_CPLL 3 64 #define PLL_GPLL 4 65 #define PLL_NPLL 5 66 #define ARMCLK 6 67 68 /* SCLK */ 69 #define SCLK_RTC32K 30 70 #define SCLK_SDMMC_EXT 31 71 #define SCLK_SPI 32 72 #define SCLK_SDMMC 33 73 #define SCLK_SDIO 34 74 #define SCLK_EMMC 35 75 #define SCLK_TSADC 36 76 #define SCLK_SARADC 37 77 #define SCLK_UART0 38 78 #define SCLK_UART1 39 79 #define SCLK_UART2 40 80 #define SCLK_I2S0 41 81 #define SCLK_I2S1 42 82 #define SCLK_I2S2 43 83 #define SCLK_I2S1_OUT 44 84 #define SCLK_I2S2_OUT 45 85 #define SCLK_SPDIF 46 86 #define SCLK_TIMER0 47 87 #define SCLK_TIMER1 48 88 #define SCLK_TIMER2 49 89 #define SCLK_TIMER3 50 90 #define SCLK_TIMER4 51 91 #define SCLK_TIMER5 52 92 #define SCLK_WIFI 53 93 #define SCLK_CIF_OUT 54 94 #define SCLK_I2C0 55 95 #define SCLK_I2C1 56 96 #define SCLK_I2C2 57 97 #define SCLK_I2C3 58 98 #define SCLK_CRYPTO 59 99 #define SCLK_PWM 60 100 #define SCLK_PDM 61 101 #define SCLK_EFUSE 62 102 #define SCLK_OTP 63 103 #define SCLK_DDRCLK 64 104 #define SCLK_VDEC_CABAC 65 105 #define SCLK_VDEC_CORE 66 106 #define SCLK_VENC_DSP 67 107 #define SCLK_VENC_CORE 68 108 #define SCLK_RGA 69 109 #define SCLK_HDMI_SFC 70 110 #define SCLK_HDMI_CEC 71 /* Unused ? */ 111 #define SCLK_USB3_REF 72 112 #define SCLK_USB3_SUSPEND 73 113 #define SCLK_SDMMC_DRV 74 114 #define SCLK_SDIO_DRV 75 115 #define SCLK_EMMC_DRV 76 116 #define SCLK_SDMMC_EXT_DRV 77 117 #define SCLK_SDMMC_SAMPLE 78 118 #define SCLK_SDIO_SAMPLE 79 119 #define SCLK_EMMC_SAMPLE 80 120 #define SCLK_SDMMC_EXT_SAMPLE 81 121 #define SCLK_VOP 82 122 #define SCLK_MAC2PHY_RXTX 83 123 #define SCLK_MAC2PHY_SRC 84 124 #define SCLK_MAC2PHY_REF 85 125 #define SCLK_MAC2PHY_OUT 86 126 #define SCLK_MAC2IO_RX 87 127 #define SCLK_MAC2IO_TX 88 128 #define SCLK_MAC2IO_REFOUT 89 129 #define SCLK_MAC2IO_REF 90 130 #define SCLK_MAC2IO_OUT 91 131 #define SCLK_TSP 92 132 #define SCLK_HSADC_TSP 93 133 #define SCLK_USB3PHY_REF 94 134 #define SCLK_REF_USB3OTG 95 135 #define SCLK_USB3OTG_REF 96 136 #define SCLK_USB3OTG_SUSPEND 97 137 #define SCLK_REF_USB3OTG_SRC 98 138 #define SCLK_MAC2IO_SRC 99 139 #define SCLK_MAC2IO 100 140 #define SCLK_MAC2PHY 101 141 #define SCLK_MAC2IO_EXT 102 142 143 /* DCLK */ 144 #define DCLK_LCDC 120 145 #define DCLK_HDMIPHY 121 146 #define HDMIPHY 122 147 #define USB480M 123 148 #define DCLK_LCDC_SRC 124 149 150 /* ACLK */ 151 #define ACLK_AXISRAM 130 /* Unused */ 152 #define ACLK_VOP_PRE 131 153 #define ACLK_USB3OTG 132 154 #define ACLK_RGA_PRE 133 155 #define ACLK_DMAC 134 /* Unused */ 156 #define ACLK_GPU 135 157 #define ACLK_BUS_PRE 136 158 #define ACLK_PERI_PRE 137 159 #define ACLK_RKVDEC_PRE 138 160 #define ACLK_RKVDEC 139 161 #define ACLK_RKVENC 140 162 #define ACLK_VPU_PRE 141 163 #define ACLK_VIO_PRE 142 164 #define ACLK_VPU 143 165 #define ACLK_VIO 144 166 #define ACLK_VOP 145 167 #define ACLK_GMAC 146 168 #define ACLK_H265 147 169 #define ACLK_H264 148 170 #define ACLK_MAC2PHY 149 171 #define ACLK_MAC2IO 150 172 #define ACLK_DCF 151 173 #define ACLK_TSP 152 174 #define ACLK_PERI 153 175 #define ACLK_RGA 154 176 #define ACLK_IEP 155 177 #define ACLK_CIF 156 178 #define ACLK_HDCP 157 179 180 /* PCLK */ 181 #define PCLK_GPIO0 200 182 #define PCLK_GPIO1 201 183 #define PCLK_GPIO2 202 184 #define PCLK_GPIO3 203 185 #define PCLK_GRF 204 186 #define PCLK_I2C0 205 187 #define PCLK_I2C1 206 188 #define PCLK_I2C2 207 189 #define PCLK_I2C3 208 190 #define PCLK_SPI 209 191 #define PCLK_UART0 210 192 #define PCLK_UART1 211 193 #define PCLK_UART2 212 194 #define PCLK_TSADC 213 195 #define PCLK_PWM 214 196 #define PCLK_TIMER 215 197 #define PCLK_BUS_PRE 216 198 #define PCLK_PERI_PRE 217 /* Unused */ 199 #define PCLK_HDMI_CTRL 218 /* Unused */ 200 #define PCLK_HDMI_PHY 219 /* Unused */ 201 #define PCLK_GMAC 220 202 #define PCLK_H265 221 203 #define PCLK_MAC2PHY 222 204 #define PCLK_MAC2IO 223 205 #define PCLK_USB3PHY_OTG 224 206 #define PCLK_USB3PHY_PIPE 225 207 #define PCLK_USB3_GRF 226 208 #define PCLK_USB2_GRF 227 209 #define PCLK_HDMIPHY 228 210 #define PCLK_DDR 229 211 #define PCLK_PERI 230 212 #define PCLK_HDMI 231 213 #define PCLK_HDCP 232 214 #define PCLK_DCF 233 215 #define PCLK_SARADC 234 216 #define PCLK_ACODECPHY 235 217 #define PCLK_WDT 236 /* Controlled from the secure GRF */ 218 219 /* HCLK */ 220 #define HCLK_PERI 308 221 #define HCLK_TSP 309 222 #define HCLK_GMAC 310 /* Unused */ 223 #define HCLK_I2S0_8CH 311 224 #define HCLK_I2S1_8CH 312 225 #define HCLK_I2S2_2CH 313 226 #define HCLK_SPDIF_8CH 314 227 #define HCLK_VOP 315 228 #define HCLK_NANDC 316 /* Unused */ 229 #define HCLK_SDMMC 317 230 #define HCLK_SDIO 318 231 #define HCLK_EMMC 319 232 #define HCLK_SDMMC_EXT 320 233 #define HCLK_RKVDEC_PRE 321 234 #define HCLK_RKVDEC 322 235 #define HCLK_RKVENC 323 236 #define HCLK_VPU_PRE 324 237 #define HCLK_VIO_PRE 325 238 #define HCLK_VPU 326 239 /* 327 doesn't exists */ 240 #define HCLK_BUS_PRE 328 241 #define HCLK_PERI_PRE 329 /* Unused */ 242 #define HCLK_H264 330 243 #define HCLK_CIF 331 244 #define HCLK_OTG_PMU 332 245 #define HCLK_OTG 333 246 #define HCLK_HOST0 334 247 #define HCLK_HOST0_ARB 335 248 #define HCLK_CRYPTO_MST 336 249 #define HCLK_CRYPTO_SLV 337 250 #define HCLK_PDM 338 251 #define HCLK_IEP 339 252 #define HCLK_RGA 340 253 #define HCLK_HDCP 341 254 255 static struct rk_cru_gate rk3328_gates[] = { 256 /* CRU_CLKGATE_CON0 */ 257 CRU_GATE(0, "core_apll_clk", "apll", 0x200, 0) 258 CRU_GATE(0, "core_dpll_clk", "dpll", 0x200, 1) 259 CRU_GATE(0, "core_gpll_clk", "gpll", 0x200, 2) 260 /* Bit 3 bus_src_clk_en */ 261 /* Bit 4 clk_ddrphy_src_en */ 262 /* Bit 5 clk_ddrpd_src_en */ 263 /* Bit 6 clk_ddrmon_en */ 264 /* Bit 7-8 unused */ 265 /* Bit 9 testclk_en */ 266 CRU_GATE(SCLK_WIFI, "sclk_wifi", "sclk_wifi_c", 0x200, 10) 267 CRU_GATE(SCLK_RTC32K, "clk_rtc32k", "clk_rtc32k_c", 0x200, 11) 268 CRU_GATE(0, "core_npll_clk", "npll", 0x200, 12) 269 /* Bit 13-15 unused */ 270 271 /* CRU_CLKGATE_CON1 */ 272 /* Bit 0 unused */ 273 CRU_GATE(0, "clk_i2s0_div", "clk_i2s0_div_c", 0x204, 1) 274 CRU_GATE(0, "clk_i2s0_frac", "clk_i2s0_frac_f", 0x204, 2) 275 CRU_GATE(SCLK_I2S0, "clk_i2s0", "clk_i2s0_mux", 0x204, 3) 276 CRU_GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 0x204, 4) 277 CRU_GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_f", 0x204, 5) 278 CRU_GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", 0x204, 6) 279 CRU_GATE(0, "clk_i2s1_out", "clk_i2s1_mux", 0x204, 7) 280 CRU_GATE(0, "clk_i2s2_div", "clk_i2s2_div_c", 0x204, 8) 281 CRU_GATE(0, "clk_i2s2_frac", "clk_i2s2_frac_f", 0x204, 9) 282 CRU_GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", 0x204, 10) 283 CRU_GATE(0, "clk_i2s2_out", "clk_i2s2_mux", 0x204, 11) 284 CRU_GATE(0, "clk_spdif_div", "clk_spdif_div_c", 0x204, 12) 285 CRU_GATE(0, "clk_spdif_frac", "clk_spdif_frac_f", 0x204, 13) 286 CRU_GATE(0, "clk_uart0_div", "clk_uart0_div_c", 0x204, 14) 287 CRU_GATE(0, "clk_uart0_frac", "clk_uart0_frac_f", 0x204, 15) 288 289 /* CRU_CLKGATE_CON2 */ 290 CRU_GATE(0, "clk_uart1_div", "clk_uart1_div_c", 0x208, 0) 291 CRU_GATE(0, "clk_uart1_frac", "clk_uart1_frac_f", 0x208, 1) 292 CRU_GATE(0, "clk_uart2_div", "clk_uart2_div_c", 0x208, 2) 293 CRU_GATE(0, "clk_uart2_frac", "clk_uart2_frac_f", 0x208, 3) 294 CRU_GATE(SCLK_CRYPTO, "clk_crypto", "clk_crypto_c", 0x208, 4) 295 CRU_GATE(SCLK_TSP, "clk_tsp", "clk_tsp_c", 0x208, 5) 296 CRU_GATE(SCLK_TSADC, "clk_tsadc_src", "clk_tsadc_c", 0x208, 6) 297 CRU_GATE(SCLK_SPI, "clk_spi", "clk_spi_c", 0x208, 7) 298 CRU_GATE(SCLK_PWM, "clk_pwm", "clk_pwm_c", 0x208, 8) 299 CRU_GATE(SCLK_I2C0, "clk_i2c0_src", "clk_i2c0_c", 0x208, 9) 300 CRU_GATE(SCLK_I2C1, "clk_i2c1_src", "clk_i2c1_c", 0x208, 10) 301 CRU_GATE(SCLK_I2C2, "clk_i2c2_src", "clk_i2c2_c", 0x208, 11) 302 CRU_GATE(SCLK_I2C3, "clk_i2c3_src", "clk_i2c3_c", 0x208, 12) 303 CRU_GATE(SCLK_EFUSE, "clk_efuse", "clk_efuse_c", 0x208, 13) 304 CRU_GATE(SCLK_SARADC, "clk_saradc", "clk_saradc_c", 0x208, 14) 305 CRU_GATE(SCLK_PDM, "clk_pdm", "clk_pdm_c", 0x208, 15) 306 307 /* CRU_CLKGATE_CON3 */ 308 CRU_GATE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", "clk_mac2phy_src_c", 0x20c, 0) 309 CRU_GATE(SCLK_MAC2IO_SRC, "clk_mac2io_src", "clk_mac2io_src_c", 0x20c, 1) 310 CRU_GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_c", 0x20c, 2) 311 /* Bit 3 gmac_gpll_src_en Unused ? */ 312 /* Bit 4 gmac_vpll_src_en Unused ? */ 313 CRU_GATE(SCLK_MAC2IO_OUT, "clk_mac2io_out", "clk_mac2io_out_c", 0x20c, 5) 314 /* Bit 6-7 unused */ 315 CRU_GATE(SCLK_OTP, "clk_otp", "clk_otp_c", 0x20c, 8) 316 /* Bit 9-15 unused */ 317 318 /* CRU_CLKGATE_CON4 */ 319 CRU_GATE(0, "periph_gclk_src", "gpll", 0x210, 0) 320 CRU_GATE(0, "periph_cclk_src", "cpll", 0x210, 1) 321 CRU_GATE(0, "hdmiphy_peri", "hdmiphy", 0x210, 2) 322 CRU_GATE(SCLK_SDMMC, "clk_mmc0_src", "clk_sdmmc_c", 0x210, 3) 323 CRU_GATE(SCLK_SDIO, "clk_sdio_src", "clk_sdio_c", 0x210, 4) 324 CRU_GATE(SCLK_EMMC, "clk_emmc_src", "clk_emmc_c", 0x210, 5) 325 CRU_GATE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", "clk_ref_usb3otg_src_c", 0x210, 6) 326 CRU_GATE(SCLK_USB3OTG_REF, "clk_usb3_otg0_ref", "xin24m", 0x210, 7) 327 CRU_GATE(SCLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", "clk_usb3otg_suspend_c", 0x210, 8) 328 /* Bit 9 clk_usb3phy_ref_25m_en */ 329 CRU_GATE(SCLK_SDMMC_EXT, "clk_sdmmc_ext", "clk_sdmmc_ext_c", 0x210, 10) 330 /* Bit 11-15 unused */ 331 332 /* CRU_CLKGATE_CON5 */ 333 CRU_GATE(ACLK_RGA_PRE, "aclk_rga_pre", "aclk_rga_pre_c", 0x214, 0) 334 CRU_GATE(SCLK_RGA, "sclk_rga", "sclk_rga_c", 0x214, 0) 335 CRU_GATE(ACLK_VIO_PRE, "aclk_vio_pre", "aclk_vio_pre_c", 0x214, 2) 336 CRU_GATE(SCLK_CIF_OUT, "clk_cif_src", "clk_cif_src_c", 0x214, 3) 337 CRU_GATE(SCLK_HDMI_SFC, "clk_hdmi_sfc", "xin24m", 0x214, 4) 338 CRU_GATE(ACLK_VOP_PRE, "aclk_vop_pre", "aclk_vop_pre_c", 0x214, 5) 339 CRU_GATE(DCLK_LCDC_SRC, "vop_dclk_src", "vop_dclk_src_c", 0x214, 6) 340 /* Bit 7-15 unused */ 341 342 /* CRU_CLKGATE_CON6 */ 343 CRU_GATE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", "aclk_rkvdec_c", 0x218, 0) 344 CRU_GATE(SCLK_VDEC_CABAC, "sclk_cabac", "sclk_cabac_c", 0x218, 1) 345 CRU_GATE(SCLK_VDEC_CORE, "sclk_vdec_core", "sclk_vdec_core_c", 0x218, 2) 346 CRU_GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_c", 0x218, 3) 347 CRU_GATE(SCLK_VENC_CORE, "sclk_venc", "sclk_venc_c", 0x218, 4) 348 CRU_GATE(ACLK_VPU_PRE, "aclk_vpu_pre", "aclk_vpu_pre_c", 0x218, 5) 349 CRU_GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c", 0x218, 6) 350 CRU_GATE(SCLK_VENC_DSP, "sclk_venc_dsp", "sclk_venc_dsp_c", 0x218, 7) 351 /* Bit 8-15 unused */ 352 353 /* CRU_CLKGATE_CON7 */ 354 /* Bit 0 aclk_core_en */ 355 /* Bit 1 clk_core_periph_en */ 356 /* Bit 2 clk_jtag_en */ 357 /* Bit 3 unused */ 358 /* Bit 4 pclk_ddr_en */ 359 /* Bit 5-15 unused */ 360 361 /* CRU_CLKGATE_CON8 */ 362 CRU_GATE(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_pre_c", 0x220, 0) 363 CRU_GATE(HCLK_BUS_PRE, "hclk_bus_pre", "hclk_bus_pre_c", 0x220, 1) 364 CRU_GATE(PCLK_BUS_PRE, "pclk_bus_pre", "pclk_bus_pre_c", 0x220, 2) 365 CRU_GATE(0, "pclk_bus", "pclk_bus_pre", 0x220, 3) 366 CRU_GATE(0, "pclk_phy", "pclk_bus_pre", 0x220, 4) 367 CRU_GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0x220, 5) 368 CRU_GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0x220, 6) 369 CRU_GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0x220, 7) 370 CRU_GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0x220, 8) 371 CRU_GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0x220, 9) 372 CRU_GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0x220, 10) 373 /* Bit 11-15 unused */ 374 375 /* CRU_CLKGATE_CON9 */ 376 CRU_GATE(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0x224, 0) 377 CRU_GATE(SCLK_MAC2PHY_RXTX, "clk_gmac2phy_rx", "clk_mac2phy", 0x224, 1) 378 CRU_GATE(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy_out_c", 0x224, 2) 379 CRU_GATE(SCLK_MAC2PHY_REF, "clk_gmac2phy_ref", "clk_mac2phy", 0x224, 3) 380 CRU_GATE(SCLK_MAC2IO_RX, "clk_gmac2io_rx", "clk_mac2io", 0x224, 4) 381 CRU_GATE(SCLK_MAC2IO_TX, "clk_gmac2io_tx", "clk_mac2io", 0x224, 5) 382 CRU_GATE(SCLK_MAC2IO_REFOUT, "clk_gmac2io_refout", "clk_mac2io", 0x224, 6) 383 CRU_GATE(SCLK_MAC2IO_REF, "clk_gmac2io_ref", "clk_mac2io", 0x224, 7) 384 /* Bit 8-15 unused */ 385 386 /* CRU_CLKGATE_CON10 */ 387 CRU_GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0x228, 0) 388 CRU_GATE(HCLK_PERI, "hclk_peri", "hclk_peri_c", 0x228, 1) 389 CRU_GATE(PCLK_PERI, "pclk_peri", "pclk_peri_c", 0x228, 2) 390 /* Bit 3-15 unused */ 391 392 /* CRU_CLKGATE_CON11 */ 393 CRU_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0x22C, 0) 394 /* Bit 1-3 unused */ 395 CRU_GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 0x22C, 4) 396 /* Bit 5-7 unused */ 397 CRU_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0x22C, 8) 398 /* Bit 9-15 unused */ 399 400 /* CRU_CLKGATE_CON12 */ 401 /* unused */ 402 403 /* CRU_CLKGATE_CON13 */ 404 /* Bit 0 aclk_core_niu_en */ 405 /* Bit 1 aclk_gic400_en */ 406 /* Bit 2-15 unused */ 407 408 /* CRU_CLKGATE_CON14 */ 409 CRU_GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0x238, 0) 410 CRU_GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0x238, 1) 411 /* Bit 2-15 unused */ 412 413 /* CRU_CLKGATE_CON15*/ 414 /* Bit 0 aclk_intmem_en Unused */ 415 /* Bit 1 aclk_dmac_bus_en Unused */ 416 /* Bit 2 hclk_rom_en Unused */ 417 CRU_GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0x23C, 3) 418 CRU_GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 0x23C, 4) 419 CRU_GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0x23C, 5) 420 CRU_GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 0x23C, 6) 421 CRU_GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0x23C, 7) 422 CRU_GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0x23C, 8) 423 CRU_GATE(0, "pclk_efuse", "pclk_bus", 0x23C, 9) 424 CRU_GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0x23C, 10) 425 CRU_GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0x23C, 11) 426 CRU_GATE(0, "aclk_bus_niu", "aclk_bus_pre", 0x23C, 12) 427 CRU_GATE(0, "hclk_bus_niu", "hclk_bus_pre", 0x23C, 13) 428 CRU_GATE(0, "pclk_bus_niu", "pclk_bus_pre", 0x23C, 14) 429 CRU_GATE(0, "pclk_phy_niu", "pclk_phy", 0x23C, 14) 430 /* Bit 15 pclk_phy_niu_en */ 431 432 /* CRU_CLKGATE_CON16 */ 433 CRU_GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0x240, 0) 434 CRU_GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0x240, 1) 435 CRU_GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0x240, 2) 436 CRU_GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", 0x240, 3) 437 CRU_GATE(0, "pclk_stimer", "pclk_bus", 0x240, 4) 438 CRU_GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 0x240, 5) 439 CRU_GATE(PCLK_PWM, "pclk_pwm", "pclk_bus", 0x240, 6) 440 CRU_GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0x240, 7) 441 CRU_GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0x240, 8) 442 CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0x240, 9) 443 CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0x240, 10) 444 CRU_GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0x240, 11) 445 CRU_GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0x240, 12) 446 CRU_GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0x240, 13) 447 CRU_GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0x240, 14) 448 CRU_GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0x240, 15) 449 450 /* CRU_CLKGATE_CON17 */ 451 CRU_GATE(PCLK_GRF, "pclk_grf", "pclk_bus", 0x244, 0) 452 /* Bit 1 unused */ 453 CRU_GATE(PCLK_USB3_GRF, "pclk_usb3grf", "pclk_phy", 0x244, 2) 454 CRU_GATE(0, "pclk_ddrphy", "pclk_phy", 0x244, 3) 455 CRU_GATE(0, "pclk_cru", "pclk_bus", 0x244, 4) 456 CRU_GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy", 0x244, 5) 457 CRU_GATE(0, "pclk_sgrf", "pclk_bus", 0x244, 6) 458 CRU_GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy", 0x244, 7) 459 CRU_GATE(0, "pclk_vdacphy", "pclk_bus", 0x244, 8) 460 /* Bit 9 unused */ 461 CRU_GATE(0, "pclk_sim", "pclk_bus", 0x244, 10) 462 CRU_GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 0x244, 11) 463 CRU_GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 0x244, 12) 464 /* Bit 13 clk_hsadc_0_tsp_en Depend on a gpio clock ? */ 465 CRU_GATE(PCLK_USB2_GRF, "pclk_usb2grf", "pclk_phy", 0x244, 14) 466 CRU_GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0x244, 15) 467 468 /* CRU_CLKGATE_CON18 */ 469 /* Bit 0 unused */ 470 /* Bit 1 pclk_ddr_upctl_en */ 471 /* Bit 2 pclk_ddr_msch_en */ 472 /* Bit 3 pclk_ddr_mon_en */ 473 /* Bit 4 aclk_ddr_upctl_en */ 474 /* Bit 5 clk_ddr_upctl_en */ 475 /* Bit 6 clk_ddr_msch_en */ 476 /* Bit 7 pclk_ddrstdby_en */ 477 /* Bit 8-15 unused */ 478 479 /* CRU_CLKGATE_CON19 */ 480 CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0x24C, 0) 481 CRU_GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0x24C, 1) 482 CRU_GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0x24C, 2) 483 /* Bit 3-5 unused */ 484 CRU_GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0x24C, 6) 485 CRU_GATE(HCLK_HOST0_ARB, "hclk_host0_arg", "hclk_peri", 0x24C, 7) 486 CRU_GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0x24C, 8) 487 CRU_GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0x24C, 9) 488 /* Bit 10 unused */ 489 CRU_GATE(0, "aclk_peri_niu", "aclk_peri", 0x24C, 11) 490 CRU_GATE(0, "hclk_peri_niu", "hclk_peri", 0x24C, 12) 491 CRU_GATE(0, "pclk_peri_niu", "hclk_peri", 0x24C, 13) 492 CRU_GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0x24C, 14) 493 CRU_GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0x24C, 15) 494 495 /* CRU_CLKGATE_CON20 */ 496 /* unused */ 497 498 /* CRU_CLKGATE_CON21 */ 499 /* Bit 0-1 unused */ 500 CRU_GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0x254, 2) 501 CRU_GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0x254, 3) 502 CRU_GATE(0, "aclk_vop_niu", "aclk_vop_pre", 0x254, 4) 503 CRU_GATE(0, "hclk_vop_niu", "hclk_vio_pre", 0x254, 5) 504 CRU_GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 0x254, 6) 505 CRU_GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0x254, 7) 506 CRU_GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 0x254, 8) 507 CRU_GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 0x254, 9) 508 CRU_GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0x254, 10) 509 CRU_GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0x254, 11) 510 CRU_GATE(0, "hclk_ahb1tom", "hclk_vio_pre", 0x254, 12) 511 CRU_GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0x254, 13) 512 CRU_GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0x254, 14) 513 CRU_GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 0x254, 15) 514 515 /* CRU_CLKGATE_CON22 */ 516 CRU_GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0x258, 0) 517 CRU_GATE(0, "hclk_vio_niu", "hclk_vio_pre", 0x258, 1) 518 CRU_GATE(0, "aclk_vio_niu", "aclk_vio_pre", 0x258, 2) 519 CRU_GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0x258, 3) 520 CRU_GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0x258, 4) 521 CRU_GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0x258, 5) 522 /* Bit 6-15 unused */ 523 524 /* CRU_CLKGATE_CON23 */ 525 CRU_GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0x25C, 0) 526 CRU_GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0x25C, 1) 527 CRU_GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 0x25C, 2) 528 CRU_GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 0x25C, 3) 529 /* Bit 4-15 unused */ 530 531 /* CRU_CLKGATE_CON24 */ 532 CRU_GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0x260, 0) 533 CRU_GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0x260, 1) 534 CRU_GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 0x260, 2) 535 CRU_GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 0x260, 3) 536 /* Bit 4-15 unused */ 537 538 /* CRU_CLKGATE_CON25 */ 539 CRU_GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 0x264, 0) 540 CRU_GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0x264, 1) 541 CRU_GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0x264, 2) 542 CRU_GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0x264, 3) 543 CRU_GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0x264, 4) 544 CRU_GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0x264, 5) 545 CRU_GATE(0, "aclk_axisram", "hclk_rkvenc", 0x264, 6) 546 /* Bit 7-15 unused */ 547 548 /* CRU_CLKGATE_CON26 */ 549 CRU_GATE(ACLK_MAC2PHY, "aclk_gmac2phy", "aclk_gmac", 0x268, 0) 550 CRU_GATE(PCLK_MAC2PHY, "pclk_gmac2phy", "pclk_gmac", 0x268, 1) 551 CRU_GATE(ACLK_MAC2IO, "aclk_gmac2io", "aclk_gmac", 0x268, 2) 552 CRU_GATE(PCLK_MAC2IO, "pclk_gmac2io", "pclk_gmac", 0x268, 3) 553 CRU_GATE(0, "aclk_gmac_niu", "aclk_gmac", 0x268, 4) 554 CRU_GATE(0, "pclk_gmac_niu", "pclk_gmac", 0x268, 5) 555 /* Bit 6-15 unused */ 556 557 /* CRU_CLKGATE_CON27 */ 558 /* Bit 0 clk_ddrphy_en */ 559 /* Bit 1 clk4x_ddrphy_en */ 560 561 /* CRU_CLKGATE_CON28 */ 562 CRU_GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0x270, 0) 563 CRU_GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy", 0x270, 1) 564 CRU_GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy", 0x270, 2) 565 CRU_GATE(0, "pclk_pmu", "pclk_bus", 0x270, 3) 566 CRU_GATE(0, "pclk_otp", "pclk_bus", 0x270, 4) 567 /* Bit 5-15 unused */ 568 }; 569 570 /* 571 * PLLs 572 */ 573 574 #define PLL_RATE(_hz, _ref, _fb, _post1, _post2, _dspd, _frac) \ 575 { \ 576 .freq = _hz, \ 577 .refdiv = _ref, \ 578 .fbdiv = _fb, \ 579 .postdiv1 = _post1, \ 580 .postdiv2 = _post2, \ 581 .dsmpd = _dspd, \ 582 .frac = _frac, \ 583 } 584 585 static struct rk_clk_pll_rate rk3328_pll_rates[] = { 586 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 587 PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 588 PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 589 PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 590 PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 591 PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 592 PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 593 PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 594 PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 595 PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 596 PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 597 PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 598 PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 599 PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 600 PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 601 PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 602 PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 603 PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 604 PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 605 PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 606 PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 607 PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 608 PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 609 PLL_RATE(984000000, 1, 82, 2, 1, 1, 0), 610 PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), 611 PLL_RATE(936000000, 1, 78, 2, 1, 1, 0), 612 PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), 613 PLL_RATE(900000000, 4, 300, 2, 1, 1, 0), 614 PLL_RATE(888000000, 1, 74, 2, 1, 1, 0), 615 PLL_RATE(864000000, 1, 72, 2, 1, 1, 0), 616 PLL_RATE(840000000, 1, 70, 2, 1, 1, 0), 617 PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 618 PLL_RATE(800000000, 6, 400, 2, 1, 1, 0), 619 PLL_RATE(700000000, 6, 350, 2, 1, 1, 0), 620 PLL_RATE(696000000, 1, 58, 2, 1, 1, 0), 621 PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), 622 PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), 623 PLL_RATE(504000000, 1, 63, 3, 1, 1, 0), 624 PLL_RATE(500000000, 6, 250, 2, 1, 1, 0), 625 PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), 626 PLL_RATE(312000000, 1, 52, 2, 2, 1, 0), 627 PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), 628 PLL_RATE(96000000, 1, 64, 4, 4, 1, 0), 629 {}, 630 }; 631 632 static struct rk_clk_pll_rate rk3328_pll_frac_rates[] = { 633 PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217), 634 PLL_RATE(983040000, 24, 983, 1, 1, 0, 671088), 635 PLL_RATE(491520000, 24, 983, 2, 1, 0, 671088), 636 PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088), 637 PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797894), 638 PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066329), 639 {}, 640 }; 641 642 /* Clock parents */ 643 #define PLIST(_name) static const char *_name[] 644 645 PLIST(pll_src_p) = {"xin24m"}; 646 PLIST(xin24m_rtc32k_p) = {"xin24m", "clk_rtc32k"}; 647 648 PLIST(pll_src_cpll_gpll_p) = {"cpll", "gpll"}; 649 PLIST(pll_src_cpll_gpll_apll_p) = {"cpll", "gpll", "apll"}; 650 PLIST(pll_src_cpll_gpll_xin24m_p) = {"cpll", "gpll", "xin24m", "xin24m" /* Dummy */}; 651 PLIST(pll_src_cpll_gpll_usb480m_p) = {"cpll", "gpll", "usb480m"}; 652 PLIST(pll_src_cpll_gpll_hdmiphy_p) = {"cpll", "gpll", "hdmi_phy"}; 653 PLIST(pll_src_cpll_gpll_hdmiphy_usb480m_p) = {"cpll", "gpll", "hdmi_phy", "usb480m"}; 654 PLIST(pll_src_apll_gpll_dpll_npll_p) = {"apll", "gpll", "dpll", "npll"}; 655 PLIST(pll_src_cpll_gpll_xin24m_usb480m_p) = {"cpll", "gpll", "xin24m", "usb480m"}; 656 PLIST(mux_ref_usb3otg_p) = { "xin24m", "clk_usb3_otg0_ref" }; 657 PLIST(mux_mac2io_p) = { "clk_mac2io_src", "gmac_clkin" }; 658 PLIST(mux_mac2io_ext_p) = { "clk_mac2io", "gmac_clkin" }; 659 PLIST(mux_mac2phy_p) = { "clk_mac2phy_src", "phy_50m_out" }; 660 PLIST(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", "xin12m", "xin12m" }; 661 PLIST(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", "clkin_i2s1", "xin12m" }; 662 PLIST(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", "clkin_i2s2", "xin12m" }; 663 PLIST(mux_dclk_lcdc_p) = {"hdmiphy", "vop_dclk_src"}; 664 PLIST(mux_hdmiphy_p) = {"hdmi_phy", "xin24m"}; 665 PLIST(mux_usb480m_p) = {"usb480m_phy", "xin24m"}; 666 PLIST(mux_uart0_p) = {"clk_uart0_div", "clk_uart0_frac", "xin24m", "xin24m"}; 667 PLIST(mux_uart1_p) = {"clk_uart1_div", "clk_uart1_frac", "xin24m", "xin24m"}; 668 PLIST(mux_uart2_p) = {"clk_uart2_div", "clk_uart2_frac", "xin24m", "xin24m"}; 669 PLIST(mux_spdif_p) = {"clk_spdif_div", "clk_spdif_frac", "xin12m", "xin12m"}; 670 PLIST(mux_cif_p) = {"clk_cif_pll", "xin24m"}; 671 672 static struct rk_clk_pll_def apll = { 673 .clkdef = { 674 .id = PLL_APLL, 675 .name = "apll", 676 .parent_names = pll_src_p, 677 .parent_cnt = nitems(pll_src_p), 678 }, 679 .base_offset = 0x00, 680 .gate_offset = 0x200, 681 .gate_shift = 0, 682 .mode_reg = 0x80, 683 .mode_shift = 1, 684 .flags = RK_CLK_PLL_HAVE_GATE, 685 .frac_rates = rk3328_pll_frac_rates, 686 }; 687 688 static struct rk_clk_pll_def dpll = { 689 .clkdef = { 690 .id = PLL_DPLL, 691 .name = "dpll", 692 .parent_names = pll_src_p, 693 .parent_cnt = nitems(pll_src_p), 694 }, 695 .base_offset = 0x20, 696 .gate_offset = 0x200, 697 .gate_shift = 1, 698 .mode_reg = 0x80, 699 .mode_shift = 4, 700 .flags = RK_CLK_PLL_HAVE_GATE, 701 }; 702 703 static struct rk_clk_pll_def cpll = { 704 .clkdef = { 705 .id = PLL_CPLL, 706 .name = "cpll", 707 .parent_names = pll_src_p, 708 .parent_cnt = nitems(pll_src_p), 709 }, 710 .base_offset = 0x40, 711 .mode_reg = 0x80, 712 .mode_shift = 8, 713 .rates = rk3328_pll_rates, 714 }; 715 716 static struct rk_clk_pll_def gpll = { 717 .clkdef = { 718 .id = PLL_GPLL, 719 .name = "gpll", 720 .parent_names = pll_src_p, 721 .parent_cnt = nitems(pll_src_p), 722 }, 723 .base_offset = 0x60, 724 .gate_offset = 0x200, 725 .gate_shift = 2, 726 .mode_reg = 0x80, 727 .mode_shift = 12, 728 .flags = RK_CLK_PLL_HAVE_GATE, 729 .frac_rates = rk3328_pll_frac_rates, 730 }; 731 732 static struct rk_clk_pll_def npll = { 733 .clkdef = { 734 .id = PLL_NPLL, 735 .name = "npll", 736 .parent_names = pll_src_p, 737 .parent_cnt = nitems(pll_src_p), 738 }, 739 .base_offset = 0xa0, 740 .gate_offset = 0x200, 741 .gate_shift = 12, 742 .mode_reg = 0x80, 743 .mode_shift = 1, 744 .flags = RK_CLK_PLL_HAVE_GATE, 745 .rates = rk3328_pll_rates, 746 }; 747 748 static struct rk_clk_armclk_rates rk3328_armclk_rates[] = { 749 { 750 .freq = 1296000000, 751 .div = 1, 752 }, 753 { 754 .freq = 1200000000, 755 .div = 1, 756 }, 757 { 758 .freq = 1104000000, 759 .div = 1, 760 }, 761 { 762 .freq = 1008000000, 763 .div = 1, 764 }, 765 { 766 .freq = 912000000, 767 .div = 1, 768 }, 769 { 770 .freq = 816000000, 771 .div = 1, 772 }, 773 { 774 .freq = 696000000, 775 .div = 1, 776 }, 777 { 778 .freq = 600000000, 779 .div = 1, 780 }, 781 { 782 .freq = 408000000, 783 .div = 1, 784 }, 785 { 786 .freq = 312000000, 787 .div = 1, 788 }, 789 { 790 .freq = 216000000, 791 .div = 1, 792 }, 793 { 794 .freq = 96000000, 795 .div = 1, 796 }, 797 }; 798 799 static struct rk_clk_armclk_def armclk = { 800 .clkdef = { 801 .id = ARMCLK, 802 .name = "armclk", 803 .parent_names = pll_src_apll_gpll_dpll_npll_p, 804 .parent_cnt = nitems(pll_src_apll_gpll_dpll_npll_p), 805 }, 806 .muxdiv_offset = 0x100, 807 .mux_shift = 6, 808 .mux_width = 2, 809 810 .div_shift = 0, 811 .div_width = 5, 812 813 .flags = RK_CLK_COMPOSITE_HAVE_MUX, 814 .main_parent = 3, /* npll */ 815 .alt_parent = 0, /* apll */ 816 817 .rates = rk3328_armclk_rates, 818 .nrates = nitems(rk3328_armclk_rates), 819 }; 820 821 static struct rk_clk rk3328_clks[] = { 822 /* External clocks */ 823 LINK("xin24m"), 824 LINK("gmac_clkin"), 825 LINK("hdmi_phy"), 826 LINK("usb480m_phy"), 827 FRATE(0, "xin12m", 12000000), 828 FRATE(0, "phy_50m_out", 50000000), 829 FRATE(0, "clkin_i2s1", 0), 830 FRATE(0, "clkin_i2s2", 0), 831 832 /* PLLs */ 833 { 834 .type = RK3328_CLK_PLL, 835 .clk.pll = &apll 836 }, 837 { 838 .type = RK3328_CLK_PLL, 839 .clk.pll = &dpll 840 }, 841 { 842 .type = RK3328_CLK_PLL, 843 .clk.pll = &cpll 844 }, 845 { 846 .type = RK3328_CLK_PLL, 847 .clk.pll = &gpll 848 }, 849 { 850 .type = RK3328_CLK_PLL, 851 .clk.pll = &npll 852 }, 853 854 { 855 .type = RK_CLK_ARMCLK, 856 .clk.armclk = &armclk, 857 }, 858 859 /* CRU_CRU_MISC */ 860 MUXRAW(HDMIPHY, "hdmiphy", mux_hdmiphy_p, 0, 0x84, 13, 1), 861 MUXRAW(USB480M, "usb480m", mux_usb480m_p, 0, 0x84, 15, 1), 862 863 /* CRU_CLKSEL_CON0 */ 864 /* COMP clk_core_div_con core_clk_pll_sel */ 865 COMP(0, "aclk_bus_pre_c", pll_src_cpll_gpll_hdmiphy_p, 0, 0, 8, 5, 13, 2), 866 867 /* CRU_CLKSEL_CON1 */ 868 /* CDIV clk_core_dbg_div_con */ 869 /* CDIV aclk_core_div_con */ 870 CDIV(0, "hclk_bus_pre_c", "aclk_bus_pre", 0, 1, 8, 2), 871 CDIV(0, "pclk_bus_pre_c", "aclk_bus_pre", 0, 1, 12, 2), 872 873 /* CRU_CLKSEL_CON2 */ 874 /* CDIV test_div_con */ 875 /* CDIV func_24m_div_con */ 876 877 /* CRU_CLKSEL_CON3 */ 878 /* COMP ddr_div_cnt ddr_clk_pll_sel */ 879 880 /* CRU_CLKSEL_CON4 */ 881 COMP(0, "clk_otp_c", pll_src_cpll_gpll_xin24m_p, 0, 4, 0, 6, 6, 2), 882 /* COMP pd_ddr_div_con ddrpdclk_clk_pll_sel */ 883 884 /* CRU_CLKSEL_CON5 */ 885 COMP(0, "clk_efuse_c", pll_src_cpll_gpll_xin24m_p, 0, 5, 8, 5, 14, 2), 886 887 /* CRU_CLKSEL_CON6 */ 888 MUX(0, "clk_i2s0_mux", mux_i2s0_p, RK_CLK_MUX_REPARENT, 6, 8, 2), 889 COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0, 6, 0, 7, 15, 1), 890 891 /* CRU_CLKSEL_CON7 */ 892 FRACT(0, "clk_i2s0_frac_f", "clk_i2s0_div", 0, 7), 893 894 /* CRU_CLKSEL_CON8 */ 895 MUX(0, "clk_i2s1_mux", mux_i2s1_p, RK_CLK_MUX_REPARENT, 8, 8, 2), 896 COMP(0, "clk_i2s1_div_c", pll_src_cpll_gpll_p, 0, 8, 0, 7, 15, 1), 897 /* MUX i2s1_out_sel */ 898 899 /* CRU_CLKSEL_CON9 */ 900 FRACT(0, "clk_i2s1_frac_f", "clk_i2s1_div", 0, 9), 901 902 /* CRU_CLKSEL_CON10 */ 903 MUX(0, "clk_i2s2_mux", mux_i2s2_p, RK_CLK_MUX_REPARENT, 10, 8, 2), 904 COMP(0, "clk_i2s2_div_c", pll_src_cpll_gpll_p, 0, 10, 0, 7, 15, 1), 905 /* MUX i2s2_out_sel */ 906 907 /* CRU_CLKSEL_CON11 */ 908 FRACT(0, "clk_i2s2_frac_f", "clk_i2s2_div", 0, 11), 909 910 /* CRU_CLKSEL_CON12 */ 911 MUX(0, "clk_spdif_pll", pll_src_cpll_gpll_p, 0, 12, 15, 1), 912 MUX(SCLK_SPDIF, "clk_spdif", mux_spdif_p, 0, 12, 8, 2), 913 CDIV(0, "clk_spdif_div_c", "clk_spdif_pll", 0, 12, 0, 7), 914 915 /* CRU_CLKSEL_CON13 */ 916 FRACT(0, "clk_spdif_frac_f", "clk_spdif", 0, 13), 917 918 /* CRU_CLKSEL_CON14 */ 919 MUX(0, "clk_uart0_pll", pll_src_cpll_gpll_usb480m_p, 0, 14, 12, 2), 920 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, 0, 14, 8, 2), 921 CDIV(0, "clk_uart0_div_c", "clk_uart0_pll", 0, 14, 0, 7), 922 923 /* CRU_CLKSEL_CON15 */ 924 FRACT(0, "clk_uart0_frac_f", "clk_uart0_pll", 0, 15), 925 926 /* CRU_CLKSEL_CON16 */ 927 MUX(0, "clk_uart1_pll", pll_src_cpll_gpll_usb480m_p, 0, 16, 12, 2), 928 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, 0, 16, 8, 2), 929 CDIV(0, "clk_uart1_div_c", "clk_uart1_pll", 0, 16, 0, 7), 930 931 /* CRU_CLKSEL_CON17 */ 932 FRACT(0, "clk_uart1_frac_f", "clk_uart1_pll", 0, 17), 933 934 /* CRU_CLKSEL_CON18 */ 935 MUX(0, "clk_uart2_pll", pll_src_cpll_gpll_usb480m_p, 0, 18, 12, 2), 936 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, 0, 18, 8, 2), 937 CDIV(0, "clk_uart2_div_c", "clk_uart2_pll", 0, 18, 0, 7), 938 939 /* CRU_CLKSEL_CON19 */ 940 FRACT(0, "clk_uart2_frac_f", "clk_uart2_pll", 0, 19), 941 942 /* CRU_CLKSEL_CON20 */ 943 COMP(0, "clk_pdm_c", pll_src_cpll_gpll_apll_p, 0, 20, 8, 5, 14, 2), 944 COMP(0, "clk_crypto_c", pll_src_cpll_gpll_p, 0, 20, 0, 5, 7, 1), 945 946 /* CRU_CLKSEL_CON21 */ 947 COMP(0, "clk_tsp_c", pll_src_cpll_gpll_p, 0, 21, 8, 5, 15, 1), 948 949 /* CRU_CLKSEL_CON22 */ 950 CDIV(0, "clk_tsadc_c", "xin24m", 0, 22, 0, 10), 951 952 /* CRU_CLKSEL_CON23 */ 953 CDIV(0, "clk_saradc_c", "xin24m", 0, 23, 0, 10), 954 955 /* CRU_CLKSEL_CON24 */ 956 COMP(0, "clk_pwm_c", pll_src_cpll_gpll_p, 0, 24, 8, 7, 15, 1), 957 COMP(0, "clk_spi_c", pll_src_cpll_gpll_p, 0, 24, 0, 7, 7, 1), 958 959 /* CRU_CLKSEL_CON25 */ 960 COMP(0, "aclk_gmac_c", pll_src_cpll_gpll_p, 0, 35, 0, 5, 6, 2), 961 CDIV(0, "pclk_gmac_c", "pclk_gmac", 0, 25, 8, 3), 962 963 /* CRU_CLKSEL_CON26 */ 964 CDIV(0, "clk_mac2phy_out_c", "clk_mac2phy", 0, 26, 8, 2), 965 COMP(0, "clk_mac2phy_src_c", pll_src_cpll_gpll_p, 0, 26, 0, 5, 7, 1), 966 967 /* CRU_CLKSEL_CON27 */ 968 COMP(0, "clk_mac2io_src_c", pll_src_cpll_gpll_p, 0, 27, 0, 5, 7, 1), 969 COMP(0, "clk_mac2io_out_c", pll_src_cpll_gpll_p, 0, 27, 8, 5, 15, 1), 970 971 /* CRU_CLKSEL_CON28 */ 972 COMP(ACLK_PERI_PRE, "aclk_peri_pre", pll_src_cpll_gpll_hdmiphy_p, 0, 28, 0, 5, 6, 2), 973 974 /* CRU_CLKSEL_CON29 */ 975 CDIV(0, "pclk_peri_c", "aclk_peri_pre", 0, 29, 0, 2), 976 CDIV(0, "hclk_peri_c", "aclk_peri_pre", 0, 29, 4, 3), 977 978 /* CRU_CLKSEL_CON30 */ 979 COMP(0, "clk_sdmmc_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 30, 0, 8, 8, 2), 980 981 /* CRU_CLKSEL_CON31 */ 982 COMP(0, "clk_sdio_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 31, 0, 8, 8, 2), 983 984 /* CRU_CLKSEL_CON32 */ 985 COMP(0, "clk_emmc_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 32, 0, 8, 8, 2), 986 987 /* CRU_CLKSEL_CON33 */ 988 COMP(0, "clk_usb3otg_suspend_c", xin24m_rtc32k_p, 0, 33, 0, 10, 15, 1), 989 990 /* CRU_CLKSEL_CON34 */ 991 COMP(0, "clk_i2c0_c", pll_src_cpll_gpll_p, 0, 34, 0, 7, 7, 1), 992 COMP(0, "clk_i2c1_c", pll_src_cpll_gpll_p, 0, 34, 8, 7, 15, 1), 993 994 /* CRU_CLKSEL_CON35 */ 995 COMP(0, "clk_i2c2_c", pll_src_cpll_gpll_p, 0, 35, 0, 7, 7, 1), 996 COMP(0, "clk_i2c3_c", pll_src_cpll_gpll_p, 0, 35, 8, 7, 15, 1), 997 998 /* CRU_CLKSEL_CON36 */ 999 COMP(0, "aclk_rga_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 36, 8, 5, 14, 2), 1000 COMP(0, "sclk_rga_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 36, 0, 5, 6, 2), 1001 1002 /* CRU_CLKSEL_CON37 */ 1003 COMP(0, "aclk_vio_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 37, 0, 5, 6, 2), 1004 CDIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_vio_pre", 0, 37, 8, 5), 1005 1006 /* CRU_CLKSEL_CON38 */ 1007 COMP(0, "clk_rtc32k_c", pll_src_cpll_gpll_xin24m_p, 0, 38, 0, 14, 14, 2), 1008 1009 /* CRU_CLKSEL_CON39 */ 1010 COMP(0, "aclk_vop_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 39, 0, 5, 6, 2), 1011 1012 /* CRU_CLKSEL_CON40 */ 1013 COMP(0, "vop_dclk_src_c", pll_src_cpll_gpll_p, 0, 40, 8, 8, 0, 1), 1014 CDIV(DCLK_HDMIPHY, "hdmiphy_div", "vop_dclk_src", 0, 40, 3, 3), 1015 /* MUX vop_dclk_frac_sel */ 1016 MUX(DCLK_LCDC, "vop_dclk", mux_dclk_lcdc_p, 0, 40, 1, 1), 1017 1018 /* CRU_CLKSEL_CON41 */ 1019 /* FRACT dclk_vop_frac_div_con */ 1020 1021 /* CRU_CLKSEL_CON42 */ 1022 MUX(0, "clk_cif_pll", pll_src_cpll_gpll_p, 0, 42, 7, 1), 1023 COMP(0, "clk_cif_src_c", mux_cif_p, 0, 42, 0, 5, 5, 1), 1024 1025 /* CRU_CLKSEL_CON43 */ 1026 COMP(0, "clk_sdmmc_ext_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 43, 0, 8, 8, 2), 1027 1028 /* CRU_CLKSEL_CON44 */ 1029 COMP(0, "aclk_gpu_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 44, 0, 5, 6, 2), 1030 1031 /* CRU_CLKSEL_CON45 */ 1032 MUX(SCLK_REF_USB3OTG, "clk_ref_usb3otg", mux_ref_usb3otg_p, 0, 45, 8, 1), 1033 COMP(0, "clk_ref_usb3otg_src_c", pll_src_cpll_gpll_p, 0, 45, 0, 7, 7, 1), 1034 1035 /* CRU_CLKSEL_CON46 */ 1036 /* Unused */ 1037 1038 /* CRU_CLKSEL_CON47 */ 1039 /* Unused */ 1040 1041 /* CRU_CLKSEL_CON48 */ 1042 COMP(0, "sclk_cabac_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 48, 8, 5, 14, 2), 1043 COMP(0, "aclk_rkvdec_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 48, 0, 5, 6, 2), 1044 1045 /* CRU_CLKSEL_CON49 */ 1046 COMP(0, "sclk_vdec_core_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 49, 0, 5, 6, 2), 1047 1048 /* CRU_CLKSEL_CON50 */ 1049 COMP(0, "aclk_vpu_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 50, 0, 5, 6, 2), 1050 1051 /* CRU_CLKSEL_CON51 */ 1052 COMP(0, "sclk_venc_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 8, 5, 14, 2), 1053 COMP(0, "aclk_rkvenc_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 0, 5, 6, 2), 1054 1055 /* CRU_CLKSEL_CON52 */ 1056 COMP(0, "sclk_venc_dsp_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 8, 5, 14, 2), 1057 COMP(0, "sclk_wifi_c", pll_src_cpll_gpll_usb480m_p, 0, 51, 0, 6, 6, 2), 1058 1059 /* GRF_SOC_CON4 */ 1060 MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, 0, RK3328_GRF_SOC_CON4, 14, 1), 1061 1062 /* GRF_MAC_CON1 */ 1063 MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_p, 0, RK3328_GRF_MAC_CON1, 10, 1), 1064 1065 /* GRF_MAC_CON2 */ 1066 MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_p, 0, RK3328_GRF_MAC_CON2, 10, 1), 1067 1068 /* 1069 * This clock is controlled in the secure world 1070 */ 1071 FFACT(PCLK_WDT, "pclk_wdt", "pclk_bus", 1, 1), 1072 }; 1073 1074 static int 1075 rk3328_cru_probe(device_t dev) 1076 { 1077 1078 if (!ofw_bus_status_okay(dev)) 1079 return (ENXIO); 1080 1081 if (ofw_bus_is_compatible(dev, "rockchip,rk3328-cru")) { 1082 device_set_desc(dev, "Rockchip RK3328 Clock and Reset Unit"); 1083 return (BUS_PROBE_DEFAULT); 1084 } 1085 1086 return (ENXIO); 1087 } 1088 1089 static int 1090 rk3328_cru_attach(device_t dev) 1091 { 1092 struct rk_cru_softc *sc; 1093 1094 sc = device_get_softc(dev); 1095 sc->dev = dev; 1096 1097 sc->gates = rk3328_gates; 1098 sc->ngates = nitems(rk3328_gates); 1099 1100 sc->clks = rk3328_clks; 1101 sc->nclks = nitems(rk3328_clks); 1102 1103 sc->reset_offset = 0x300; 1104 sc->reset_num = 184; 1105 1106 return (rk_cru_attach(dev)); 1107 } 1108 1109 static device_method_t rk3328_cru_methods[] = { 1110 /* Device interface */ 1111 DEVMETHOD(device_probe, rk3328_cru_probe), 1112 DEVMETHOD(device_attach, rk3328_cru_attach), 1113 1114 DEVMETHOD_END 1115 }; 1116 1117 DEFINE_CLASS_1(rk3328_cru, rk3328_cru_driver, rk3328_cru_methods, 1118 sizeof(struct rk_cru_softc), rk_cru_driver); 1119 1120 EARLY_DRIVER_MODULE(rk3328_cru, simplebus, rk3328_cru_driver, 0, 0, 1121 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
Cache object: 7387d76d278596c3d3dcaefa9add280b
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