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sys/arm64/rockchip/clk/rk3568_cru.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/rman.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <machine/bus.h> 35 36 #include <dev/fdt/simplebus.h> 37 38 #include <dev/ofw/ofw_bus.h> 39 #include <dev/ofw/ofw_bus_subr.h> 40 41 #include <dev/extres/clk/clk_div.h> 42 #include <dev/extres/clk/clk_fixed.h> 43 #include <dev/extres/clk/clk_mux.h> 44 45 #include <arm64/rockchip/clk/rk_cru.h> 46 #include <contrib/device-tree/include/dt-bindings/clock/rk3568-cru.h> 47 48 49 #define RK3568_PLLSEL_CON(x) ((x) * 0x20) 50 #define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 51 #define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300) 52 #define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400) 53 54 #define PNAME(_name) static const char *_name[] 55 56 #define RK_PLLRATE(_hz, _ref, _fb, _post1, _post2, _dspd) \ 57 { \ 58 .freq = _hz, \ 59 .refdiv = _ref, \ 60 .fbdiv = _fb, \ 61 .postdiv1 = _post1, \ 62 .postdiv2 = _post2, \ 63 .dsmpd = _dspd, \ 64 } 65 66 /* PLL clock */ 67 #define RK_PLL(_id, _name, _pnames, _off, _shift) \ 68 { \ 69 .type = RK3328_CLK_PLL, \ 70 .clk.pll = &(struct rk_clk_pll_def) { \ 71 .clkdef.id = _id, \ 72 .clkdef.name = _name, \ 73 .clkdef.parent_names = _pnames, \ 74 .clkdef.parent_cnt = nitems(_pnames), \ 75 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 76 .base_offset = RK3568_PLLSEL_CON(_off), \ 77 .mode_reg = 0xc0, \ 78 .mode_shift = _shift, \ 79 .rates = rk3568_pll_rates, \ 80 }, \ 81 } 82 83 /* Clock for ARM core(s) */ 84 #define RK_ARMDIV(_id, _nm, _pn, _r, _off, _ds, _dw, _ms, _mw, _mp, _ap)\ 85 { \ 86 .type = RK_CLK_ARMCLK, \ 87 .clk.armclk = &(struct rk_clk_armclk_def) { \ 88 .clkdef.id = _id, \ 89 .clkdef.name = _nm, \ 90 .clkdef.parent_names = _pn, \ 91 .clkdef.parent_cnt = nitems(_pn), \ 92 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 93 .muxdiv_offset = RK3568_CLKSEL_CON(_off), \ 94 .mux_shift = _ms, \ 95 .mux_width = _mw, \ 96 .div_shift = _ds, \ 97 .div_width = _dw, \ 98 .main_parent = _mp, \ 99 .alt_parent = _ap, \ 100 .rates = _r, \ 101 .nrates = nitems(_r), \ 102 }, \ 103 } 104 105 /* Composite */ 106 #define RK_COMPOSITE(_id, _name, _pnames, _o, _ms, _mw, _ds, _dw, _go, _gw,_f)\ 107 { \ 108 .type = RK_CLK_COMPOSITE, \ 109 .clk.composite = &(struct rk_clk_composite_def) { \ 110 .clkdef.id = _id, \ 111 .clkdef.name = _name, \ 112 .clkdef.parent_names = _pnames, \ 113 .clkdef.parent_cnt = nitems(_pnames), \ 114 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 115 .muxdiv_offset = RK3568_CLKSEL_CON(_o), \ 116 .mux_shift = _ms, \ 117 .mux_width = _mw, \ 118 .div_shift = _ds, \ 119 .div_width = _dw, \ 120 .gate_offset = RK3568_CLKGATE_CON(_go), \ 121 .gate_shift = _gw, \ 122 .flags = RK_CLK_COMPOSITE_HAVE_MUX | \ 123 RK_CLK_COMPOSITE_HAVE_GATE | _f, \ 124 }, \ 125 } 126 127 /* Composite no mux */ 128 #define RK_COMPNOMUX(_id, _name, _pname, _o, _ds, _dw, _go, _gw, _f) \ 129 { \ 130 .type = RK_CLK_COMPOSITE, \ 131 .clk.composite = &(struct rk_clk_composite_def) { \ 132 .clkdef.id = _id, \ 133 .clkdef.name = _name, \ 134 .clkdef.parent_names = (const char *[]){_pname}, \ 135 .clkdef.parent_cnt = 1, \ 136 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 137 .muxdiv_offset = RK3568_CLKSEL_CON(_o), \ 138 .div_shift = _ds, \ 139 .div_width = _dw, \ 140 .gate_offset = RK3568_CLKGATE_CON(_go), \ 141 .gate_shift = _gw, \ 142 .flags = RK_CLK_COMPOSITE_HAVE_GATE | _f, \ 143 }, \ 144 } 145 146 /* Composite no div */ 147 #define RK_COMPNODIV(_id, _name, _pnames, _o, _ms, _mw, _go, _gw, _f) \ 148 { \ 149 .type = RK_CLK_COMPOSITE, \ 150 .clk.composite = &(struct rk_clk_composite_def) { \ 151 .clkdef.id = _id, \ 152 .clkdef.name = _name, \ 153 .clkdef.parent_names = _pnames, \ 154 .clkdef.parent_cnt = nitems(_pnames), \ 155 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 156 .muxdiv_offset = RK3568_CLKSEL_CON(_o), \ 157 .mux_shift = _ms, \ 158 .mux_width = _mw, \ 159 .gate_offset = RK3568_CLKGATE_CON(_go), \ 160 .gate_shift = _gw, \ 161 .flags = RK_CLK_COMPOSITE_HAVE_MUX | \ 162 RK_CLK_COMPOSITE_HAVE_GATE | _f, \ 163 }, \ 164 } 165 166 /* Composite div only */ 167 #define RK_COMPDIV(_id, _name, _pname, _o, _ds, _dw, _f) \ 168 { \ 169 .type = RK_CLK_COMPOSITE, \ 170 .clk.composite = &(struct rk_clk_composite_def) { \ 171 .clkdef.id = _id, \ 172 .clkdef.name = _name, \ 173 .clkdef.parent_names = (const char *[]){_pname}, \ 174 .clkdef.parent_cnt = 1, \ 175 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 176 .muxdiv_offset = RK3568_CLKSEL_CON(_o), \ 177 .div_shift = _ds, \ 178 .div_width = _dw, \ 179 .flags = _f, \ 180 }, \ 181 } 182 183 184 /* Fixed factor mux/div */ 185 #define RK_FACTOR(_id, _name, _pname, _mult, _div) \ 186 { \ 187 .type = RK_CLK_FIXED, \ 188 .clk.fixed = &(struct clk_fixed_def) { \ 189 .clkdef.id = _id, \ 190 .clkdef.name = _name, \ 191 .clkdef.parent_names = (const char *[]){_pname}, \ 192 .clkdef.parent_cnt = 1, \ 193 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 194 .mult = _mult, \ 195 .div = _div, \ 196 }, \ 197 } 198 199 /* Fractional */ 200 #define RK_FRACTION(_id, _name, _pname, _o, _go, _gw, _f) \ 201 { \ 202 .type = RK_CLK_FRACT, \ 203 .clk.fract = &(struct rk_clk_fract_def) { \ 204 .clkdef.id = _id, \ 205 .clkdef.name = _name, \ 206 .clkdef.parent_names = (const char *[]){_pname}, \ 207 .clkdef.parent_cnt = 1, \ 208 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 209 .offset = RK3568_CLKSEL_CON(_o), \ 210 .gate_offset = RK3568_CLKGATE_CON(_go), \ 211 .gate_shift = _gw, \ 212 .flags = RK_CLK_FRACT_HAVE_GATE | _f, \ 213 }, \ 214 } 215 216 /* Multiplexer */ 217 #define RK_MUX(_id, _name, _pnames, _o, _ms, _mw, _f) \ 218 { \ 219 .type = RK_CLK_MUX, \ 220 .clk.mux = &(struct rk_clk_mux_def) { \ 221 .clkdef.id = _id, \ 222 .clkdef.name = _name, \ 223 .clkdef.parent_names = _pnames, \ 224 .clkdef.parent_cnt = nitems(_pnames), \ 225 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 226 .offset = RK3568_CLKSEL_CON(_o), \ 227 .shift = _ms, \ 228 .width = _mw, \ 229 .mux_flags = _f, \ 230 }, \ 231 } 232 233 #define RK_GATE(_id, _name, _pname, _o, _s) \ 234 { \ 235 .id = _id, \ 236 .name = _name, \ 237 .parent_name = _pname, \ 238 .offset = RK3568_CLKGATE_CON(_o), \ 239 .shift = _s, \ 240 } 241 242 struct rk_clk_pll_rate rk3568_pll_rates[] = { 243 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd */ 244 RK_PLLRATE(2208000000, 1, 92, 1, 1, 1), 245 RK_PLLRATE(2184000000, 1, 91, 1, 1, 1), 246 RK_PLLRATE(2160000000, 1, 90, 1, 1, 1), 247 RK_PLLRATE(2088000000, 1, 87, 1, 1, 1), 248 RK_PLLRATE(2064000000, 1, 86, 1, 1, 1), 249 RK_PLLRATE(2040000000, 1, 85, 1, 1, 1), 250 RK_PLLRATE(2016000000, 1, 84, 1, 1, 1), 251 RK_PLLRATE(1992000000, 1, 83, 1, 1, 1), 252 RK_PLLRATE(1920000000, 1, 80, 1, 1, 1), 253 RK_PLLRATE(1896000000, 1, 79, 1, 1, 1), 254 RK_PLLRATE(1800000000, 1, 75, 1, 1, 1), 255 RK_PLLRATE(1704000000, 1, 71, 1, 1, 1), 256 RK_PLLRATE(1608000000, 1, 67, 1, 1, 1), 257 RK_PLLRATE(1600000000, 3, 200, 1, 1, 1), 258 RK_PLLRATE(1584000000, 1, 132, 2, 1, 1), 259 RK_PLLRATE(1560000000, 1, 130, 2, 1, 1), 260 RK_PLLRATE(1536000000, 1, 128, 2, 1, 1), 261 RK_PLLRATE(1512000000, 1, 126, 2, 1, 1), 262 RK_PLLRATE(1488000000, 1, 124, 2, 1, 1), 263 RK_PLLRATE(1464000000, 1, 122, 2, 1, 1), 264 RK_PLLRATE(1440000000, 1, 120, 2, 1, 1), 265 RK_PLLRATE(1416000000, 1, 118, 2, 1, 1), 266 RK_PLLRATE(1400000000, 3, 350, 2, 1, 1), 267 RK_PLLRATE(1392000000, 1, 116, 2, 1, 1), 268 RK_PLLRATE(1368000000, 1, 114, 2, 1, 1), 269 RK_PLLRATE(1344000000, 1, 112, 2, 1, 1), 270 RK_PLLRATE(1320000000, 1, 110, 2, 1, 1), 271 RK_PLLRATE(1296000000, 1, 108, 2, 1, 1), 272 RK_PLLRATE(1272000000, 1, 106, 2, 1, 1), 273 RK_PLLRATE(1248000000, 1, 104, 2, 1, 1), 274 RK_PLLRATE(1200000000, 1, 100, 2, 1, 1), 275 RK_PLLRATE(1188000000, 1, 99, 2, 1, 1), 276 RK_PLLRATE(1104000000, 1, 92, 2, 1, 1), 277 RK_PLLRATE(1100000000, 3, 275, 2, 1, 1), 278 RK_PLLRATE(1008000000, 1, 84, 2, 1, 1), 279 RK_PLLRATE(1000000000, 3, 250, 2, 1, 1), 280 RK_PLLRATE(912000000, 1, 76, 2, 1, 1), 281 RK_PLLRATE(816000000, 1, 68, 2, 1, 1), 282 RK_PLLRATE(800000000, 3, 200, 2, 1, 1), 283 RK_PLLRATE(700000000, 3, 350, 4, 1, 1), 284 RK_PLLRATE(696000000, 1, 116, 4, 1, 1), 285 RK_PLLRATE(600000000, 1, 100, 4, 1, 1), 286 RK_PLLRATE(594000000, 1, 99, 4, 1, 1), 287 RK_PLLRATE(500000000, 1, 125, 6, 1, 1), 288 RK_PLLRATE(408000000, 1, 68, 2, 2, 1), 289 RK_PLLRATE(312000000, 1, 78, 6, 1, 1), 290 RK_PLLRATE(216000000, 1, 72, 4, 2, 1), 291 RK_PLLRATE(200000000, 1, 100, 3, 4, 1), 292 RK_PLLRATE(148500000, 1, 99, 4, 4, 1), 293 RK_PLLRATE(100000000, 1, 150, 6, 6, 1), 294 RK_PLLRATE(96000000, 1, 96, 6, 4, 1), 295 RK_PLLRATE(74250000, 2, 99, 4, 4, 1), 296 {}, 297 }; 298 299 static struct rk_clk_armclk_rates rk3568_armclk_rates[] = { 300 {2208000000, 1}, 301 {2160000000, 1}, 302 {2064000000, 1}, 303 {2016000000, 1}, 304 {1992000000, 1}, 305 {1800000000, 1}, 306 {1704000000, 1}, 307 {1608000000, 1}, 308 {1512000000, 1}, 309 {1488000000, 1}, 310 {1416000000, 1}, 311 {1200000000, 1}, 312 {1104000000, 1}, 313 {1008000000, 1}, 314 { 816000000, 1}, 315 { 696000000, 1}, 316 { 600000000, 1}, 317 { 408000000, 1}, 318 { 312000000, 1}, 319 { 216000000, 1}, 320 { 96000000, 1}, 321 {}, 322 }; 323 324 /* Parent clock defines */ 325 PNAME(mux_pll_p) = { "xin24m" }; 326 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" }; 327 PNAME(mux_armclk_p) = { "apll", "gpll" }; 328 PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", 329 "i2s0_mclkin", "xin_osc0_half" }; 330 PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", 331 "i2s0_mclkin", "xin_osc0_half" }; 332 PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", 333 "i2s1_mclkin", "xin_osc0_half" }; 334 PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", 335 "i2s1_mclkin", "xin_osc0_half" }; 336 PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", 337 "i2s2_mclkin", "xin_osc0_half"}; 338 PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", 339 "i2s3_mclkin", "xin_osc0_half" }; 340 PNAME(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", 341 "i2s3_mclkin", "xin_osc0_half" }; 342 PNAME(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" }; 343 PNAME(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" }; 344 PNAME(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; 345 PNAME(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; 346 PNAME(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; 347 PNAME(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; 348 PNAME(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; 349 PNAME(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; 350 PNAME(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; 351 PNAME(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; 352 PNAME(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; 353 PNAME(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" }; 354 PNAME(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" }; 355 PNAME(npll_gpll_p) = { "npll", "gpll" }; 356 PNAME(cpll_gpll_p) = { "cpll", "gpll" }; 357 PNAME(gpll_cpll_p) = { "gpll", "cpll" }; 358 PNAME(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" }; 359 PNAME(apll_gpll_npll_p) = { "apll", "gpll", "npll" }; 360 PNAME(sclk_core_pre_p) = { "sclk_core_src", "npll" }; 361 PNAME(gpll150_gpll100_gpll75_xin24m_p) = { "gpll_150m", "gpll_100m", "gpll_75m", 362 "xin24m" }; 363 PNAME(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" }; 364 PNAME(clk_npu_pre_ndft_p) = { "clk_npu_src", "dummy"}; 365 PNAME(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" }; 366 PNAME(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" }; 367 PNAME(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" }; 368 PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", 369 "gpll_100m", "xin24m" }; 370 PNAME(gpll100_gpll75_gpll50_p) = { "gpll_100m", "gpll_75m", "cpll_50m" }; 371 PNAME(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" }; 372 PNAME(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" }; 373 PNAME(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" }; 374 PNAME(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" }; 375 PNAME(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" }; 376 PNAME(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" }; 377 PNAME(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" }; 378 PNAME(mclk_pdm_p) = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" }; 379 PNAME(clk_i2c_p) = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" }; 380 PNAME(gpll200_gpll150_gpll100_p) = { "gpll_200m", "gpll_150m", "gpll_100m" }; 381 PNAME(gpll300_gpll200_gpll100_p) = { "gpll_300m", "gpll_200m", "gpll_100m" }; 382 PNAME(clk_nandc_p) = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" }; 383 PNAME(sclk_sfc_p) = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", 384 "cpll_125m", "gpll_150m" }; 385 PNAME(gpll200_gpll150_cpll125_p) = { "gpll_200m", "gpll_150m", "cpll_125m" }; 386 PNAME(cclk_emmc_p) = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", 387 "cpll_50m", "clk_osc0_div_375k" }; 388 PNAME(aclk_pipe_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" }; 389 PNAME(gpll200_cpll125_p) = { "gpll_200m", "cpll_125m" }; 390 PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", 391 "gpll_100m", "xin24m" }; 392 PNAME(clk_sdmmc_p) = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", 393 "cpll_50m", "clk_osc0_div_750k" }; 394 PNAME(cpll125_cpll50_cpll25_xin24m_p) = { "cpll_125m", "cpll_50m", "cpll_25m", 395 "xin24m" }; 396 PNAME(clk_gmac_ptp_p) = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" }; 397 PNAME(cpll333_gpll300_gpll200_p) = { "cpll_333m", "gpll_300m", "gpll_200m" }; 398 PNAME(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" }; 399 PNAME(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" }; 400 PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", 401 "gpll_100m", "xin24m" }; 402 PNAME(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" }; 403 PNAME(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" }; 404 PNAME(gpll400_cpll333_gpll200_p) = { "gpll_400m", "cpll_333m", "gpll_200m" }; 405 PNAME(gpll100_gpll75_cpll50_xin24m_p) = { "gpll_100m", "gpll_75m", "cpll_50m", 406 "xin24m" }; 407 PNAME(xin24m_gpll100_cpll100_p) = { "xin24m", "gpll_100m", "cpll_100m" }; 408 PNAME(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" }; 409 PNAME(gpll100_xin24m_cpll100_p) = { "gpll_100m", "xin24m", "cpll_100m" }; 410 PNAME(gpll200_xin24m_cpll100_p) = { "gpll_200m", "xin24m", "cpll_100m" }; 411 PNAME(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; 412 PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", 413 "gpll_300m", "xin24m" }; 414 PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", 415 "gpll_200m", "xin24m" }; 416 PNAME(xin24m_cpll100_p) = { "xin24m", "cpll_100m" }; 417 PNAME(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" }; 418 PNAME(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", 419 "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" }; 420 PNAME(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" }; 421 PNAME(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", 422 "clk_gmac0_xpcs_mii" }; 423 PNAME(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" }; 424 PNAME(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", 425 "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" }; 426 PNAME(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" }; 427 PNAME(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", 428 "clk_gmac1_xpcs_mii" }; 429 PNAME(clk_mac_2top_p) = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" }; 430 PNAME(aclk_rkvdec_pre_p) = { "gpll", "cpll" }; 431 PNAME(clk_rkvdec_core_p) = { "gpll", "cpll", "npll", "vpll" }; 432 433 /* CLOCKS */ 434 static struct rk_clk rk3568_clks[] = { 435 /* External clocks */ 436 LINK("xin24m"), 437 LINK("clk_rtc_32k"), 438 LINK("usb480m_phy"), 439 LINK("mpll"), // SOS SCRU 440 LINK("i2s0_mclkin"), 441 LINK("i2s1_mclkin"), 442 LINK("i2s2_mclkin"), 443 LINK("i2s3_mclkin"), 444 LINK("gpu_pvtpll_out"), 445 LINK("npu_pvtpll_out"), 446 LINK("gmac0_clkin"), 447 LINK("gmac1_clkin"), 448 LINK("clk_gmac0_xpcs_mii"), 449 LINK("clk_gmac1_xpcs_mii"), 450 LINK("dummy"), 451 452 /* PLL's */ 453 RK_PLL(PLL_APLL, "apll", mux_pll_p, 0, 0), 454 RK_PLL(PLL_DPLL, "dpll", mux_pll_p, 1, 2), 455 RK_PLL(PLL_GPLL, "gpll", mux_pll_p, 2, 6), 456 RK_PLL(PLL_CPLL, "cpll", mux_pll_p, 3, 4), 457 RK_PLL(PLL_NPLL, "npll", mux_pll_p, 4, 10), 458 RK_PLL(PLL_VPLL, "vpll", mux_pll_p, 5, 12), 459 RK_ARMDIV(ARMCLK, "armclk", mux_armclk_p, rk3568_armclk_rates, 0, 0, 5, 460 6, 1, 0, 1), 461 RK_FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 1, 2), 462 RK_FACTOR(0, "xin_osc0_half", "xin24m", 1, 2), 463 RK_MUX(USB480M, "usb480m", mux_usb480m_p, -16, 14, 2, 0), 464 465 /* Clocks */ 466 RK_COMPNOMUX(0, "gpll_400m", "gpll", 75, 0, 5, 35, 0, 0), 467 RK_COMPNOMUX(0, "gpll_300m", "gpll", 75, 8, 5, 35, 1, 0), 468 RK_COMPNOMUX(0, "gpll_200m", "gpll", 76, 0, 5, 35, 2, 0), 469 RK_COMPNOMUX(0, "gpll_150m", "gpll", 76, 8, 5, 35, 3, 0), 470 RK_COMPNOMUX(0, "gpll_100m", "gpll", 77, 0, 5, 35, 4, 0), 471 RK_COMPNOMUX(0, "gpll_75m", "gpll", 77, 8, 5, 35, 5, 0), 472 RK_COMPNOMUX(0, "gpll_20m", "gpll", 78, 0, 6, 35, 6, 0), 473 RK_COMPNOMUX(CPLL_500M, "cpll_500m", "cpll", 78, 8, 5, 35, 7, 0), 474 RK_COMPNOMUX(CPLL_333M, "cpll_333m", "cpll", 79, 0, 5, 35, 8, 0), 475 RK_COMPNOMUX(CPLL_250M, "cpll_250m", "cpll", 79, 8, 5, 35, 9, 0), 476 RK_COMPNOMUX(CPLL_125M, "cpll_125m", "cpll", 80, 0, 5, 35, 10, 0), 477 RK_COMPNOMUX(CPLL_100M, "cpll_100m", "cpll", 82, 0, 5, 35, 11, 0), 478 RK_COMPNOMUX(CPLL_62P5M, "cpll_62p5", "cpll", 80, 8, 5, 35, 12, 0), 479 RK_COMPNOMUX(CPLL_50M, "cpll_50m", "cpll", 81, 0, 5, 35, 13, 0), 480 RK_COMPNOMUX(CPLL_25M, "cpll_25m", "cpll", 81, 8, 6, 35, 14, 0), 481 RK_COMPNOMUX(0, "clk_osc0_div_750k", "xin24m", 82, 8, 6, 35, 15, 0), 482 RK_COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, 2, 8, 2, 0, 4, 0, 483 5, 0), 484 RK_COMPNODIV(0, "sclk_core", sclk_core_pre_p, 2, 15, 1, 0, 7, 0), 485 RK_COMPNOMUX(0, "atclk_core", "armclk", 3, 0, 5, 0, 8, 0), 486 RK_COMPNOMUX(0, "gicclk_core", "armclk", 3, 8, 5, 0, 9, 0), 487 RK_COMPNOMUX(0, "pclk_core_pre", "armclk", 4, 0, 5, 0, 10, 0), 488 RK_COMPNOMUX(0, "periphclk_core_pre", "armclk", 4, 8, 5, 0, 11, 0), 489 RK_COMPNOMUX(0, "tsclk_core", "periphclk_core_pre", 5, 0, 4, 0, 14, 0), 490 RK_COMPNOMUX(0, "cntclk_core", "periphclk_core_pre", 5, 4, 4, 0, 15, 0), 491 RK_COMPNOMUX(0, "aclk_core", "sclk_core", 5, 8, 5, 1, 0, 0), 492 RK_COMPNODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", 493 gpll150_gpll100_gpll75_xin24m_p, 5, 14, 2, 1, 2, 0), 494 RK_COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 6, 6, 2, 495 0, 4, 2, 0, 0), 496 RK_MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, 6, 11, 497 1, 0), 498 RK_COMPDIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 6, 8, 2, 0), 499 RK_COMPDIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 6, 12, 4,0), 500 RK_COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 7, 6, 1, 0, 4, 3, 501 0, 0), 502 RK_MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, 7, 8, 503 1, 0), 504 RK_MUX(CLK_NPU, "clk_npu", clk_npu_p, 7, 15, 1, 0), 505 RK_COMPNOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 8, 0, 4, 3, 2, 0), 506 RK_COMPNOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 8, 4, 4, 3, 3, 0), 507 RK_COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, 9, 508 6, 2, 0, 5, 4, 0, 0), 509 RK_MUX(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, 9, 15, 1, 510 RK_CLK_COMPOSITE_GRF), 511 RK_COMPNOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", 10, 0, 2, 4, 2, 0), 512 RK_COMPNODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", 513 gpll200_gpll150_gpll100_xin24m_p, 10, 8, 2, 5, 0, 0), 514 RK_COMPNODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", 515 gpll150_gpll100_gpll75_xin24m_p, 10, 10, 2, 5, 1, 0), 516 RK_COMPNODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", 517 gpll100_gpll75_gpll50_p, 10, 12, 2, 5, 9, 0), 518 RK_COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", 519 gpll_cpll_npll_p, 11, 8, 2, 0, 7, 6, 0, 0), 520 RK_MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, 11, 10, 521 2, 0), 522 RK_FRACTION(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", 523 "clk_i2s0_8ch_tx_src", 12, 6, 1, 0), 524 RK_COMPNODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, 11, 525 15, 1, 6, 3, 0), 526 RK_COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", 527 gpll_cpll_npll_p, 13, 8, 2, 0, 7, 6, 4, 0), 528 RK_MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, 13, 10, 529 2, 0), 530 RK_FRACTION(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", 531 "clk_i2s0_8ch_rx_src", 14, 6, 5, 0), 532 RK_COMPNODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, 13, 533 15, 1, 6, 7, 0), 534 RK_COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", 535 gpll_cpll_npll_p, 15, 8, 2, 0, 7, 6, 8, 0), 536 RK_MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, 15, 10, 537 2, 0), 538 RK_FRACTION(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", 539 "clk_i2s1_8ch_tx_src", 16, 6, 9, 0), 540 RK_COMPNODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, 15, 541 15, 1, 6, 11, 0), 542 RK_COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", 543 gpll_cpll_npll_p, 17, 8, 2, 0, 7, 6, 12, 0), 544 RK_MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, 17, 10, 545 2, 0), 546 RK_FRACTION(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", 547 "clk_i2s1_8ch_rx_src", 18, 6, 13, 0), 548 RK_COMPNODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, 17, 549 15, 1, 6, 15, 0), 550 RK_COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 19, 551 8, 2, 0, 7, 7, 0, 0), 552 RK_MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, 19, 10, 2, 0), 553 RK_FRACTION(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", 554 20, 7, 1, 0), 555 RK_COMPNODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, 19, 15, 1, 7, 556 3, 0), 557 RK_COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", 558 gpll_cpll_npll_p, 21, 8, 2, 0, 7, 7, 4, 0), 559 RK_MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, 21, 10, 560 2, 0), 561 RK_FRACTION(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", 562 "clk_i2s3_2ch_tx_src", 22, 7, 5, 0), 563 RK_COMPNODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, 21, 564 15, 1, 7, 7, 0), 565 RK_COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", 566 gpll_cpll_npll_p, 83, 8, 2, 0, 7, 7, 8, 0), 567 RK_MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, 83, 10, 568 2, 0), 569 RK_FRACTION(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", 570 "clk_i2s3_2ch_rx_src", 84, 7, 9, 0), 571 RK_COMPNODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, 83, 572 15, 1, 7, 11, 0), 573 RK_COMPNODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 23, 8, 2, 5, 15, 0), 574 RK_COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 23, 575 14, 1, 0, 7, 7, 14, 0), 576 RK_MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, 23, 15, 1,0), 577 RK_FRACTION(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", 578 "mclk_spdif_8ch_src", 24, 7, 15, 0), 579 RK_COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 25, 14, 1, 580 0, 6, 8, 1, 0), 581 RK_MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, 25, 15, 1, 0), 582 RK_FRACTION(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", 26, 583 8, 2, 0), 584 RK_COMPNODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 23, 10, 2, 585 8, 4, 0), 586 RK_COMPNODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", 587 gpll200_gpll150_gpll100_xin24m_p, 27, 0, 2, 8, 7, 0), 588 RK_COMPNODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", 589 gpll150_gpll100_gpll75_xin24m_p, 27, 2, 2, 8, 8, 0), 590 RK_COMPNODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", 591 gpll200_gpll150_gpll100_p, 27, 4, 2, 8, 13, 0), 592 RK_COMPNODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", 593 gpll300_gpll200_gpll100_p, 27, 6, 2, 8, 14, 0), 594 RK_COMPNODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 28, 0, 2, 9, 1, 0), 595 RK_COMPNODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 28, 4, 3, 9, 4, 0), 596 RK_COMPNODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 28, 8, 597 2, 9, 7, 0), 598 RK_COMPNODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 28, 12, 3, 9, 8, 0), 599 RK_COMPNODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 29, 0, 2, 10, 0, 0), 600 RK_COMPNOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 29, 4, 4, 10, 1, 0), 601 RK_COMPNODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 602 29, 8, 1, 10, 10, 0), 603 RK_COMPNODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 604 29, 9, 1, 10, 14, 0), 605 RK_COMPNODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 29, 13, 1, 606 10, 4, 0), 607 RK_COMPNODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 30, 608 0, 2, 14, 8, 0), 609 RK_COMPNODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 30, 610 2, 2, 14, 9, 0), 611 RK_COMPNOMUX(PCLK_PHP, "pclk_php", "aclk_php", 30, 4, 4, 14, 10, 0), 612 RK_COMPNODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 30, 8, 3, 15, 1, 0), 613 RK_COMPNODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 30, 12, 3, 15, 3,0), 614 RK_COMPNODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 31, 8, 2, 615 15, 7, 0), 616 RK_COMPNODIV(CLK_MAC0_OUT, "clk_mac0_out", 617 cpll125_cpll50_cpll25_xin24m_p, 31, 14, 2, 15, 8, 0), 618 RK_COMPNODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 31, 619 12, 2, 15, 4, 0), 620 RK_MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, 31, 2, 1, 0), 621 RK_FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 1, 5), 622 RK_FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 1, 50), 623 RK_FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 1, 2), 624 RK_FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 1, 20), 625 RK_MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", 626 mux_gmac0_rgmii_speed_p, 31, 4, 2, 0), 627 RK_MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", 628 mux_gmac0_rmii_speed_p, 31, 3, 1, 0), 629 RK_MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, 31, 0, 630 2, 0), 631 RK_COMPNODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 32, 632 0, 2, 16, 0, 0), 633 RK_COMPNODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 32, 634 2, 2, 16, 1, 0), 635 RK_COMPNOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 32, 4, 4, 16, 2, 0), 636 RK_COMPNODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 32, 8, 3, 17, 1, 0), 637 RK_COMPNODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 33, 8, 2, 638 17, 5, 0), 639 RK_COMPNODIV(CLK_MAC1_OUT, "clk_mac1_out", 640 cpll125_cpll50_cpll25_xin24m_p, 33, 14, 2, 17, 6, 0), 641 RK_COMPNODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 33, 642 12, 2, 17, 2, 0), 643 RK_MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, 33, 2, 1, 0), 644 RK_FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 1, 5), 645 RK_FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 1, 50), 646 RK_FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 1, 2), 647 RK_FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 1, 20), 648 RK_MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", 649 mux_gmac1_rgmii_speed_p, 33, 4, 2, 0), 650 RK_MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", 651 mux_gmac1_rmii_speed_p, 33, 3, 1, 0), 652 RK_MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, 33, 0, 653 2, 0), 654 RK_COMPNODIV(ACLK_PERIMID, "aclk_perimid", 655 gpll300_gpll200_gpll100_xin24m_p, 10, 4, 2, 14, 0, 0), 656 RK_COMPNODIV(HCLK_PERIMID, "hclk_perimid", 657 gpll150_gpll100_gpll75_xin24m_p, 10, 6, 2, 14, 1, 0), 658 RK_COMPNODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 34, 659 0, 2, 18, 0, 0), 660 RK_COMPNOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 34, 4, 4, 18, 1, 0), 661 RK_COMPNOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 34, 8, 4, 18, 2, 0), 662 RK_COMPNODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 34, 663 14, 2, 18, 11, 0), 664 RK_COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 35, 6, 2, 0, 5, 19, 665 2, 0), 666 RK_COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 35, 14, 667 2, 8, 6, 19, 8, 0), 668 RK_COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 36, 6, 669 2, 0, 6, 19, 9, 0), 670 RK_COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 36, 671 14, 2, 8, 6, 19, 10, 0), 672 RK_COMPNODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 37, 673 0, 2, 20, 0, 0), 674 RK_COMPNOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 37, 8, 4, 20, 1, 0), 675 RK_COMPNOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 37, 12, 4, 20, 2, 0), 676 RK_COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 38, 6, 677 2, 0, 5, 20, 6, 0), 678 RK_COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, 39, 10, 2, 679 0, 8, 20, 10, 0), 680 RK_COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, 40, 10, 2, 681 0, 8, 20, 11, 0), 682 RK_COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 41, 10, 2, 683 0, 8, 20, 12, 0), 684 RK_COMPNODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 685 38, 8, 2, 21, 9, 0), 686 RK_COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 42, 7, 1, 0, 5, 687 22, 0, 0), 688 RK_COMPNOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 42, 8, 4, 22, 689 1, 0), 690 RK_COMPNODIV(ACLK_RGA_PRE, "aclk_rga_pre", 691 gpll300_cpll250_gpll100_xin24m_p, 43, 0, 2, 23, 0, 0), 692 RK_COMPNOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 43, 8, 4, 23, 693 1, 0), 694 RK_COMPNOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 43, 12, 4, 695 22, 12, 0), 696 RK_COMPNODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 697 43, 2, 2, 23, 6, 0), 698 RK_COMPNODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 699 43, 4, 2, 23, 9, 0), 700 RK_COMPNODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 43, 6, 2, 701 23, 11, 0), 702 RK_COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 44, 703 6, 2, 0, 5, 24, 0, 0), 704 RK_COMPNOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 44, 705 8, 4, 24, 1, 0), 706 RK_COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 707 45, 14, 2, 0, 5, 24, 8, 0), 708 RK_COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, 47, 709 7, 1, 0, 5, 25, 0, 0), 710 RK_COMPNOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 47, 711 8, 4, 25, 1, 0), 712 RK_COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 48, 713 6, 2, 0, 5, 25, 6, 0), 714 RK_COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, 49, 715 14, 2, 8, 5, 25, 7, 0), 716 RK_COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", 717 gpll_cpll_npll_vpll_p, 49, 6, 2, 0, 5, 25, 8, 0), 718 RK_COMPNODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 50, 719 0, 2, 26, 0, 0), 720 RK_COMPNODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 50, 721 4, 2, 26, 1, 0), 722 RK_COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 723 51, 4, 2, 0, 3, 26, 5, 0), 724 RK_COMPNOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 51, 8, 7, 26, 725 6, 0), 726 RK_COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 52, 8, 727 2, 0, 7, 27, 13, 0), 728 RK_FRACTION(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", 53, 27, 729 14, 0), 730 RK_MUX(0, "sclk_uart1_mux", sclk_uart1_p, 52, 12, 2, 0), 731 RK_COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 54, 8, 732 2, 0, 7, 28, 1, 0), 733 RK_FRACTION(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", 55, 28, 734 2, 0), 735 RK_MUX(0, "sclk_uart2_mux", sclk_uart2_p, 54, 12, 2, 0), 736 RK_COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 56, 8, 737 2, 0, 7, 28, 5, 0), 738 RK_FRACTION(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", 57, 28, 739 6, 0), 740 RK_MUX(0, "sclk_uart3_mux", sclk_uart3_p, 56, 12, 2, 0), 741 RK_COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 58, 8, 742 2, 0, 7, 28, 9, 0), 743 RK_FRACTION(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", 59, 28, 744 10, 0), 745 RK_MUX(0, "sclk_uart4_mux", sclk_uart4_p, 58, 12, 2, 0), 746 RK_COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 60, 8, 747 2, 0, 7, 28, 13, 0), 748 RK_FRACTION(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", 61, 28, 749 14, 0), 750 RK_MUX(0, "sclk_uart5_mux", sclk_uart5_p, 60, 12, 2, 0), 751 RK_COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 62, 8, 752 2, 0, 7, 29, 1, 0), 753 RK_FRACTION(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", 63, 29, 754 2, 0), 755 RK_MUX(0, "sclk_uart6_mux", sclk_uart6_p, 62, 12, 2, 0), 756 RK_COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 64, 8, 757 2, 0, 7, 29, 5, 0), 758 RK_FRACTION(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", 65, 29, 759 6, 0), 760 RK_MUX(0, "sclk_uart7_mux", sclk_uart7_p, 64, 12, 2, 0), 761 RK_COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 66, 8, 762 2, 0, 7, 29, 9, 0), 763 RK_FRACTION(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", 67, 29, 764 10, 0), 765 RK_MUX(0, "sclk_uart8_mux", sclk_uart8_p, 66, 12, 2, 0), 766 RK_COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 68, 8, 767 2, 0, 7, 29, 13, 0), 768 RK_FRACTION(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", 69, 29, 769 14, 0), 770 RK_MUX(0, "sclk_uart9_mux", sclk_uart9_p, 68, 12, 2, 0), 771 RK_COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 70, 7, 1, 0, 5, 27, 772 6, 0), 773 RK_COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 70, 15, 1, 8, 5, 27, 774 8, 0), 775 RK_COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 71, 7, 1, 0, 5, 27, 776 10, 0), 777 RK_COMPNODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 71, 8, 2, 32, 10, 0), 778 RK_COMPNODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 72, 0, 1, 779 30, 11, 0), 780 RK_COMPNODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 72, 2, 1, 781 30, 13, 0), 782 RK_COMPNODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 72, 4, 1, 783 30, 15, 0), 784 RK_COMPNODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 72, 6, 1, 785 31, 1, 0), 786 RK_COMPNODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 72, 8, 1, 787 31, 11, 0), 788 RK_COMPNODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 72, 10, 1, 789 31, 14, 0), 790 RK_COMPNODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 72, 12, 1, 791 32, 1, 0), 792 RK_COMPNODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 72, 14, 1, 32, 793 11, 0), 794 RK_COMPNODIV(ACLK_TOP_HIGH, "aclk_top_high", 795 cpll500_gpll400_gpll300_xin24m_p, 73, 0, 2, 33, 0, 0), 796 RK_COMPNODIV(ACLK_TOP_LOW, "aclk_top_low", 797 gpll400_gpll300_gpll200_xin24m_p, 73, 4, 2, 33, 1, 0), 798 RK_COMPNODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 73, 799 8, 2, 33, 2, 0), 800 RK_COMPNODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 73, 801 12, 2, 33, 3, 0), 802 RK_COMPNODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 73, 15, 1, 803 33, 9, 0), 804 }; 805 806 /* GATES */ 807 static struct rk_cru_gate rk3568_gates[] = { 808 RK_GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 1, 10), 809 RK_GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 1, 11), 810 RK_GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", 1, 12), 811 RK_GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 1, 9), 812 RK_GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 2, 3), 813 RK_GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 2, 6), 814 RK_GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 2, 7), 815 RK_GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 2, 8), 816 RK_GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", 2, 9), 817 RK_GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 3, 4), 818 RK_GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 3, 7), 819 RK_GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 3, 8), 820 RK_GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 3, 9), 821 RK_GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 3, 10), 822 RK_GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 823 3, 11), 824 RK_GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", 3, 12), 825 RK_GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", 4, 15), 826 RK_GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 5, 8), 827 RK_GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", 5, 4), 828 RK_GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", 5, 7), 829 RK_GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 5, 10), 830 RK_GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 5, 11), 831 RK_GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 5, 12), 832 RK_GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 5, 13), 833 RK_GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 6, 2), 834 RK_GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 6, 6), 835 RK_GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 6, 10), 836 RK_GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 6, 14), 837 RK_GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 7, 2), 838 RK_GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 7, 6), 839 RK_GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 7, 10), 840 RK_GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 5, 14), 841 RK_GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 7, 12), 842 RK_GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 7, 13), 843 RK_GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 8, 0), 844 RK_GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 8, 3), 845 RK_GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 8, 5), 846 RK_GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 8, 6), 847 RK_GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 8, 11), 848 RK_GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 8, 12), 849 RK_GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 850 8, 15), 851 RK_GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", 9, 10), 852 RK_GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", 9, 11), 853 RK_GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 26, 9), 854 RK_GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 26, 10), 855 RK_GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 26, 11), 856 RK_GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 9, 0), 857 RK_GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 9, 2), 858 RK_GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 9, 3), 859 RK_GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 9, 5), 860 RK_GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 9, 6), 861 RK_GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 9, 9), 862 RK_GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 12, 0), 863 RK_GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 12, 1), 864 RK_GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 12, 2), 865 RK_GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 12, 3), 866 RK_GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 12, 4), 867 RK_GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 12, 8), 868 RK_GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 12, 9), 869 RK_GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 12, 10), 870 RK_GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 12, 11), 871 RK_GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 872 12, 12), 873 RK_GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 13, 0), 874 RK_GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 13, 1), 875 RK_GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 13, 2), 876 RK_GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 13, 3), 877 RK_GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 878 13, 4), 879 RK_GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 11, 0), 880 RK_GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 11, 1), 881 RK_GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 11, 2), 882 RK_GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 11, 4), 883 RK_GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 11, 5), 884 RK_GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 11, 6), 885 RK_GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 11, 8), 886 RK_GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 11, 9), 887 RK_GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 11, 10), 888 RK_GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 10, 8), 889 RK_GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 10, 9), 890 RK_GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 10, 12), 891 RK_GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 10, 13), 892 RK_GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 13, 6), 893 RK_GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 15, 0), 894 RK_GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 15, 2), 895 RK_GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 15, 5), 896 RK_GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 15, 6), 897 RK_GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 15, 12), 898 RK_GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 16, 12), 899 RK_GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 16, 13), 900 RK_GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 16, 14), 901 RK_GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 16, 15), 902 RK_GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 17, 0), 903 RK_GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 17, 3), 904 RK_GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 17, 4), 905 RK_GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 17, 10), 906 RK_GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 18, 9), 907 RK_GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 18, 10), 908 RK_GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 19, 0), 909 RK_GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 19, 1), 910 RK_GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 19, 4), 911 RK_GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 20, 8), 912 RK_GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 20, 9), 913 RK_GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 20, 13), 914 RK_GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 21, 0), 915 RK_GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 21, 1), 916 RK_GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 21, 2), 917 RK_GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 21, 3), 918 RK_GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 21, 4), 919 RK_GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 21, 5), 920 RK_GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 21, 6), 921 RK_GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 21, 7), 922 RK_GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 21, 8), 923 RK_GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 22, 4), 924 RK_GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 22, 5), 925 RK_GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 23, 4), 926 RK_GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 23, 5), 927 RK_GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 23, 7), 928 RK_GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 23, 8), 929 RK_GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 23, 10), 930 RK_GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 23, 12), 931 RK_GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 23, 13), 932 RK_GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 23, 14), 933 RK_GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 23, 15), 934 RK_GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 22, 14), 935 RK_GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 22, 15), 936 RK_GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 24, 6), 937 RK_GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 24, 7), 938 RK_GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 25, 4), 939 RK_GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 25, 5), 940 RK_GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 26, 4), 941 RK_GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 26, 7), 942 RK_GATE(CLK_SARADC, "clk_saradc", "xin24m", 26, 8), 943 RK_GATE(PCLK_SCR, "pclk_scr", "pclk_bus", 26, 12), 944 RK_GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 26, 13), 945 RK_GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 26, 14), 946 RK_GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", 32, 13), 947 RK_GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", 32, 14), 948 RK_GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 32, 15), 949 RK_GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 27, 12), 950 RK_GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 27, 15), 951 RK_GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 28, 0), 952 RK_GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 28, 3), 953 RK_GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 28, 4), 954 RK_GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 28, 7), 955 RK_GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 28, 8), 956 RK_GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 28, 11), 957 RK_GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 28, 12), 958 RK_GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 28, 15), 959 RK_GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 29, 0), 960 RK_GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 29, 3), 961 RK_GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 29, 4), 962 RK_GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 29, 7), 963 RK_GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 29, 8), 964 RK_GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 29, 11), 965 RK_GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 29, 12), 966 RK_GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 29, 15), 967 RK_GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 27, 5), 968 RK_GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 27, 7), 969 RK_GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 27, 9), 970 RK_GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 30, 0), 971 RK_GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 30, 1), 972 RK_GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 30, 2), 973 RK_GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 30, 3), 974 RK_GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 30, 4), 975 RK_GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 30, 5), 976 RK_GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 30, 6), 977 RK_GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 30, 7), 978 RK_GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 30, 8), 979 RK_GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 30, 9), 980 RK_GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 30, 10), 981 RK_GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 30, 12), 982 RK_GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 30, 14), 983 RK_GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 31, 0), 984 RK_GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 31, 10), 985 RK_GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 31, 12), 986 RK_GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 31, 13), 987 RK_GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 31, 15), 988 RK_GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 32, 0), 989 RK_GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 32, 2), 990 RK_GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 31, 2), 991 RK_GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 31, 3), 992 RK_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 31, 4), 993 RK_GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 31, 5), 994 RK_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 31, 6), 995 RK_GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 31, 7), 996 RK_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 31, 8), 997 RK_GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 31, 9), 998 RK_GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 32, 3), 999 RK_GATE(CLK_TIMER0, "clk_timer0", "xin24m", 32, 4), 1000 RK_GATE(CLK_TIMER1, "clk_timer1", "xin24m", 32, 5), 1001 RK_GATE(CLK_TIMER2, "clk_timer2", "xin24m", 32, 6), 1002 RK_GATE(CLK_TIMER3, "clk_timer3", "xin24m", 32, 7), 1003 RK_GATE(CLK_TIMER4, "clk_timer4", "xin24m", 32, 8), 1004 RK_GATE(CLK_TIMER5, "clk_timer5", "xin24m", 32, 9), 1005 RK_GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 33, 8), 1006 RK_GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 33, 13), 1007 RK_GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 33, 14), 1008 RK_GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 33, 15), 1009 RK_GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 34, 4), 1010 RK_GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 34, 5), 1011 RK_GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 34, 6), 1012 RK_GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 34, 11), 1013 RK_GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 34, 12), 1014 RK_GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 34, 13), 1015 RK_GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 34, 14), 1016 }; 1017 1018 1019 static int 1020 rk3568_cru_probe(device_t dev) 1021 { 1022 1023 if (!ofw_bus_status_okay(dev)) 1024 return (ENXIO); 1025 1026 if (ofw_bus_is_compatible(dev, "rockchip,rk3568-cru")) { 1027 device_set_desc(dev, "Rockchip RK3568 Clock & Reset Unit"); 1028 return (BUS_PROBE_DEFAULT); 1029 } 1030 return (ENXIO); 1031 } 1032 1033 static int 1034 rk3568_cru_attach(device_t dev) 1035 { 1036 struct rk_cru_softc *sc; 1037 1038 sc = device_get_softc(dev); 1039 sc->dev = dev; 1040 sc->clks = rk3568_clks; 1041 sc->nclks = nitems(rk3568_clks); 1042 sc->gates = rk3568_gates; 1043 sc->ngates = nitems(rk3568_gates); 1044 sc->reset_offset = 0x400; 1045 sc->reset_num = 478; 1046 1047 return (rk_cru_attach(dev)); 1048 } 1049 1050 static device_method_t methods[] = { 1051 /* Device interface */ 1052 DEVMETHOD(device_probe, rk3568_cru_probe), 1053 DEVMETHOD(device_attach, rk3568_cru_attach), 1054 1055 DEVMETHOD_END 1056 }; 1057 1058 DEFINE_CLASS_1(rk3568_cru, rk3568_cru_driver, methods, 1059 sizeof(struct rk_cru_softc), rk_cru_driver); 1060 1061 EARLY_DRIVER_MODULE(rk3568_cru, simplebus, rk3568_cru_driver, 1062 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
Cache object: 98adef7363f24012bfafa9d65c371f99
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