rk_clk_pll.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright 2018 Emmanuel Vadot <manu@FreeBSD.org>
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  * $FreeBSD$
   28  */
   29 
   30 #ifndef _RK_CLK_PLL_H_
   31 #define _RK_CLK_PLL_H_
   32 
   33 #include <dev/extres/clk/clk.h>
   34 
   35 struct rk_clk_pll_rate {
   36         uint32_t        freq;
   37         uint32_t        refdiv;
   38         uint32_t        fbdiv;
   39         uint32_t        postdiv1;
   40         uint32_t        postdiv2;
   41         uint32_t        dsmpd;
   42         uint32_t        frac;
   43         uint32_t        bwadj;
   44 };
   45 
   46 struct rk_clk_pll_def {
   47         struct clknode_init_def clkdef;
   48         uint32_t                base_offset;
   49 
   50         uint32_t                gate_offset;
   51         uint32_t                gate_shift;
   52 
   53         uint32_t                mode_reg;
   54         uint32_t                mode_shift;
   55 
   56         uint32_t                flags;
   57 
   58         struct rk_clk_pll_rate  *rates;
   59         struct rk_clk_pll_rate  *frac_rates;
   60 };
   61 
   62 #define RK_CLK_PLL_HAVE_GATE    0x1
   63 
   64 int rk3066_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef);
   65 int rk3328_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef);
   66 int rk3399_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef);
   67 
   68 #endif /* _RK_CLK_PLL_H_ */

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FreeBSD/Linux Kernel Cross Reference sys/arm64/rockchip/clk/rk_clk_pll.h

FreeBSD/Linux Kernel Cross Reference
sys/arm64/rockchip/clk/rk_clk_pll.h