rk3568_pciephy.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause
    3  *
    4  * Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk>
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  */
   28 
   29 #include <sys/param.h>
   30 #include <sys/bus.h>
   31 #include <sys/kernel.h>
   32 #include <sys/module.h>
   33 #include <sys/mutex.h>
   34 #include <sys/rman.h>
   35 #include <machine/bus.h>
   36 
   37 #include <dev/ofw/openfirm.h>
   38 #include <dev/ofw/ofw_bus.h>
   39 #include <dev/ofw/ofw_bus_subr.h>
   40 
   41 #include <dev/fdt/simple_mfd.h>
   42 
   43 #include <dev/extres/clk/clk.h>
   44 #include <dev/extres/hwreset/hwreset.h>
   45 #include <dev/extres/regulator/regulator.h>
   46 #include <dev/extres/syscon/syscon.h>
   47 #include <dev/extres/phy/phy.h>
   48 
   49 #include <contrib/device-tree/include/dt-bindings/phy/phy.h>
   50 
   51 #include "syscon_if.h"
   52 #include "phydev_if.h"
   53 #include "phynode_if.h"
   54 
   55 #define GRF_PCIE30PHY_CON1              0x04
   56 #define GRF_PCIE30PHY_CON4              0x10
   57 #define GRF_PCIE30PHY_CON6              0x18
   58 #define  GRF_BIFURCATION_LANE_0_1       (1 << 0)
   59 #define  GRF_BIFURCATION_LANE_2_3       (1 << 1)
   60 #define  GRF_PCIE30PHY_WR_EN            (0xf << 16)
   61 #define GRF_PCIE30PHY_CON9              0x24
   62 #define  GRF_PCIE30PHY_DA_OCM           ((1 << 15) | (1 << (15 + 16)))
   63 #define GRF_PCIE30PHY_STATUS0           0x80
   64 #define  SRAM_INIT_DONE                 (1 << 14)
   65 
   66 static struct ofw_compat_data compat_data[] = {
   67         {"rockchip,rk3568-pcie3-phy",   1},
   68         {NULL, 0}
   69 };
   70 
   71 struct rk3568_pciephy_softc {
   72         device_t        dev;
   73         phandle_t       node;
   74         struct resource *mem;
   75         struct phynode  *phynode;
   76         struct syscon   *phy_grf;
   77         clk_t           refclk_m;
   78         clk_t           refclk_n;
   79         clk_t           pclk;
   80         hwreset_t       phy_reset;
   81 };
   82 
   83 
   84 /* PHY class and methods */
   85 static int
   86 rk3568_pciephy_enable(struct phynode *phynode, bool enable)
   87 {
   88         device_t dev = phynode_get_device(phynode);
   89         struct rk3568_pciephy_softc *sc = device_get_softc(dev);
   90         int count;
   91 
   92         if (enable) {
   93                 /* Deassert PCIe PMA output clamp mode */
   94                 SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON9,
   95                     GRF_PCIE30PHY_DA_OCM);
   96 
   97                 /* Set bifurcation according to DT entry */
   98                 if (OF_hasprop(sc->node, "rockchip,bifurcation")) {
   99                         SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON6,
  100                             GRF_PCIE30PHY_WR_EN | GRF_BIFURCATION_LANE_0_1);
  101                         SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON1,
  102                             GRF_PCIE30PHY_DA_OCM);
  103                         device_printf(dev, "setup 2 x PCIeX1\n");
  104                 }
  105                 else
  106                         device_printf(dev, "setup 1 x PCIeX2\n");
  107 
  108                 hwreset_deassert(sc->phy_reset);
  109 
  110                 /* Poll for SRAM loaded and ready */
  111                 for (count = 100; count; count--) {
  112                         if (SYSCON_READ_4(sc->phy_grf, GRF_PCIE30PHY_STATUS0) &
  113                             SRAM_INIT_DONE)
  114                                 break;
  115                         DELAY(10000);
  116                         if (count == 0) {
  117                                 device_printf(dev, "SRAM init timeout!\n");
  118                                 return (ENXIO);
  119                         }
  120                 }
  121         }
  122         return (0);
  123 }
  124 
  125 static phynode_method_t rk3568_pciephy_phynode_methods[] = {
  126         PHYNODEMETHOD(phynode_enable,   rk3568_pciephy_enable),
  127 
  128         PHYNODEMETHOD_END
  129 };
  130 DEFINE_CLASS_1(rk3568_pciephy_phynode, rk3568_pciephy_phynode_class,
  131     rk3568_pciephy_phynode_methods, 0, phynode_class);
  132 
  133 
  134 /* Device class and methods */
  135 static int
  136 rk3568_pciephy_probe(device_t dev)
  137 {
  138 
  139         if (!ofw_bus_status_okay(dev))
  140                 return (ENXIO);
  141         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
  142                 return (ENXIO);
  143         device_set_desc(dev, "RockChip PCIe PHY");
  144         return (BUS_PROBE_DEFAULT);
  145 }
  146 
  147 static int
  148 rk3568_pciephy_attach(device_t dev)
  149 {
  150         struct rk3568_pciephy_softc *sc = device_get_softc(dev);
  151         struct phynode_init_def phy_init;
  152         struct phynode *phynode;
  153         int rid = 0;
  154 
  155         sc->dev = dev;
  156         sc->node = ofw_bus_get_node(dev);
  157 
  158         /* Get memory resource */
  159         if (!(sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
  160             RF_ACTIVE))) {
  161                 device_printf(dev, "Cannot allocate memory resources\n");
  162                 return (ENXIO);
  163         }
  164 
  165         /* Get syncons handle */
  166         if (OF_hasprop(sc->node, "rockchip,phy-grf") &&
  167             syscon_get_by_ofw_property(dev, sc->node, "rockchip,phy-grf",
  168             &sc->phy_grf))
  169                 return (ENXIO);
  170 
  171         /* Get & enable clocks */
  172         if (clk_get_by_ofw_name(dev, 0, "refclk_m", &sc->refclk_m)) {
  173                 device_printf(dev, "getting refclk_m failed\n");
  174                 return (ENXIO);
  175         }
  176         if (clk_enable(sc->refclk_m))
  177                 device_printf(dev, "enable refclk_m failed\n");
  178         if (clk_get_by_ofw_name(dev, 0, "refclk_n", &sc->refclk_n)) {
  179                 device_printf(dev, "getting refclk_n failed\n");
  180                 return (ENXIO);
  181         }
  182         if (clk_enable(sc->refclk_n))
  183                 device_printf(dev, "enable refclk_n failed\n");
  184         if (clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk)) {
  185                 device_printf(dev, "getting pclk failed\n");
  186                 return (ENXIO);
  187         }
  188         if (clk_enable(sc->pclk))
  189                 device_printf(dev, "enable pclk failed\n");
  190 
  191         /* Get & assert reset */
  192         if (hwreset_get_by_ofw_idx(dev, sc->node, 0, &sc->phy_reset)) {
  193                 device_printf(dev, "Cannot get reset\n");
  194         }
  195         else
  196                 hwreset_assert(sc->phy_reset);
  197 
  198         /* Set RC/EP mode not implemented yet (RC mode only) */
  199 
  200         bzero(&phy_init, sizeof(phy_init));
  201         phy_init.id = PHY_NONE;
  202         phy_init.ofw_node = sc->node;
  203         if (!(phynode = phynode_create(dev, &rk3568_pciephy_phynode_class,
  204             &phy_init))) {
  205                 device_printf(dev, "failed to create pciephy PHY\n");
  206                 return (ENXIO);
  207         }
  208         if (!phynode_register(phynode)) {
  209                 device_printf(dev, "failed to register pciephy PHY\n");
  210                 return (ENXIO);
  211         }
  212         sc->phynode = phynode;
  213 
  214         return (0);
  215 }
  216 
  217 static device_method_t rk3568_pciephy_methods[] = {
  218         DEVMETHOD(device_probe,         rk3568_pciephy_probe),
  219         DEVMETHOD(device_attach,        rk3568_pciephy_attach),
  220 
  221         DEVMETHOD_END
  222 };
  223 
  224 DEFINE_CLASS_1(rk3568_pciephy, rk3568_pciephy_driver, rk3568_pciephy_methods,
  225     sizeof(struct simple_mfd_softc), simple_mfd_driver);
  226 EARLY_DRIVER_MODULE(rk3568_pciephy, simplebus, rk3568_pciephy_driver,
  227     0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE);

Cache object: 65a1b0df05d8a80aff52725648a4702f

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FreeBSD/Linux Kernel Cross Reference sys/arm64/rockchip/rk3568_pciephy.c

FreeBSD/Linux Kernel Cross Reference
sys/arm64/rockchip/rk3568_pciephy.c