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FreeBSD/Linux Kernel Cross Reference
sys/arm64/rockchip/rk_gpio.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2021 Soren Schmidt <sos@deepcore.dk> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/proc.h> 40 #include <sys/rman.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/gpio.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <machine/intr.h> 48 49 #include <dev/gpio/gpiobusvar.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 #include <dev/extres/clk/clk.h> 53 54 #include "gpio_if.h" 55 #include "pic_if.h" 56 57 #include "fdt_pinctrl_if.h" 58 59 enum gpio_regs { 60 RK_GPIO_SWPORTA_DR = 1, /* Data register */ 61 RK_GPIO_SWPORTA_DDR, /* Data direction register */ 62 RK_GPIO_INTEN, /* Interrupt enable register */ 63 RK_GPIO_INTMASK, /* Interrupt mask register */ 64 RK_GPIO_INTTYPE_LEVEL, /* Interrupt level register */ 65 RK_GPIO_INTTYPE_BOTH, /* Both rise and falling edge */ 66 RK_GPIO_INT_POLARITY, /* Interrupt polarity register */ 67 RK_GPIO_INT_STATUS, /* Interrupt status register */ 68 RK_GPIO_INT_RAWSTATUS, /* Raw Interrupt status register */ 69 RK_GPIO_DEBOUNCE, /* Debounce enable register */ 70 RK_GPIO_PORTA_EOI, /* Clear interrupt register */ 71 RK_GPIO_EXT_PORTA, /* External port register */ 72 RK_GPIO_REGNUM 73 }; 74 75 #define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */ 76 77 #define RK_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 78 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_EDGE_BOTH | \ 79 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | \ 80 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_LEVEL_LOW) 81 82 #define GPIO_FLAGS_PINCTRL GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN 83 #define RK_GPIO_MAX_PINS 32 84 85 struct pin_cached { 86 uint8_t is_gpio; 87 uint32_t flags; 88 }; 89 90 struct rk_pin_irqsrc { 91 struct intr_irqsrc isrc; 92 uint32_t irq; 93 uint32_t mode; 94 }; 95 96 struct rk_gpio_softc { 97 device_t sc_dev; 98 device_t sc_busdev; 99 struct mtx sc_mtx; 100 struct resource *sc_res[2]; 101 bus_space_tag_t sc_bst; 102 bus_space_handle_t sc_bsh; 103 clk_t clk; 104 device_t pinctrl; 105 uint32_t swporta; 106 uint32_t swporta_ddr; 107 uint32_t version; 108 struct pin_cached pin_cached[RK_GPIO_MAX_PINS]; 109 uint8_t regs[RK_GPIO_REGNUM]; 110 void *ihandle; 111 struct rk_pin_irqsrc isrcs[RK_GPIO_MAX_PINS]; 112 }; 113 114 static struct ofw_compat_data compat_data[] = { 115 {"rockchip,gpio-bank", 1}, 116 {NULL, 0} 117 }; 118 119 static struct resource_spec rk_gpio_spec[] = { 120 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 121 { SYS_RES_IRQ, 0, RF_ACTIVE }, 122 { -1, 0 } 123 }; 124 125 #define RK_GPIO_VERSION 0x78 126 #define RK_GPIO_TYPE_V1 0x00000000 127 #define RK_GPIO_TYPE_V2 0x01000c2b 128 #define RK_GPIO_ISRC(sc, irq) (&(sc->isrcs[irq].isrc)) 129 130 static int rk_gpio_detach(device_t dev); 131 132 #define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 133 #define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 134 #define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 135 136 #define RK_GPIO_WRITE(_sc, _off, _val) \ 137 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) 138 #define RK_GPIO_READ(_sc, _off) \ 139 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) 140 141 static int 142 rk_gpio_read_bit(struct rk_gpio_softc *sc, int reg, int bit) 143 { 144 int offset = sc->regs[reg]; 145 uint32_t value; 146 147 if (sc->version == RK_GPIO_TYPE_V1) { 148 value = RK_GPIO_READ(sc, offset); 149 value >>= bit; 150 } else { 151 value = RK_GPIO_READ(sc, bit > 15 ? offset + 4 : offset); 152 value >>= (bit % 16); 153 } 154 return (value & 1); 155 } 156 157 static void 158 rk_gpio_write_bit(struct rk_gpio_softc *sc, int reg, int bit, int data) 159 { 160 int offset = sc->regs[reg]; 161 uint32_t value; 162 163 if (sc->version == RK_GPIO_TYPE_V1) { 164 value = RK_GPIO_READ(sc, offset); 165 if (data) 166 value |= (1 << bit); 167 else 168 value &= ~(1 << bit); 169 RK_GPIO_WRITE(sc, offset, value); 170 } else { 171 if (data) 172 value = (1 << (bit % 16)); 173 else 174 value = 0; 175 value |= (1 << ((bit % 16) + 16)); 176 RK_GPIO_WRITE(sc, bit > 15 ? offset + 4 : offset, value); 177 } 178 } 179 180 static uint32_t 181 rk_gpio_read_4(struct rk_gpio_softc *sc, int reg) 182 { 183 int offset = sc->regs[reg]; 184 uint32_t value; 185 186 if (sc->version == RK_GPIO_TYPE_V1) 187 value = RK_GPIO_READ(sc, offset); 188 else 189 value = (RK_GPIO_READ(sc, offset) & 0xffff) | 190 (RK_GPIO_READ(sc, offset + 4) << 16); 191 return (value); 192 } 193 194 static void 195 rk_gpio_write_4(struct rk_gpio_softc *sc, int reg, uint32_t value) 196 { 197 int offset = sc->regs[reg]; 198 199 if (sc->version == RK_GPIO_TYPE_V1) 200 RK_GPIO_WRITE(sc, offset, value); 201 else { 202 RK_GPIO_WRITE(sc, offset, (value & 0xffff) | 0xffff0000); 203 RK_GPIO_WRITE(sc, offset + 4, (value >> 16) | 0xffff0000); 204 } 205 } 206 207 static int 208 rk_gpio_intr(void *arg) 209 { 210 struct rk_gpio_softc *sc = (struct rk_gpio_softc *)arg;; 211 struct trapframe *tf = curthread->td_intr_frame; 212 uint32_t status; 213 214 RK_GPIO_LOCK(sc); 215 status = rk_gpio_read_4(sc, RK_GPIO_INT_STATUS); 216 rk_gpio_write_4(sc, RK_GPIO_PORTA_EOI, status); 217 RK_GPIO_UNLOCK(sc); 218 219 while (status) { 220 int pin = ffs(status) - 1; 221 222 status &= ~(1 << pin); 223 if (intr_isrc_dispatch(RK_GPIO_ISRC(sc, pin), tf)) { 224 device_printf(sc->sc_dev, "Interrupt pin=%d unhandled\n", 225 pin); 226 continue; 227 } 228 229 if ((sc->version == RK_GPIO_TYPE_V1) && 230 (sc->isrcs[pin].mode & GPIO_INTR_EDGE_BOTH)) { 231 RK_GPIO_LOCK(sc); 232 if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin)) 233 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 234 (1 << pin), 0); 235 else 236 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 237 (1 << pin), 1); 238 RK_GPIO_UNLOCK(sc); 239 } 240 } 241 return (FILTER_HANDLED); 242 } 243 244 static int 245 rk_gpio_probe(device_t dev) 246 { 247 248 if (!ofw_bus_status_okay(dev)) 249 return (ENXIO); 250 251 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 252 return (ENXIO); 253 254 device_set_desc(dev, "RockChip GPIO Bank controller"); 255 return (BUS_PROBE_DEFAULT); 256 } 257 258 static int 259 rk_gpio_attach(device_t dev) 260 { 261 struct rk_gpio_softc *sc; 262 phandle_t parent_node, node; 263 int err, i; 264 265 sc = device_get_softc(dev); 266 sc->sc_dev = dev; 267 sc->pinctrl = device_get_parent(dev); 268 parent_node = ofw_bus_get_node(sc->pinctrl); 269 270 node = ofw_bus_get_node(sc->sc_dev); 271 if (!OF_hasprop(node, "gpio-controller")) 272 return (ENXIO); 273 274 mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN); 275 276 if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) { 277 device_printf(dev, "could not allocate resources\n"); 278 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 279 mtx_destroy(&sc->sc_mtx); 280 return (ENXIO); 281 } 282 283 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 284 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 285 286 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) { 287 device_printf(dev, "Cannot get clock\n"); 288 rk_gpio_detach(dev); 289 return (ENXIO); 290 } 291 err = clk_enable(sc->clk); 292 if (err != 0) { 293 device_printf(dev, "Could not enable clock %s\n", 294 clk_get_name(sc->clk)); 295 rk_gpio_detach(dev); 296 return (ENXIO); 297 } 298 299 if ((err = bus_setup_intr(dev, sc->sc_res[1], 300 INTR_TYPE_MISC | INTR_MPSAFE, rk_gpio_intr, NULL, 301 sc, &sc->ihandle))) { 302 device_printf(dev, "Can not setup IRQ\n"); 303 rk_gpio_detach(dev); 304 return (ENXIO); 305 } 306 307 /* 308 * RK3568 has GPIO_VER_ID register, however both 309 * RK3328 and RK3399 doesn't have. So choose the 310 * version based on parent's compat string. 311 */ 312 if (ofw_bus_node_is_compatible(parent_node, "rockchip,rk3568-pinctrl")) 313 sc->version = RK_GPIO_TYPE_V2; 314 else 315 sc->version = RK_GPIO_TYPE_V1; 316 317 switch (sc->version) { 318 case RK_GPIO_TYPE_V1: 319 sc->regs[RK_GPIO_SWPORTA_DR] = 0x00; 320 sc->regs[RK_GPIO_SWPORTA_DDR] = 0x04; 321 sc->regs[RK_GPIO_INTEN] = 0x30; 322 sc->regs[RK_GPIO_INTMASK] = 0x34; 323 sc->regs[RK_GPIO_INTTYPE_LEVEL] = 0x38; 324 sc->regs[RK_GPIO_INT_POLARITY] = 0x3c; 325 sc->regs[RK_GPIO_INT_STATUS] = 0x40; 326 sc->regs[RK_GPIO_INT_RAWSTATUS] = 0x44; 327 sc->regs[RK_GPIO_DEBOUNCE] = 0x48; 328 sc->regs[RK_GPIO_PORTA_EOI] = 0x4c; 329 sc->regs[RK_GPIO_EXT_PORTA] = 0x50; 330 break; 331 case RK_GPIO_TYPE_V2: 332 sc->regs[RK_GPIO_SWPORTA_DR] = 0x00; 333 sc->regs[RK_GPIO_SWPORTA_DDR] = 0x08; 334 sc->regs[RK_GPIO_INTEN] = 0x10; 335 sc->regs[RK_GPIO_INTMASK] = 0x18; 336 sc->regs[RK_GPIO_INTTYPE_LEVEL] = 0x20; 337 sc->regs[RK_GPIO_INTTYPE_BOTH] = 0x30; 338 sc->regs[RK_GPIO_INT_POLARITY] = 0x28; 339 sc->regs[RK_GPIO_INT_STATUS] = 0x50; 340 sc->regs[RK_GPIO_INT_RAWSTATUS] = 0x58; 341 sc->regs[RK_GPIO_DEBOUNCE] = 0x38; 342 sc->regs[RK_GPIO_PORTA_EOI] = 0x60; 343 sc->regs[RK_GPIO_EXT_PORTA] = 0x70; 344 break; 345 default: 346 device_printf(dev, "Unknown gpio version %08x\n", sc->version); 347 rk_gpio_detach(dev); 348 return (ENXIO); 349 } 350 351 for (i = 0; i < RK_GPIO_MAX_PINS; i++) { 352 sc->isrcs[i].irq = i; 353 sc->isrcs[i].mode = GPIO_INTR_CONFORM; 354 if ((err = intr_isrc_register(RK_GPIO_ISRC(sc, i), 355 dev, 0, "%s", device_get_nameunit(dev)))) { 356 device_printf(dev, "Can not register isrc %d\n", err); 357 rk_gpio_detach(dev); 358 return (ENXIO); 359 } 360 } 361 362 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { 363 device_printf(dev, "Can not register pic\n"); 364 rk_gpio_detach(dev); 365 return (ENXIO); 366 } 367 368 sc->sc_busdev = gpiobus_attach_bus(dev); 369 if (sc->sc_busdev == NULL) { 370 rk_gpio_detach(dev); 371 return (ENXIO); 372 } 373 374 /* Set the cached value to unknown */ 375 for (i = 0; i < RK_GPIO_MAX_PINS; i++) 376 sc->pin_cached[i].is_gpio = 2; 377 378 RK_GPIO_LOCK(sc); 379 sc->swporta = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR); 380 sc->swporta_ddr = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR); 381 RK_GPIO_UNLOCK(sc); 382 383 return (0); 384 } 385 386 static int 387 rk_gpio_detach(device_t dev) 388 { 389 struct rk_gpio_softc *sc; 390 391 sc = device_get_softc(dev); 392 393 if (sc->sc_busdev) 394 gpiobus_detach_bus(dev); 395 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 396 mtx_destroy(&sc->sc_mtx); 397 clk_disable(sc->clk); 398 399 return(0); 400 } 401 402 static device_t 403 rk_gpio_get_bus(device_t dev) 404 { 405 struct rk_gpio_softc *sc; 406 407 sc = device_get_softc(dev); 408 409 return (sc->sc_busdev); 410 } 411 412 static int 413 rk_gpio_pin_max(device_t dev, int *maxpin) 414 { 415 416 /* Each bank have always 32 pins */ 417 /* XXX not true*/ 418 *maxpin = 31; 419 return (0); 420 } 421 422 static int 423 rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 424 { 425 struct rk_gpio_softc *sc; 426 uint32_t bank; 427 428 sc = device_get_softc(dev); 429 430 if (pin >= 32) 431 return (EINVAL); 432 433 bank = pin / 8; 434 pin = pin - (bank * 8); 435 RK_GPIO_LOCK(sc); 436 snprintf(name, GPIOMAXNAME, "P%c%d", bank + 'A', pin); 437 RK_GPIO_UNLOCK(sc); 438 439 return (0); 440 } 441 442 static int 443 rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 444 { 445 struct rk_gpio_softc *sc; 446 int rv; 447 448 sc = device_get_softc(dev); 449 450 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) { 451 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio); 452 if (rv != 0) 453 return (rv); 454 if (sc->pin_cached[pin].is_gpio == 0) 455 return (EINVAL); 456 } 457 *flags = 0; 458 rv = FDT_PINCTRL_GET_FLAGS(sc->pinctrl, dev, pin, flags); 459 if (rv != 0) 460 return (rv); 461 sc->pin_cached[pin].flags = *flags; 462 463 if (sc->swporta_ddr & (1 << pin)) 464 *flags |= GPIO_PIN_OUTPUT; 465 else 466 *flags |= GPIO_PIN_INPUT; 467 468 return (0); 469 } 470 471 static int 472 rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 473 { 474 475 if (pin >= RK_GPIO_MAX_PINS) 476 return EINVAL; 477 478 *caps = RK_GPIO_DEFAULT_CAPS; 479 return (0); 480 } 481 482 static int 483 rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 484 { 485 struct rk_gpio_softc *sc; 486 int rv; 487 488 sc = device_get_softc(dev); 489 490 if (pin >= RK_GPIO_MAX_PINS) 491 return (EINVAL); 492 493 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) { 494 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio); 495 if (rv != 0) 496 return (rv); 497 if (sc->pin_cached[pin].is_gpio == 0) 498 return (EINVAL); 499 } 500 501 if (__predict_false((flags & GPIO_PIN_INPUT) && ((flags & GPIO_FLAGS_PINCTRL) != sc->pin_cached[pin].flags))) { 502 rv = FDT_PINCTRL_SET_FLAGS(sc->pinctrl, dev, pin, flags); 503 sc->pin_cached[pin].flags = flags & GPIO_FLAGS_PINCTRL; 504 if (rv != 0) 505 return (rv); 506 } 507 508 RK_GPIO_LOCK(sc); 509 if (flags & GPIO_PIN_INPUT) 510 sc->swporta_ddr &= ~(1 << pin); 511 else if (flags & GPIO_PIN_OUTPUT) 512 sc->swporta_ddr |= (1 << pin); 513 514 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, sc->swporta_ddr); 515 RK_GPIO_UNLOCK(sc); 516 517 return (0); 518 } 519 520 static int 521 rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 522 { 523 struct rk_gpio_softc *sc; 524 525 sc = device_get_softc(dev); 526 527 if (pin >= RK_GPIO_MAX_PINS) 528 return (EINVAL); 529 530 RK_GPIO_LOCK(sc); 531 *val = rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin); 532 RK_GPIO_UNLOCK(sc); 533 534 return (0); 535 } 536 537 static int 538 rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 539 { 540 struct rk_gpio_softc *sc; 541 542 sc = device_get_softc(dev); 543 544 if (pin >= RK_GPIO_MAX_PINS) 545 return (EINVAL); 546 547 RK_GPIO_LOCK(sc); 548 if (value) 549 sc->swporta |= (1 << pin); 550 else 551 sc->swporta &= ~(1 << pin); 552 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta); 553 RK_GPIO_UNLOCK(sc); 554 555 return (0); 556 } 557 558 static int 559 rk_gpio_pin_toggle(device_t dev, uint32_t pin) 560 { 561 struct rk_gpio_softc *sc; 562 563 sc = device_get_softc(dev); 564 565 if (pin >= RK_GPIO_MAX_PINS) 566 return (EINVAL); 567 568 RK_GPIO_LOCK(sc); 569 if (sc->swporta & (1 << pin)) 570 sc->swporta &= ~(1 << pin); 571 else 572 sc->swporta |= (1 << pin); 573 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta); 574 RK_GPIO_UNLOCK(sc); 575 576 return (0); 577 } 578 579 static int 580 rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 581 uint32_t change_pins, uint32_t *orig_pins) 582 { 583 struct rk_gpio_softc *sc; 584 uint32_t reg; 585 586 sc = device_get_softc(dev); 587 588 RK_GPIO_LOCK(sc); 589 reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR); 590 if (orig_pins) 591 *orig_pins = reg; 592 sc->swporta = reg; 593 594 if ((clear_pins | change_pins) != 0) { 595 reg = (reg & ~clear_pins) ^ change_pins; 596 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, reg); 597 } 598 RK_GPIO_UNLOCK(sc); 599 600 return (0); 601 } 602 603 static int 604 rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 605 uint32_t *pin_flags) 606 { 607 struct rk_gpio_softc *sc; 608 uint32_t reg, set, mask, flags; 609 int i; 610 611 sc = device_get_softc(dev); 612 613 if (first_pin != 0 || num_pins > 32) 614 return (EINVAL); 615 616 set = 0; 617 mask = 0; 618 for (i = 0; i < num_pins; i++) { 619 mask = (mask << 1) | 1; 620 flags = pin_flags[i]; 621 if (flags & GPIO_PIN_INPUT) { 622 set &= ~(1 << i); 623 } else if (flags & GPIO_PIN_OUTPUT) { 624 set |= (1 << i); 625 } 626 } 627 628 RK_GPIO_LOCK(sc); 629 reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR); 630 reg &= ~mask; 631 reg |= set; 632 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, reg); 633 sc->swporta_ddr = reg; 634 RK_GPIO_UNLOCK(sc); 635 636 return (0); 637 } 638 639 static int 640 rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 641 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 642 { 643 644 /* The gpios are mapped as <pin flags> */ 645 *pin = gpios[0]; 646 *flags = gpios[1]; 647 return (0); 648 } 649 650 static phandle_t 651 rk_gpio_get_node(device_t bus, device_t dev) 652 { 653 654 /* We only have one child, the GPIO bus, which needs our own node. */ 655 return (ofw_bus_get_node(bus)); 656 } 657 658 static int 659 rk_pic_map_intr(device_t dev, struct intr_map_data *data, 660 struct intr_irqsrc **isrcp) 661 { 662 struct rk_gpio_softc *sc = device_get_softc(dev); 663 struct intr_map_data_gpio *gdata; 664 uint32_t irq; 665 666 if (data->type != INTR_MAP_DATA_GPIO) { 667 device_printf(dev, "Wrong type\n"); 668 return (ENOTSUP); 669 } 670 gdata = (struct intr_map_data_gpio *)data; 671 irq = gdata->gpio_pin_num; 672 if (irq >= RK_GPIO_MAX_PINS) { 673 device_printf(dev, "Invalid interrupt %u\n", irq); 674 return (EINVAL); 675 } 676 *isrcp = RK_GPIO_ISRC(sc, irq); 677 return (0); 678 } 679 680 static int 681 rk_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 682 struct resource *res, struct intr_map_data *data) 683 { 684 struct rk_gpio_softc *sc = device_get_softc(dev); 685 struct rk_pin_irqsrc *rkisrc = (struct rk_pin_irqsrc *)isrc; 686 struct intr_map_data_gpio *gdata; 687 uint32_t mode; 688 uint8_t pin; 689 690 if (!data) { 691 device_printf(dev, "No map data\n"); 692 return (ENOTSUP); 693 } 694 gdata = (struct intr_map_data_gpio *)data; 695 mode = gdata->gpio_intr_mode; 696 pin = gdata->gpio_pin_num; 697 698 if (rkisrc->irq != gdata->gpio_pin_num) { 699 device_printf(dev, "Interrupts don't match\n"); 700 return (EINVAL); 701 } 702 703 if (isrc->isrc_handlers != 0) { 704 device_printf(dev, "Handler already attached\n"); 705 return (rkisrc->mode == mode ? 0 : EINVAL); 706 } 707 rkisrc->mode = mode; 708 709 RK_GPIO_LOCK(sc); 710 711 switch (mode & GPIO_INTR_MASK) { 712 case GPIO_INTR_EDGE_RISING: 713 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 714 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 715 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1); 716 break; 717 case GPIO_INTR_EDGE_FALLING: 718 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 719 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 720 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0); 721 break; 722 case GPIO_INTR_EDGE_BOTH: 723 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 724 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 725 if (sc->version == RK_GPIO_TYPE_V1) { 726 if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin)) 727 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 728 pin, 0); 729 else 730 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 731 pin, 1); 732 } else 733 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_BOTH, pin, 1); 734 break; 735 case GPIO_INTR_LEVEL_HIGH: 736 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 737 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0); 738 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1); 739 break; 740 case GPIO_INTR_LEVEL_LOW: 741 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 742 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0); 743 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0); 744 break; 745 default: 746 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 1); 747 rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 0); 748 RK_GPIO_UNLOCK(sc); 749 return (EINVAL); 750 } 751 rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, pin, 1); 752 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 0); 753 rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 1); 754 RK_GPIO_UNLOCK(sc); 755 756 return (0); 757 } 758 759 static int 760 rk_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 761 struct resource *res, struct intr_map_data *data) 762 { 763 struct rk_gpio_softc *sc = device_get_softc(dev); 764 struct rk_pin_irqsrc *irqsrc; 765 766 irqsrc = (struct rk_pin_irqsrc *)isrc; 767 768 if (isrc->isrc_handlers == 0) { 769 irqsrc->mode = GPIO_INTR_CONFORM; 770 RK_GPIO_LOCK(sc); 771 rk_gpio_write_bit(sc, RK_GPIO_INTEN, irqsrc->irq, 0); 772 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, irqsrc->irq, 0); 773 rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, irqsrc->irq, 0); 774 RK_GPIO_UNLOCK(sc); 775 } 776 return (0); 777 } 778 779 static device_method_t rk_gpio_methods[] = { 780 /* Device interface */ 781 DEVMETHOD(device_probe, rk_gpio_probe), 782 DEVMETHOD(device_attach, rk_gpio_attach), 783 DEVMETHOD(device_detach, rk_gpio_detach), 784 785 /* GPIO protocol */ 786 DEVMETHOD(gpio_get_bus, rk_gpio_get_bus), 787 DEVMETHOD(gpio_pin_max, rk_gpio_pin_max), 788 DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname), 789 DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags), 790 DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps), 791 DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags), 792 DEVMETHOD(gpio_pin_get, rk_gpio_pin_get), 793 DEVMETHOD(gpio_pin_set, rk_gpio_pin_set), 794 DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle), 795 DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32), 796 DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32), 797 DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios), 798 799 /* Interrupt controller interface */ 800 DEVMETHOD(pic_map_intr, rk_pic_map_intr), 801 DEVMETHOD(pic_setup_intr, rk_pic_setup_intr), 802 DEVMETHOD(pic_teardown_intr, rk_pic_teardown_intr), 803 804 /* ofw_bus interface */ 805 DEVMETHOD(ofw_bus_get_node, rk_gpio_get_node), 806 807 DEVMETHOD_END 808 }; 809 810 static driver_t rk_gpio_driver = { 811 "gpio", 812 rk_gpio_methods, 813 sizeof(struct rk_gpio_softc), 814 }; 815 816 /* 817 * GPIO driver is always a child of rk_pinctrl driver and should be probed 818 * and attached within rk_pinctrl_attach function. Due to this, bus pass order 819 * must be same as bus pass order of rk_pinctrl driver. 820 */ 821 EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver, 0, 0, 822 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
Cache object: 5ede95ae30c2456d12e0eb83fa80c26d
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