rk_i2c.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  */
   27 
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD$");
   30 
   31 #include <sys/param.h>
   32 #include <sys/bus.h>
   33 #include <sys/kernel.h>
   34 #include <sys/module.h>
   35 #include <sys/mutex.h>
   36 #include <sys/rman.h>
   37 #include <machine/bus.h>
   38 
   39 #include <dev/ofw/ofw_bus.h>
   40 #include <dev/ofw/ofw_bus_subr.h>
   41 
   42 #include <dev/iicbus/iiconf.h>
   43 #include <dev/iicbus/iicbus.h>
   44 
   45 #include <dev/extres/clk/clk.h>
   46 
   47 #include "iicbus_if.h"
   48 
   49 #define RK_I2C_CON                      0x00
   50 #define  RK_I2C_CON_EN                  (1 << 0)
   51 #define  RK_I2C_CON_MODE_SHIFT          1
   52 #define  RK_I2C_CON_MODE_TX             0
   53 #define  RK_I2C_CON_MODE_RRX            1
   54 #define  RK_I2C_CON_MODE_RX             2
   55 #define  RK_I2C_CON_MODE_RTX            3
   56 #define  RK_I2C_CON_MODE_MASK           0x6
   57 #define  RK_I2C_CON_START               (1 << 3)
   58 #define  RK_I2C_CON_STOP                (1 << 4)
   59 #define  RK_I2C_CON_LASTACK             (1 << 5)
   60 #define  RK_I2C_CON_NAKSTOP             (1 << 6)
   61 #define  RK_I2C_CON_CTRL_MASK           0xFF
   62 
   63 #define RK_I2C_CLKDIV           0x04
   64 #define  RK_I2C_CLKDIVL_MASK    0xFFFF
   65 #define  RK_I2C_CLKDIVL_SHIFT   0
   66 #define  RK_I2C_CLKDIVH_MASK    0xFFFF0000
   67 #define  RK_I2C_CLKDIVH_SHIFT   16
   68 #define  RK_I2C_CLKDIV_MUL      8
   69 
   70 #define RK_I2C_MRXADDR                  0x08
   71 #define  RK_I2C_MRXADDR_SADDR_MASK      0xFFFFFF
   72 #define  RK_I2C_MRXADDR_VALID(x)        (1 << (24 + x))
   73 
   74 #define RK_I2C_MRXRADDR                 0x0C
   75 #define  RK_I2C_MRXRADDR_SRADDR_MASK    0xFFFFFF
   76 #define  RK_I2C_MRXRADDR_VALID(x)       (1 << (24 + x))
   77 
   78 #define RK_I2C_MTXCNT           0x10
   79 #define  RK_I2C_MTXCNT_MASK     0x3F
   80 
   81 #define RK_I2C_MRXCNT           0x14
   82 #define  RK_I2C_MRXCNT_MASK     0x3F
   83 
   84 #define RK_I2C_IEN              0x18
   85 #define  RK_I2C_IEN_BTFIEN      (1 << 0)
   86 #define  RK_I2C_IEN_BRFIEN      (1 << 1)
   87 #define  RK_I2C_IEN_MBTFIEN     (1 << 2)
   88 #define  RK_I2C_IEN_MBRFIEN     (1 << 3)
   89 #define  RK_I2C_IEN_STARTIEN    (1 << 4)
   90 #define  RK_I2C_IEN_STOPIEN     (1 << 5)
   91 #define  RK_I2C_IEN_NAKRCVIEN   (1 << 6)
   92 #define  RK_I2C_IEN_ALL         (RK_I2C_IEN_MBTFIEN | RK_I2C_IEN_MBRFIEN | \
   93         RK_I2C_IEN_STARTIEN | RK_I2C_IEN_STOPIEN | RK_I2C_IEN_NAKRCVIEN)
   94 
   95 #define RK_I2C_IPD              0x1C
   96 #define  RK_I2C_IPD_BTFIPD      (1 << 0)
   97 #define  RK_I2C_IPD_BRFIPD      (1 << 1)
   98 #define  RK_I2C_IPD_MBTFIPD     (1 << 2)
   99 #define  RK_I2C_IPD_MBRFIPD     (1 << 3)
  100 #define  RK_I2C_IPD_STARTIPD    (1 << 4)
  101 #define  RK_I2C_IPD_STOPIPD     (1 << 5)
  102 #define  RK_I2C_IPD_NAKRCVIPD   (1 << 6)
  103 #define  RK_I2C_IPD_ALL         (RK_I2C_IPD_MBTFIPD | RK_I2C_IPD_MBRFIPD | \
  104         RK_I2C_IPD_STARTIPD | RK_I2C_IPD_STOPIPD | RK_I2C_IPD_NAKRCVIPD)
  105 
  106 #define RK_I2C_FNCT             0x20
  107 #define  RK_I2C_FNCT_MASK       0x3F
  108 
  109 #define RK_I2C_TXDATA_BASE      0x100
  110 
  111 #define RK_I2C_RXDATA_BASE      0x200
  112 
  113 /* 8 data registers, 4 bytes each. */
  114 #define RK_I2C_MAX_RXTX_LEN     32
  115 
  116 enum rk_i2c_state {
  117         STATE_IDLE = 0,
  118         STATE_START,
  119         STATE_READ,
  120         STATE_WRITE,
  121         STATE_STOP
  122 };
  123 
  124 struct rk_i2c_softc {
  125         device_t        dev;
  126         struct resource *res[2];
  127         struct mtx      mtx;
  128         clk_t           sclk;
  129         clk_t           pclk;
  130         int             busy;
  131         void *          intrhand;
  132         uint32_t        intr;
  133         uint32_t        ipd;
  134         struct iic_msg  *msg;
  135         size_t          cnt;
  136         bool            transfer_done;
  137         bool            nak_recv;
  138         bool            tx_slave_addr;
  139         uint8_t         mode;
  140         uint8_t         state;
  141 
  142         device_t        iicbus;
  143 };
  144 
  145 static struct ofw_compat_data compat_data[] = {
  146         {"rockchip,rk3288-i2c", 1},
  147         {"rockchip,rk3328-i2c", 1},
  148         {"rockchip,rk3399-i2c", 1},
  149         {NULL,             0}
  150 };
  151 
  152 static struct resource_spec rk_i2c_spec[] = {
  153         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  154         { SYS_RES_IRQ,          0,      RF_ACTIVE | RF_SHAREABLE },
  155         { -1, 0 }
  156 };
  157 
  158 static int rk_i2c_probe(device_t dev);
  159 static int rk_i2c_attach(device_t dev);
  160 static int rk_i2c_detach(device_t dev);
  161 
  162 #define RK_I2C_LOCK(sc)                 mtx_lock(&(sc)->mtx)
  163 #define RK_I2C_UNLOCK(sc)               mtx_unlock(&(sc)->mtx)
  164 #define RK_I2C_ASSERT_LOCKED(sc)        mtx_assert(&(sc)->mtx, MA_OWNED)
  165 #define RK_I2C_READ(sc, reg)            bus_read_4((sc)->res[0], (reg))
  166 #define RK_I2C_WRITE(sc, reg, val)      bus_write_4((sc)->res[0], (reg), (val))
  167 
  168 static uint32_t
  169 rk_i2c_get_clkdiv(struct rk_i2c_softc *sc, uint32_t speed)
  170 {
  171         uint64_t sclk_freq;
  172         uint32_t clkdiv;
  173         int err;
  174 
  175         err = clk_get_freq(sc->sclk, &sclk_freq);
  176         if (err != 0)
  177                 return (err);
  178 
  179         clkdiv = (sclk_freq / speed / RK_I2C_CLKDIV_MUL / 2) - 1;
  180         clkdiv &= RK_I2C_CLKDIVL_MASK;
  181 
  182         clkdiv = clkdiv << RK_I2C_CLKDIVH_SHIFT | clkdiv;
  183 
  184         return (clkdiv);
  185 }
  186 
  187 static int
  188 rk_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
  189 {
  190         struct rk_i2c_softc *sc;
  191         uint32_t clkdiv;
  192         u_int busfreq;
  193 
  194         sc = device_get_softc(dev);
  195 
  196         busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
  197 
  198         clkdiv = rk_i2c_get_clkdiv(sc, busfreq);
  199 
  200         RK_I2C_LOCK(sc);
  201 
  202         /* Set the clock divider */
  203         RK_I2C_WRITE(sc, RK_I2C_CLKDIV, clkdiv);
  204 
  205         /* Disable the module */
  206         RK_I2C_WRITE(sc, RK_I2C_CON, 0);
  207 
  208         RK_I2C_UNLOCK(sc);
  209 
  210         return (0);
  211 }
  212 
  213 static uint8_t
  214 rk_i2c_fill_tx(struct rk_i2c_softc *sc)
  215 {
  216         uint32_t buf32;
  217         uint8_t buf;
  218         int i, j, len;
  219 
  220         len = sc->msg->len - sc->cnt;
  221         if (sc->tx_slave_addr) {
  222                 KASSERT(sc->cnt == 0, ("tx_slave_addr in the middle of data"));
  223                 len++;
  224         }
  225 
  226         if (len > RK_I2C_MAX_RXTX_LEN)
  227                 len = RK_I2C_MAX_RXTX_LEN;
  228 
  229         for (i = 0; i < len; ) {
  230                 buf32 = 0;
  231 
  232                 /* Process next 4 bytes or whatever remains. */
  233                 for (j = 0; j < MIN(len - i, 4); j++) {
  234                         /* Fill the addr if needed */
  235                         if (sc->tx_slave_addr) {
  236                                 buf = sc->msg->slave;
  237                                 sc->tx_slave_addr = false;
  238                         } else {
  239                                 KASSERT(sc->cnt < sc->msg->len,
  240                                     ("%s: data buffer overrun", __func__));
  241                                 buf = sc->msg->buf[sc->cnt];
  242                                 sc->cnt++;
  243                         }
  244                         buf32 |= (uint32_t)buf << (j * 8);
  245                 }
  246 
  247                 KASSERT(i % 4 == 0, ("%s: misaligned write offset", __func__));
  248                 RK_I2C_WRITE(sc, RK_I2C_TXDATA_BASE + i, buf32);
  249 
  250                 i += j;
  251         }
  252 
  253         return (len);
  254 }
  255 
  256 static void
  257 rk_i2c_drain_rx(struct rk_i2c_softc *sc)
  258 {
  259         uint32_t buf32 = 0;
  260         uint8_t buf8;
  261         int len;
  262         int i;
  263 
  264         if (sc->msg == NULL) {
  265                 device_printf(sc->dev, "No current iic msg\n");
  266                 return;
  267         }
  268 
  269         len = sc->msg->len - sc->cnt;
  270         if (len > RK_I2C_MAX_RXTX_LEN)
  271                 len = RK_I2C_MAX_RXTX_LEN;
  272 
  273         for (i = 0; i < len; i++) {
  274                 if (i % 4 == 0)
  275                         buf32 = RK_I2C_READ(sc, RK_I2C_RXDATA_BASE + i);
  276 
  277                 buf8 = (buf32 >> ((i % 4) * 8)) & 0xFF;
  278                 sc->msg->buf[sc->cnt++] = buf8;
  279         }
  280 }
  281 
  282 static void
  283 rk_i2c_send_stop(struct rk_i2c_softc *sc)
  284 {
  285         uint32_t reg;
  286 
  287         RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STOPIEN);
  288 
  289         sc->state = STATE_STOP;
  290 
  291         reg = RK_I2C_READ(sc, RK_I2C_CON);
  292         reg |= RK_I2C_CON_STOP;
  293         RK_I2C_WRITE(sc, RK_I2C_CON, reg);
  294 }
  295 
  296 static void
  297 rk_i2c_intr_locked(struct rk_i2c_softc *sc)
  298 {
  299         uint32_t reg;
  300         int transfer_len;
  301 
  302         sc->ipd = RK_I2C_READ(sc, RK_I2C_IPD);
  303 
  304         /* Something to handle? */
  305         if ((sc->ipd & RK_I2C_IPD_ALL) == 0)
  306                 return;
  307 
  308         RK_I2C_WRITE(sc, RK_I2C_IPD, sc->ipd);
  309         sc->ipd &= RK_I2C_IPD_ALL;
  310 
  311         if (sc->ipd & RK_I2C_IPD_NAKRCVIPD) {
  312                 /* NACK received */
  313                 sc->ipd &= ~RK_I2C_IPD_NAKRCVIPD;
  314                 sc->nak_recv = true;
  315                 /* XXXX last byte !!!, signal error !!! */
  316                 sc->transfer_done = true;
  317                 sc->state = STATE_IDLE;
  318                 goto err;
  319         }
  320 
  321         switch (sc->state) {
  322         case STATE_START:
  323                 /* Disable start bit */
  324                 reg = RK_I2C_READ(sc, RK_I2C_CON);
  325                 reg &= ~RK_I2C_CON_START;
  326                 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
  327 
  328                 if (sc->mode == RK_I2C_CON_MODE_RRX ||
  329                     sc->mode == RK_I2C_CON_MODE_RX) {
  330                         sc->state = STATE_READ;
  331                         RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN |
  332                             RK_I2C_IEN_NAKRCVIEN);
  333 
  334                         if ((sc->msg->len - sc->cnt) > 32)
  335                                 transfer_len = 32;
  336                         else {
  337                                 transfer_len = sc->msg->len - sc->cnt;
  338                                 reg = RK_I2C_READ(sc, RK_I2C_CON);
  339                                 reg |= RK_I2C_CON_LASTACK;
  340                                 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
  341                         }
  342 
  343                         RK_I2C_WRITE(sc, RK_I2C_MRXCNT, transfer_len);
  344                 } else {
  345                         sc->state = STATE_WRITE;
  346                         RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
  347                             RK_I2C_IEN_NAKRCVIEN);
  348 
  349                         transfer_len = rk_i2c_fill_tx(sc);
  350                         RK_I2C_WRITE(sc, RK_I2C_MTXCNT, transfer_len);
  351                 }
  352                 break;
  353         case STATE_READ:
  354                 rk_i2c_drain_rx(sc);
  355 
  356                 if (sc->cnt == sc->msg->len)
  357                         rk_i2c_send_stop(sc);
  358                 else {
  359                         sc->mode = RK_I2C_CON_MODE_RX;
  360                         reg = RK_I2C_READ(sc, RK_I2C_CON) & \
  361                             ~RK_I2C_CON_CTRL_MASK;
  362                         reg |= sc->mode << RK_I2C_CON_MODE_SHIFT;
  363                         reg |= RK_I2C_CON_EN;
  364 
  365                         if ((sc->msg->len - sc->cnt) > 32)
  366                                 transfer_len = 32;
  367                         else {
  368                                 transfer_len = sc->msg->len - sc->cnt;
  369                                 reg |= RK_I2C_CON_LASTACK;
  370                         }
  371 
  372                         RK_I2C_WRITE(sc, RK_I2C_CON, reg);
  373                         RK_I2C_WRITE(sc, RK_I2C_MRXCNT, transfer_len);
  374                 }
  375 
  376                 break;
  377         case STATE_WRITE:
  378                 if (sc->cnt < sc->msg->len) {
  379                         /* Keep writing. */
  380                         RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
  381                             RK_I2C_IEN_NAKRCVIEN);
  382                         transfer_len = rk_i2c_fill_tx(sc);
  383                         RK_I2C_WRITE(sc, RK_I2C_MTXCNT, transfer_len);
  384                         break;
  385                 } else if (!(sc->msg->flags & IIC_M_NOSTOP)) {
  386                         rk_i2c_send_stop(sc);
  387                         break;
  388                 }
  389                 /* passthru */
  390         case STATE_STOP:
  391                 /* Disable stop bit */
  392                 reg = RK_I2C_READ(sc, RK_I2C_CON);
  393                 reg &= ~RK_I2C_CON_STOP;
  394                 RK_I2C_WRITE(sc, RK_I2C_CON, reg);
  395 
  396                 sc->transfer_done = 1;
  397                 sc->state = STATE_IDLE;
  398                 break;
  399         case STATE_IDLE:
  400                 break;
  401         }
  402 
  403 err:
  404         wakeup(sc);
  405 }
  406 
  407 static void
  408 rk_i2c_intr(void *arg)
  409 {
  410         struct rk_i2c_softc *sc;
  411 
  412         sc = (struct rk_i2c_softc *)arg;
  413 
  414         RK_I2C_LOCK(sc);
  415         rk_i2c_intr_locked(sc);
  416         RK_I2C_UNLOCK(sc);
  417 }
  418 
  419 static void
  420 rk_i2c_start_xfer(struct rk_i2c_softc *sc, struct iic_msg *msg, boolean_t last)
  421 {
  422         uint32_t reg;
  423         uint8_t len;
  424 
  425         sc->transfer_done = false;
  426         sc->nak_recv = false;
  427         sc->tx_slave_addr = false;
  428         sc->cnt = 0;
  429         sc->state = STATE_IDLE;
  430         sc->msg = msg;
  431 
  432         reg = RK_I2C_READ(sc, RK_I2C_CON) & ~RK_I2C_CON_CTRL_MASK;
  433         if (!(sc->msg->flags & IIC_M_NOSTART)) {
  434                 /* Stadard message */
  435                 if (sc->mode == RK_I2C_CON_MODE_TX) {
  436                         sc->tx_slave_addr = true;
  437                 }
  438                 sc->state = STATE_START;
  439                 reg |= RK_I2C_CON_START;
  440 
  441                 RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STARTIEN);
  442         } else {
  443                 /* Continuation message */
  444                 if (sc->mode == RK_I2C_CON_MODE_RX) {
  445                         sc->state = STATE_READ;
  446                         if (last)
  447                                 reg |= RK_I2C_CON_LASTACK;
  448 
  449                         RK_I2C_WRITE(sc, RK_I2C_MRXCNT, sc->msg->len);
  450                         RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN |
  451                             RK_I2C_IEN_NAKRCVIEN);
  452                 } else {
  453                         sc->state = STATE_WRITE;
  454                         len = rk_i2c_fill_tx(sc);
  455 
  456                         RK_I2C_WRITE(sc, RK_I2C_MTXCNT, len);
  457 
  458                         RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
  459                             RK_I2C_IEN_NAKRCVIEN);
  460                 }
  461         }
  462         reg |= RK_I2C_CON_NAKSTOP;
  463         reg |= sc->mode << RK_I2C_CON_MODE_SHIFT;
  464         reg |= RK_I2C_CON_EN;
  465         RK_I2C_WRITE(sc, RK_I2C_CON, reg);
  466 }
  467 
  468 static int
  469 rk_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
  470 {
  471         struct rk_i2c_softc *sc;
  472         uint32_t reg;
  473         bool last_msg;
  474         int i, j, timeout, err;
  475 
  476         sc = device_get_softc(dev);
  477 
  478         RK_I2C_LOCK(sc);
  479 
  480         while (sc->busy)
  481                 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0);
  482         sc->busy = 1;
  483 
  484         /* Disable the module and interrupts */
  485         RK_I2C_WRITE(sc, RK_I2C_CON, 0);
  486         RK_I2C_WRITE(sc, RK_I2C_IEN, 0);
  487 
  488         /* Clean stale interrupts */
  489         RK_I2C_WRITE(sc, RK_I2C_IPD, RK_I2C_IPD_ALL);
  490 
  491         err = 0;
  492         for (i = 0; i < nmsgs; i++) {
  493                 /* Validate parameters. */
  494                 if (msgs == NULL || msgs[i].buf == NULL ||
  495                     msgs[i].len == 0) {
  496                         err = IIC_ENOTSUPP;
  497                         break;
  498                 }
  499                 /*
  500                  * If next message have NOSTART flag, then they both
  501                  * should be same type (read/write) and same address.
  502                  */
  503                 if (i < nmsgs - 1) {
  504                         if ((msgs[i + 1].flags & IIC_M_NOSTART) &&
  505                             ((msgs[i].flags & IIC_M_RD) !=
  506                             (msgs[i + 1].flags & IIC_M_RD) ||
  507                             (msgs[i].slave !=  msgs[i + 1].slave))) {
  508                                 err = IIC_ENOTSUPP;
  509                                 break;
  510                         }
  511                 }
  512                 /*
  513                  * Detect simple register read case.
  514                  * The first message should be IIC_M_WR | IIC_M_NOSTOP,
  515                  * next pure IIC_M_RD (no other flags allowed). Both
  516                  * messages should have same slave address.
  517                  */
  518 
  519                 if (nmsgs - i >= 2 && msgs[i].len < 4 &&
  520                     msgs[i].flags == (IIC_M_WR  | IIC_M_NOSTOP) &&
  521                     msgs[i + 1].flags == IIC_M_RD &&
  522                     (msgs[i].slave & ~LSB) == (msgs[i + 1].slave & ~LSB)) {
  523                         sc->mode = RK_I2C_CON_MODE_RRX;
  524 
  525                         /* Write slave address */
  526                         reg = msgs[i].slave & ~LSB;
  527                         reg |= RK_I2C_MRXADDR_VALID(0);
  528                         RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg);
  529 
  530                         /* Write slave register address */
  531                         reg = 0;
  532                         for (j = 0; j < msgs[i].len ; j++) {
  533                                 reg |= (uint32_t)msgs[i].buf[j] << (j * 8);
  534                                 reg |= RK_I2C_MRXADDR_VALID(j);
  535                         }
  536                         RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, reg);
  537 
  538                         i++;
  539                 } else {
  540                         if (msgs[i].flags & IIC_M_RD) {
  541                                 if (msgs[i].flags & IIC_M_NOSTART) {
  542                                         sc->mode = RK_I2C_CON_MODE_RX;
  543                                 } else {
  544                                         sc->mode = RK_I2C_CON_MODE_RRX;
  545                                         reg = msgs[i].slave & ~LSB;
  546                                         reg |= RK_I2C_MRXADDR_VALID(0);
  547                                         RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg);
  548                                         RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, 0);
  549                                 }
  550                         } else {
  551                                 sc->mode = RK_I2C_CON_MODE_TX;
  552                         }
  553                 }
  554                 /* last message ? */
  555                 last_msg = (i >= nmsgs - 1) ||
  556                     !(msgs[i + 1].flags & IIC_M_NOSTART);
  557                 rk_i2c_start_xfer(sc, msgs + i, last_msg);
  558 
  559                 if (cold) {
  560                         for(timeout = 10000; timeout > 0; timeout--)  {
  561                                 rk_i2c_intr_locked(sc);
  562                                 if (sc->transfer_done)
  563                                         break;
  564                                 DELAY(1000);
  565                         }
  566                         if (timeout <= 0)
  567                                 err = IIC_ETIMEOUT;
  568                 } else {
  569                         while (err == 0 && !sc->transfer_done) {
  570                                 err = msleep(sc, &sc->mtx, PZERO, "rk_i2c",
  571                                     10 * hz);
  572                         }
  573                 }
  574         }
  575 
  576         /* Disable the module and interrupts */
  577         RK_I2C_WRITE(sc, RK_I2C_CON, 0);
  578         RK_I2C_WRITE(sc, RK_I2C_IEN, 0);
  579 
  580         sc->busy = 0;
  581 
  582         if (sc->nak_recv)
  583                 err = IIC_ENOACK;
  584 
  585         RK_I2C_UNLOCK(sc);
  586         return (err);
  587 }
  588 
  589 static int
  590 rk_i2c_probe(device_t dev)
  591 {
  592 
  593         if (!ofw_bus_status_okay(dev))
  594                 return (ENXIO);
  595         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
  596                 return (ENXIO);
  597 
  598         device_set_desc(dev, "RockChip I2C");
  599         return (BUS_PROBE_DEFAULT);
  600 }
  601 
  602 static int
  603 rk_i2c_attach(device_t dev)
  604 {
  605         struct rk_i2c_softc *sc;
  606         int error;
  607 
  608         sc = device_get_softc(dev);
  609         sc->dev = dev;
  610 
  611         mtx_init(&sc->mtx, device_get_nameunit(dev), "rk_i2c", MTX_DEF);
  612 
  613         if (bus_alloc_resources(dev, rk_i2c_spec, sc->res) != 0) {
  614                 device_printf(dev, "cannot allocate resources for device\n");
  615                 error = ENXIO;
  616                 goto fail;
  617         }
  618 
  619         if (bus_setup_intr(dev, sc->res[1],
  620             INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_i2c_intr, sc,
  621             &sc->intrhand)) {
  622                 bus_release_resources(dev, rk_i2c_spec, sc->res);
  623                 device_printf(dev, "cannot setup interrupt handler\n");
  624                 return (ENXIO);
  625         }
  626 
  627         clk_set_assigned(dev, ofw_bus_get_node(dev));
  628 
  629         /* Activate the module clocks. */
  630         error = clk_get_by_ofw_name(dev, 0, "i2c", &sc->sclk);
  631         if (error != 0) {
  632                 device_printf(dev, "cannot get i2c clock\n");
  633                 goto fail;
  634         }
  635         error = clk_enable(sc->sclk);
  636         if (error != 0) {
  637                 device_printf(dev, "cannot enable i2c clock\n");
  638                 goto fail;
  639         }
  640         /* pclk clock is optional. */
  641         error = clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk);
  642         if (error != 0 && error != ENOENT) {
  643                 device_printf(dev, "cannot get pclk clock\n");
  644                 goto fail;
  645         }
  646         if (sc->pclk != NULL) {
  647                 error = clk_enable(sc->pclk);
  648                 if (error != 0) {
  649                         device_printf(dev, "cannot enable pclk clock\n");
  650                         goto fail;
  651                 }
  652         }
  653 
  654         sc->iicbus = device_add_child(dev, "iicbus", -1);
  655         if (sc->iicbus == NULL) {
  656                 device_printf(dev, "cannot add iicbus child device\n");
  657                 error = ENXIO;
  658                 goto fail;
  659         }
  660 
  661         bus_generic_attach(dev);
  662 
  663         return (0);
  664 
  665 fail:
  666         if (rk_i2c_detach(dev) != 0)
  667                 device_printf(dev, "Failed to detach\n");
  668         return (error);
  669 }
  670 
  671 static int
  672 rk_i2c_detach(device_t dev)
  673 {
  674         struct rk_i2c_softc *sc;
  675         int error;
  676 
  677         sc = device_get_softc(dev);
  678 
  679         if ((error = bus_generic_detach(dev)) != 0)
  680                 return (error);
  681 
  682         if (sc->iicbus != NULL)
  683                 if ((error = device_delete_child(dev, sc->iicbus)) != 0)
  684                         return (error);
  685 
  686         if (sc->sclk != NULL)
  687                 clk_release(sc->sclk);
  688         if (sc->pclk != NULL)
  689                 clk_release(sc->pclk);
  690 
  691         if (sc->intrhand != NULL)
  692                 bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand);
  693 
  694         bus_release_resources(dev, rk_i2c_spec, sc->res);
  695 
  696         mtx_destroy(&sc->mtx);
  697 
  698         return (0);
  699 }
  700 
  701 static phandle_t
  702 rk_i2c_get_node(device_t bus, device_t dev)
  703 {
  704 
  705         return ofw_bus_get_node(bus);
  706 }
  707 
  708 static device_method_t rk_i2c_methods[] = {
  709         DEVMETHOD(device_probe,         rk_i2c_probe),
  710         DEVMETHOD(device_attach,        rk_i2c_attach),
  711         DEVMETHOD(device_detach,        rk_i2c_detach),
  712 
  713         /* OFW methods */
  714         DEVMETHOD(ofw_bus_get_node,             rk_i2c_get_node),
  715 
  716         DEVMETHOD(iicbus_callback,      iicbus_null_callback),
  717         DEVMETHOD(iicbus_reset,         rk_i2c_reset),
  718         DEVMETHOD(iicbus_transfer,      rk_i2c_transfer),
  719 
  720         DEVMETHOD_END
  721 };
  722 
  723 static driver_t rk_i2c_driver = {
  724         "rk_i2c",
  725         rk_i2c_methods,
  726         sizeof(struct rk_i2c_softc),
  727 };
  728 
  729 EARLY_DRIVER_MODULE(rk_i2c, simplebus, rk_i2c_driver, 0, 0,
  730     BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
  731 EARLY_DRIVER_MODULE(ofw_iicbus, rk_i2c, ofw_iicbus_driver,
  732     0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
  733 MODULE_DEPEND(rk_i2c, iicbus, 1, 1, 1);
  734 MODULE_VERSION(rk_i2c, 1);
Cache object: 815b76c73151c83a802de4d4377eec1e
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FreeBSD/Linux Kernel Cross Reference sys/arm64/rockchip/rk_i2c.c

FreeBSD/Linux Kernel Cross Reference
sys/arm64/rockchip/rk_i2c.c
