Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/bitsy/io.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* 2 * Definitions for IO devices. Used only in C. 3 */ 4 5 enum 6 { 7 /* hardware counter frequency */ 8 ClockFreq= 3686400, 9 }; 10 11 /* 12 * IRQ's defined by SA1100 13 */ 14 enum 15 { 16 IRQgpio0= 0, 17 IRQgpio1= 1, 18 IRQgpio2= 2, 19 IRQgpio3= 3, 20 IRQgpio4= 4, 21 IRQgpio5= 5, 22 IRQgpio6= 6, 23 IRQgpio7= 7, 24 IRQgpio8= 8, 25 IRQgpio9= 9, 26 IRQgpio10= 10, 27 IRQgpiohi= 11, 28 IRQlcd= 12, 29 IRQudc= 13, 30 IRQuart1b= 15, 31 IRQuart2= 16, 32 IRQuart3= 17, 33 IRQmcp= 18, 34 IRQssp= 19, 35 IRQdma0= 20, 36 IRQdma1= 21, 37 IRQdma2= 22, 38 IRQdma3= 23, 39 IRQdma4= 24, 40 IRQdma5= 25, 41 IRQtimer0= 26, 42 IRQtimer1= 27, 43 IRQtimer2= 28, 44 IRQtimer3= 29, 45 IRQsecond= 30, 46 IRQrtc= 31, 47 }; 48 49 /* 50 * GPIO lines (signal names from compaq document). _i indicates input 51 * and _o output. 52 */ 53 enum 54 { 55 GPIO_PWR_ON_i= 1<<0, /* power button */ 56 GPIO_UP_IRQ_i= 1<<1, /* microcontroller interrupts */ 57 GPIO_LDD8_o= 1<<2, /* LCD data 8-15 */ 58 GPIO_LDD9_o= 1<<3, 59 GPIO_LDD10_o= 1<<4, 60 GPIO_LDD11_o= 1<<5, 61 GPIO_LDD12_o= 1<<6, 62 GPIO_LDD13_o= 1<<7, 63 GPIO_LDD14_o= 1<<8, 64 GPIO_LDD15_o= 1<<9, 65 GPIO_CARD_IND1_i= 1<<10, /* card inserted in PCMCIA socket 1 */ 66 GPIO_CARD_IRQ1_i= 1<<11, /* PCMCIA socket 1 interrupt */ 67 GPIO_CLK_SET0_o= 1<<12, /* clock selects for audio codec */ 68 GPIO_CLK_SET1_o= 1<<13, 69 GPIO_L3_SDA_io= 1<<14, /* UDA1341 interface */ 70 GPIO_L3_MODE_o= 1<<15, 71 GPIO_L3_SCLK_o= 1<<16, 72 GPIO_CARD_IND0_i= 1<<17, /* card inserted in PCMCIA socket 0 */ 73 GPIO_KEY_ACT_i= 1<<18, /* hot key from cradle */ 74 GPIO_SYS_CLK_i= 1<<19, /* clock from codec */ 75 GPIO_BAT_FAULT_i= 1<<20, /* battery fault */ 76 GPIO_CARD_IRQ0_i= 1<<21, /* PCMCIA socket 0 interrupt */ 77 GPIO_LOCK_i= 1<<22, /* expansion pack lock/unlock */ 78 GPIO_COM_DCD_i= 1<<23, /* DCD from UART3 */ 79 GPIO_OPT_IRQ_i= 1<<24, /* expansion pack IRQ */ 80 GPIO_COM_CTS_i= 1<<25, /* CTS from UART3 */ 81 GPIO_COM_RTS_o= 1<<26, /* RTS to UART3 */ 82 GPIO_OPT_IND_i= 1<<27, /* expansion pack inserted */ 83 84 /* Peripheral Unit GPIO pin assignments: alternate functions */ 85 GPIO_SSP_TXD_o= 1<<10, /* SSP Transmit Data */ 86 GPIO_SSP_RXD_i= 1<<11, /* SSP Receive Data */ 87 GPIO_SSP_SCLK_o= 1<<12, /* SSP Sample CLocK */ 88 GPIO_SSP_SFRM_o= 1<<13, /* SSP Sample FRaMe */ 89 /* ser. port 1: */ 90 GPIO_UART_TXD_o= 1<<14, /* UART Transmit Data */ 91 GPIO_UART_RXD_i= 1<<15, /* UART Receive Data */ 92 GPIO_SDLC_SCLK_io= 1<<16, /* SDLC Sample CLocK (I/O) */ 93 GPIO_SDLC_AAF_o= 1<<17, /* SDLC Abort After Frame */ 94 GPIO_UART_SCLK1_i= 1<<18, /* UART Sample CLocK 1 */ 95 /* ser. port 4: */ 96 GPIO_SSP_CLK_i= 1<<19, /* SSP external CLocK */ 97 /* ser. port 3: */ 98 GPIO_UART_SCLK3_i= 1<<20, /* UART Sample CLocK 3 */ 99 /* ser. port 4: */ 100 GPIO_MCP_CLK_i= 1<<21, /* MCP CLocK */ 101 /* test controller: */ 102 GPIO_TIC_ACK_o= 1<<21, /* TIC ACKnowledge */ 103 GPIO_MBGNT_o= 1<<21, /* Memory Bus GraNT */ 104 GPIO_TREQA_i= 1<<22, /* TIC REQuest A */ 105 GPIO_MBREQ_i= 1<<22, /* Memory Bus REQuest */ 106 GPIO_TREQB_i= 1<<23, /* TIC REQuest B */ 107 GPIO_1Hz_o= 1<<25, /* 1 Hz clock */ 108 GPIO_RCLK_o= 1<<26, /* internal (R) CLocK (O, fcpu/2) */ 109 GPIO_32_768kHz_o= 1<<27, /* 32.768 kHz clock (O, RTC) */ 110 }; 111 112 /* 113 * types of interrupts 114 */ 115 enum 116 { 117 GPIOrising, 118 GPIOfalling, 119 GPIOboth, 120 IRQ, 121 }; 122 123 /* hardware registers */ 124 typedef struct Uartregs Uartregs; 125 struct Uartregs 126 { 127 ulong ctl[4]; 128 ulong dummya; 129 ulong data; 130 ulong dummyb; 131 ulong status[2]; 132 }; 133 extern Uartregs *uart3regs; 134 extern Uartregs *uart1regs; 135 136 /* general purpose I/O lines control registers */ 137 typedef struct GPIOregs GPIOregs; 138 struct GPIOregs 139 { 140 ulong level; /* 1 == high */ 141 ulong direction; /* 1 == output */ 142 ulong set; /* a 1 sets the bit, 0 leaves it alone */ 143 ulong clear; /* a 1 clears the bit, 0 leaves it alone */ 144 ulong rising; /* rising edge detect enable */ 145 ulong falling; /* falling edge detect enable */ 146 ulong edgestatus; /* writing a 1 bit clears */ 147 ulong altfunc; /* turn on alternate function for any set bits */ 148 }; 149 150 extern GPIOregs *gpioregs; 151 152 /* extra general purpose I/O bits, output only */ 153 enum 154 { 155 EGPIO_prog_flash= 1<<0, 156 EGPIO_pcmcia_reset= 1<<1, 157 EGPIO_exppack_reset= 1<<2, 158 EGPIO_codec_reset= 1<<3, 159 EGPIO_exp_nvram_power= 1<<4, 160 EGPIO_exp_full_power= 1<<5, 161 EGPIO_lcd_3v= 1<<6, 162 EGPIO_rs232_power= 1<<7, 163 EGPIO_lcd_ic_power= 1<<8, 164 EGPIO_ir_power= 1<<9, 165 EGPIO_audio_power= 1<<10, 166 EGPIO_audio_ic_power= 1<<11, 167 EGPIO_audio_mute= 1<<12, 168 EGPIO_fir= 1<<13, /* not set is sir */ 169 EGPIO_lcd_5v= 1<<14, 170 EGPIO_lcd_9v= 1<<15, 171 }; 172 extern ulong *egpioreg; 173 174 /* Peripheral pin controller registers */ 175 typedef struct PPCregs PPCregs; 176 struct PPCregs { 177 ulong direction; 178 ulong state; 179 ulong assignment; 180 ulong sleepdir; 181 ulong flags; 182 }; 183 extern PPCregs *ppcregs; 184 185 /* Synchronous Serial Port controller registers */ 186 typedef struct SSPregs SSPregs; 187 struct SSPregs { 188 ulong control0; 189 ulong control1; 190 ulong dummy0; 191 ulong data; 192 ulong dummy1; 193 ulong status; 194 }; 195 extern SSPregs *sspregs; 196 197 /* Multimedia Communications Port controller registers */ 198 typedef struct MCPregs MCPregs; 199 struct MCPregs { 200 ulong control0; 201 ulong reserved0; 202 ulong data0; 203 ulong data1; 204 ulong data2; 205 ulong reserved1; 206 ulong status; 207 ulong reserved[11]; 208 ulong control1; 209 }; 210 extern MCPregs *mcpregs; 211 212 /* 213 * memory configuration 214 */ 215 enum 216 { 217 /* bit shifts for pcmcia access time counters */ 218 MECR_io0= 0, 219 MECR_attr0= 5, 220 MECR_mem0= 10, 221 MECR_fast0= 11, 222 MECR_io1= MECR_io0+16, 223 MECR_attr1= MECR_attr0+16, 224 MECR_mem1= MECR_mem0+16, 225 MECR_fast1= MECR_fast0+16, 226 227 REFR_kapd= 29, 228 REFR_eapd= 28, 229 REFR_k1db2= 22, 230 REFR_slfrsh= 31, 231 }; 232 233 typedef struct MemConfRegs MemConfRegs; 234 struct MemConfRegs 235 { 236 ulong mdcnfg; /* 0x00 dram */ 237 ulong mdcas00; /* 0x04 dram banks 0/1 */ 238 ulong mdcas01; /* 0x08 */ 239 ulong mdcas02; /* 0x0c */ 240 ulong msc0; /* 0x10 static */ 241 ulong msc1; /* 0x14 */ 242 ulong mecr; /* 0x18 pcmcia */ 243 ulong mdrefr; /* 0x1c dram refresh */ 244 ulong mdcas20; /* 0x20 dram banks 2/3 */ 245 ulong mdcas21; /* 0x24 */ 246 ulong mdcas22; /* 0x28 */ 247 ulong msc2; /* 0x2c static */ 248 ulong smcnfg; /* 0x30 SMROM config */ 249 }; 250 extern MemConfRegs *memconfregs; 251 252 /* 253 * power management 254 */ 255 256 /* Power management ops */ 257 258 typedef struct PowerRegs PowerRegs; 259 struct PowerRegs 260 { 261 ulong pmcr; /* 0x0 Power manager control register */ 262 ulong pssr; /* 0x4 Power manager sleep status register */ 263 ulong pspr; /* 0x8 Power manager scratch pad register */ 264 ulong pwer; /* 0xc Power manager wakeup enable register */ 265 ulong pcfr; /* 0x10 Power manager general configuration register */ 266 ulong ppcr; /* 0x14 Power manager PPL configuration register */ 267 ulong pgsr; /* 0x18 Power manager GPIO sleep state register */ 268 ulong posr; /* 0x1c Power manager oscillator status register */ 269 }; 270 extern PowerRegs *powerregs; 271 272 /* 273 * reset controller 274 */ 275 276 enum 277 { 278 RCSR_hwr = 0x00000001, /* hw reset */ 279 RCSR_swr = 0x00000002, /* sw reset */ 280 RCSR_wdr = 0x00000004, /* watch dog */ 281 RCSR_smr = 0x00000008, /* sleep mode reset */ 282 }; 283 284 typedef struct ResetRegs ResetRegs; 285 struct ResetRegs 286 { 287 ulong rsrr; /* reset controller software reset register */ 288 ulong rcsr; /* reset controller status register */ 289 }; 290 extern ResetRegs *resetregs; 291 292 typedef struct OSTimerRegs OSTimerRegs; 293 struct OSTimerRegs 294 { 295 ulong osmr[4]; /* match registers */ 296 ulong oscr; /* counter register */ 297 ulong ossr; /* status register */ 298 ulong ower; /* watchdog enable register */ 299 ulong oier; /* timer interrupt enable register */ 300 }; 301 extern OSTimerRegs* timerregs; 302 303 typedef struct Intrregs Intrregs; 304 struct Intrregs 305 { 306 ulong icip; /* pending IRQs */ 307 ulong icmr; /* IRQ mask */ 308 ulong iclr; /* IRQ if bit == 0, FRIQ if 1 */ 309 ulong iccr; /* control register */ 310 ulong icfp; /* pending FIQs */ 311 ulong dummy1[3]; 312 ulong icpr; /* pending interrupts */ 313 }; 314 extern Intrregs *intrregs; 315 316 typedef struct Gpclkregs Gpclkregs; 317 struct Gpclkregs 318 { 319 ulong r0; 320 ulong r1; 321 ulong dummya; 322 ulong r2; 323 ulong r3; 324 }; 325 extern Gpclkregs *gpclkregs; 326 327 /* 328 * Dont use this on bitsy drivers. 329 * This is for compat with code compiled 330 * from the ../pc directory 331 */ 332 333 typedef struct Pcidev Pcidev; 334 typedef struct ISAConf ISAConf; 335 struct Pcidev { int dummy; }; 336 struct ISAConf{ int port; int irq; }; 337 int pcmspecial(char*, ISAConf*);
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