FreeBSD/Linux Kernel Cross Reference
sys/bitsy/mem.h
1 /*
2 * Memory and machine-specific definitions. Used in C and assembler.
3 */
4
5 /*
6 * Sizes
7 */
8 #define BI2BY 8 /* bits per byte */
9 #define BI2WD 32 /* bits per word */
10 #define BY2WD 4 /* bytes per word */
11 #define BY2V 8 /* bytes per double word */
12 #define BY2PG 4096 /* bytes per page */
13 #define WD2PG (BY2PG/BY2WD) /* words per page */
14 #define PGSHIFT 12 /* log(BY2PG) */
15 #define ROUND(s, sz) (((s)+(sz-1))&~(sz-1))
16 #define PGROUND(s) ROUND(s, BY2PG)
17 #define BLOCKALIGN 8
18
19 #define MAXMACH 1 /* max # cpus system can run */
20
21 /*
22 * Time
23 */
24 #define HZ (20) /* clock frequency */
25 #define MS2HZ (1000/HZ) /* millisec per clock tick */
26 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
27
28 /*
29 * Virtual addresses:
30 *
31 * We direct map all discovered DRAM and the area twixt 0xe0000000 and
32 * 0xe8000000 used to provide zeros for cache flushing.
33 *
34 * Flash is mapped to 0xb0000000 and special registers are mapped
35 * on demand to areas starting at 0xa0000000.
36 *
37 * The direct mapping is convenient but not necessary. It means
38 * that we don't have to turn on the MMU till well into the
39 * kernel. This can be changed by providing a mapping in l.s
40 * before calling main.
41 */
42 #define UZERO 0 /* base of user address space */
43 #define UTZERO (UZERO+BY2PG) /* first address in user text */
44 #define KZERO 0xC0000000 /* base of kernel address space */
45 #define KTZERO 0xC0008000 /* first address in kernel text */
46 #define EMEMZERO 0x90000000 /* 256 meg for add on memory */
47 #define EMEMTOP 0xA0000000 /* ... */
48 #define REGZERO 0xA0000000 /* 128 meg for mapspecial regs */
49 #define REGTOP 0xA8000000 /* ... */
50 #define FLASHZERO 0xB0000000 /* 128 meg for flash */
51 #define FLASHTOP 0xB8000000 /* ... */
52 #define DRAMZERO 0xC0000000 /* 128 meg for dram */
53 #define DRAMTOP 0xC8000000 /* ... */
54 #define UCDRAMZERO 0xC8000000 /* 128 meg for dram (uncached/unbuffered) */
55 #define UCDRAMTOP 0xD0000000 /* ... */
56 #define NULLZERO 0xE0000000 /* 128 meg for cache flush zeroes */
57 #define NULLTOP 0xE8000000 /* ... */
58 #define USTKTOP 0x2000000 /* byte just beyond user stack */
59 #define USTKSIZE (8*1024*1024) /* size of user stack */
60 #define TSTKTOP (USTKTOP-USTKSIZE) /* end of new stack in sysexec */
61 #define TSTKSIZ 100
62 #define MACHADDR (KZERO+0x00001000)
63 #define EVECTORS 0xFFFF0000 /* virt base of exception vectors */
64
65 #define KSTACK (16*1024) /* Size of kernel stack */
66
67 /*
68 * Offsets into flash
69 */
70 #define Flash_bootldr (FLASHZERO+0x0) /* boot loader */
71 #define Flash_kernel (FLASHZERO+0x10000) /* boot kernel */
72 #define Flash_tar (FLASHZERO+0x200000) /* fs.sac (tar file) */
73
74 /*
75 * virtual MMU
76 */
77 #define PTEMAPMEM (1024*1024)
78 #define PTEPERTAB (PTEMAPMEM/BY2PG)
79 #define SEGMAPSIZE 1984
80 #define SSEGMAPSIZE 16
81 #define PPN(x) ((x)&~(BY2PG-1))
82
83 /*
84 * SA1110 definitions
85 */
86
87 /*
88 * memory physical addresses
89 */
90 #define PHYSFLASH0 0x00000000
91 #define PHYSDRAM0 0xC0000000
92 #define PHYSNULL0 0xE0000000
93
94 /*
95 * peripheral control module physical addresses
96 */
97 #define USBREGS 0x80000000 /* serial port 0 - USB */
98 #define UART1REGS 0x80010000 /* serial port 1 - UART */
99 #define GPCLKREGS 0x80020060 /* serial port 1 - general purpose clock */
100 #define UART2REGS 0x80030000 /* serial port 2 - low speed IR */
101 #define HSSPREGS 0x80040060 /* serial port 2 - high speed IR */
102 #define UART3REGS 0x80050000 /* serial port 3 - RS232 UART */
103 #define MCPREGS 0x80060000 /* serial port 4 - multimedia comm port */
104 #define SSPREGS 0x80070060 /* serial port 4 - synchronous serial port */
105 #define OSTIMERREGS 0x90000000 /* operating system timer registers */
106 #define POWERREGS 0x90020000 /* power management */
107 #define RESETREGS 0x90030000 /* reset controller */
108 #define GPIOREGS 0x90040000 /* 28 general purpose IO pins */
109 #define INTRREGS 0x90050000 /* interrupt registers */
110 #define PPCREGS 0x90060000 /* peripheral pin controller */
111 #define MEMCONFREGS 0xA0000000 /* memory configuration */
112 #define LCDREGS 0xB0100000 /* display */
113
114 /*
115 * PCMCIA addresses
116 */
117 #define PHYSPCM0REGS 0x20000000
118 #define PYHSPCM0ATTR 0x28000000
119 #define PYHSPCM0MEM 0x2C000000
120 #define PHYSPCM1REGS 0x30000000
121 #define PYHSPCM1ATTR 0x38000000
122 #define PYHSPCM1MEM 0x3C000000
123
124 /*
125 * Program Status Registers
126 */
127 #define PsrMusr 0x00000010 /* mode */
128 #define PsrMfiq 0x00000011
129 #define PsrMirq 0x00000012
130 #define PsrMsvc 0x00000013
131 #define PsrMabt 0x00000017
132 #define PsrMund 0x0000001B
133 #define PsrMask 0x0000001F
134
135 #define PsrDfiq 0x00000040 /* disable FIQ interrupts */
136 #define PsrDirq 0x00000080 /* disable IRQ interrupts */
137
138 #define PsrV 0x10000000 /* overflow */
139 #define PsrC 0x20000000 /* carry/borrow/extend */
140 #define PsrZ 0x40000000 /* zero */
141 #define PsrN 0x80000000 /* negative/less than */
142
143 /*
144 * Coprocessors
145 */
146 #define CpMMU 15
147 #define CpPWR 15
148
149 /*
150 * Internal MMU coprocessor registers
151 */
152 #define CpCPUID 0 /* R: */
153 #define CpControl 1 /* RW: */
154 #define CpTTB 2 /* RW: translation table base */
155 #define CpDAC 3 /* RW: domain access control */
156 #define CpFSR 5 /* RW: fault status */
157 #define CpFAR 6 /* RW: fault address */
158 #define CpCacheFlush 7 /* W: cache flushing, wb draining*/
159 #define CpTLBFlush 8 /* W: TLB flushing */
160 #define CpRBFlush 9 /* W: Read Buffer ops */
161 #define CpPID 13 /* RW: PID for virtual mapping */
162 #define CpBpt 14 /* W: Breakpoint register */
163 #define CpTest 15 /* W: Test, Clock and Idle Control */
164
165 /*
166 * CpControl
167 */
168 #define CpCmmuena 0x00000001 /* M: MMU enable */
169 #define CpCalign 0x00000002 /* A: alignment fault enable */
170 #define CpCdcache 0x00000004 /* C: data cache on */
171 #define CpCwb 0x00000008 /* W: write buffer turned on */
172 #define CpCi32 0x00000010 /* P: 32-bit program space */
173 #define CpCd32 0x00000020 /* D: 32-bit data space */
174 #define CpCbe 0x00000080 /* B: big-endian operation */
175 #define CpCsystem 0x00000100 /* S: system permission */
176 #define CpCrom 0x00000200 /* R: ROM permission */
177 #define CpCicache 0x00001000 /* I: instruction cache on */
178 #define CpCvivec 0x00002000 /* X: virtual interrupt vector adjust */
179
180 /*
181 * fault codes
182 */
183 #define FCterm 0x2 /* terminal */
184 #define FCvec 0x0 /* vector */
185 #define FCalignf 0x1 /* unaligned full word data access */
186 #define FCalignh 0x3 /* unaligned half word data access */
187 #define FCl1abort 0xc /* level 1 external abort on translation */
188 #define FCl2abort 0xe /* level 2 external abort on translation */
189 #define FCtransSec 0x5 /* section translation */
190 #define FCtransPage 0x7 /* page translation */
191 #define FCdomainSec 0x9 /* section domain */
192 #define FCdomainPage 0x11 /* page domain */
193 #define FCpermSec 0x9 /* section permissions */
194 #define FCpermPage 0x11 /* page permissions */
195 #define FCabortLFSec 0x4 /* external abort on linefetch for section */
196 #define FCabortLFPage 0x6 /* external abort on linefetch for page */
197 #define FCabortNLFSec 0x8 /* external abort on non-linefetch for section */
198 #define FCabortNLFPage 0xa /* external abort on non-linefetch for page */
199
200 /*
201 * PTE bits used by fault.h. mmu.c translates them to real values.
202 */
203 #define PTEVALID (1<<0)
204 #define PTERONLY 0 /* this is implied by the absence of PTEWRITE */
205 #define PTEWRITE (1<<1)
206 #define PTEUNCACHED (1<<2)
207 #define PTEKERNEL (1<<3) /* no user access */
208
209 /*
210 * H3650 specific definitions
211 */
212 #define EGPIOREGS 0x49000000 /* Additional GPIO register */
213
214 /* Power management */
215
216 #define PWR_rtc 0x80000000 /* resume on RTC */
217 #define PWR_gpio0 0x00000001 /* resume on power button */
218
219 #define RCSR_all 0x0000000f
220 #define PCFR_opde 0x00000001 /* oscillator power-down enable */
221 #define PCFR_suspend 0x00000001
222 #define PCFR_fp 0x00000002 /* float pcmcia */
223 #define PCFR_fs 0x00000004 /* float static memory */
224 #define PCFR_fo 0x00000008
225
226 #define MDREFR_k1db2 (1 << 22)
227 #define MDREFR_slfrsh 0x80000000 /* self refresh */
228 #define MDREFR_e1pin (1 << 20)
229 #define MSC_rt 0x00030003
230
231 #define MDCNFG_de0 0x00000001 /* dram enable */
232 #define MDCNFG_de1 0x00000002
233 #define MDCNFG_de2 0x00000004
234 #define MDCNFG_de3 0x00000008
235 #define MDCFNG_de 0x0000000f
236 #define PMCR_sf 1
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