lance.h

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    1 /* 
    2  * Mach Operating System
    3  * Copyright (c) 1992,1991,1990,1989 Carnegie Mellon University
    4  * All Rights Reserved.
    5  * 
    6  * Permission to use, copy, modify and distribute this software and its
    7  * documentation is hereby granted, provided that both the copyright
    8  * notice and this permission notice appear in all copies of the
    9  * software, derivative works or modified versions, and any portions
   10  * thereof, and that both notices appear in supporting documentation.
   11  * 
   12  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
   13  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
   14  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
   15  * 
   16  * Carnegie Mellon requests users of this software to return to
   17  * 
   18  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
   19  *  School of Computer Science
   20  *  Carnegie Mellon University
   21  *  Pittsburgh PA 15213-3890
   22  * 
   23  * any improvements or extensions that they make and grant Carnegie Mellon
   24  * the rights to redistribute these changes.
   25  */
   26 /*
   27  * HISTORY
   28  * $Log:        lance.h,v $
   29  * Revision 2.15  93/03/09  10:52:11  danner
   30  *      Proper types for functions in switch structure.
   31  *      [93/03/06            af]
   32  * 
   33  * Revision 2.13.1.1  93/02/04  01:31:59  af
   34  *      More flexible in register accesses (Flamingo).
   35  *      64bit cleanup.
   36  * 
   37  * Revision 2.13  92/05/21  17:05:49  jfriedl
   38  *      Removed comment start from within comment.
   39  *      [92/05/16            jfriedl]
   40  * 
   41  * Revision 2.12  92/05/04  11:23:10  danner
   42  *      Added endianness support.
   43  *      [92/04/21            danner]
   44  * 
   45  * Revision 2.11  91/08/24  11:52:12  af
   46  *      Fixed mis-typing of strides, mods to switch to cope with yet-another
   47  *      DMA bogosity.
   48  *      [91/08/02  01:54:00  af]
   49  * 
   50  * Revision 2.10  91/06/19  11:53:39  rvb
   51  *      File moved here from mips/PMAX since it tries to be generic;
   52  *      it is used on the PMAX and the Vax3100.
   53  *      [91/06/04            rvb]
   54  * 
   55  * Revision 2.9  91/05/14  17:22:15  mrt
   56  *      Correcting copyright
   57  * 
   58  * Revision 2.8  91/02/05  17:41:17  mrt
   59  *      Changed to use new Mach copyright
   60  *      [91/02/02  12:11:54  mrt]
   61  * 
   62  * Revision 2.7  90/12/05  23:31:29  af
   63  * 
   64  * 
   65  * Revision 2.6  90/12/05  20:46:57  af
   66  *      Added decl of se_switch for kernel use.
   67  *      [90/12/03  23:19:49  af]
   68  * 
   69  * Revision 2.5  90/09/09  23:20:30  rpd
   70  *      Minor typos.
   71  *      [90/09/09  19:00:09  af]
   72  * 
   73  *      Documented the extra info that the mapped interface shares with 
   74  *      the user-level driver.
   75  *      [90/08/30  17:09:12  af]
   76  * 
   77  * Revision 2.4  90/08/27  22:05:53  dbg
   78  *      Fixed copyright notice.
   79  *      [90/08/17  23:39:45  af]
   80  * 
   81  * Revision 2.3  90/08/07  22:24:50  rpd
   82  *      Re-Created from scratch, using AMD's data sheets.
   83  *      [90/08/07  15:50:53  af]
   84  * 
   85  * 18-May-89  Robert Baron (rvb) at Carnegie-Mellon University
   86  *      Created.
   87  */
   88 /*
   89  *      File:   if_se.h
   90  *      Authors: Robert V. Baron and Alessandro Forin
   91  *      Date:   1989
   92  *
   93  */
   94 /*
   95  *      AMD 7990 "Lance" Ethernet interface definitions.
   96  *      All structures are as seen from the Lance,
   97  *      both in the memory-alignment sense and in the
   98  *      byte-order sense.  Mapping to host memory is
   99  *      model specific: on pmaxen there is a 16 bit gap
  100  *      every other 16 bits.
  101  */
  102 
  103 #include <scsi/scsi_endian.h>
  104 
  105 /*
  106  * Selection of one of the four Lance CSR is done in a
  107  * two-step process: select which CSR first by writing
  108  * into the RAP, then access the register via the RDP.
  109  * Note that (a) the selection remains, and (b) all
  110  * but CSR0 can only be accessed when the chip is stopped.
  111  * These registers are mapped in the 'registers' I/O segment.
  112  */
  113 #ifndef se_reg_type
  114 #define se_reg_type unsigned short
  115 #endif
  116 typedef volatile se_reg_type *se_reg_t;
  117 
  118 #define CSR0_SELECT     0x0     /* Valid RAP selections                 */
  119 #define CSR1_SELECT     0x1
  120 #define CSR2_SELECT     0x2
  121 #define CSR3_SELECT     0x3
  122 
  123 /*
  124  * Bit definitions for the CSR0.
  125  * Legend:
  126  *      R=Readable       W=Writeable
  127  *      S=Set-on-write-1 C=Clear-on-write-1
  128  */
  129 
  130 #define LN_CSR0_INIT    0x0001  /* (RS) Initialize                      */
  131 #define LN_CSR0_STRT    0x0002  /* (RS) Start                           */
  132 #define LN_CSR0_STOP    0x0004  /* (RS) Stop                            */
  133 #define LN_CSR0_TDMD    0x0008  /* (RS) Transmit demand                 */
  134 #define LN_CSR0_TXON    0x0010  /* (R)  Transmitter enabled             */
  135 #define LN_CSR0_RXON    0x0020  /* (R)  Receiver enabled                */
  136 #define LN_CSR0_INEA    0x0040  /* (RW) Interrupt enable                */
  137 #define LN_CSR0_INTR    0x0080  /* (R)  Interrupt pending               */
  138 #define LN_CSR0_IDON    0x0100  /* (RC) Initialization done             */
  139 #define LN_CSR0_TINT    0x0200  /* (RC) Transmitter interrupt           */
  140 #define LN_CSR0_RINT    0x0400  /* (RC) Receiver interrupt              */
  141 #define LN_CSR0_MERR    0x0800  /* (RC) Memory error during DMA         */
  142 #define LN_CSR0_MISS    0x1000  /* (RC) No available receive buffers    */
  143 #define LN_CSR0_CERR    0x2000  /* (RC) Signal quality (SQE) test       */
  144 #define LN_CSR0_BABL    0x4000  /* (RC) Babble error: xmit too long     */
  145 #define LN_CSR0_ERR     0x8000  /* (R)  Error summary: any of the 4 above */
  146 
  147 #define LN_CSR0_WTC     0x7f00  /* Write-to-clear bits */
  148 
  149 /*
  150  * Bit definitions for the CSR1.
  151  */
  152 
  153 #define LN_CSR1_MBZ     0x0001  /*      Must be zero                    */
  154 #define LN_CSR1_IADR    0xfffe  /* (RW) Initialization block address (low) */
  155 
  156 /*
  157  * Bit definitions for the CSR2.
  158  */
  159 
  160 #define LN_CSR2_IADR    0x00ff  /* (RW) Initialization block address (high) */
  161 #define LN_CSR2_XXXX    0xff00  /* (RW) Reserved                        */
  162 
  163 /*
  164  * Bit definitions for the CSR3.
  165  */
  166 
  167 #define LN_CSR3_BCON    0x0001  /* (RW) BM/HOLD Control                 */
  168 #define LN_CSR3_ACON    0x0002  /* (RW) ALE Control                     */
  169 #define LN_CSR3_BSWP    0x0004  /* (RW) Byte Swap                       */
  170 #define LN_CSR3_XXXX    0xfff8  /* (RW) Reserved                        */
  171 
  172 
  173 /*
  174  * Initialization Block
  175  *
  176  * Read when the INIT command is sent to the lance.
  177  */
  178 
  179 struct se_init_block {
  180         unsigned short  mode;                   /* Mode Register, see below */
  181         unsigned short  phys_addr_low;          /* Ethernet address     */
  182         unsigned short  phys_addr_med;          /* Ethernet address     */
  183         unsigned short  phys_addr_high;         /* Ethernet address     */
  184         unsigned short  logical_addr_filter0;   /* Multicast filter     */
  185         unsigned short  logical_addr_filter1;   /* Multicast filter     */
  186         unsigned short  logical_addr_filter2;   /* Multicast filter     */
  187         unsigned short  logical_addr_filter3;   /* Multicast filter     */
  188         unsigned short  recv_ring_pointer_lo;   /* Receive Ring ptr, low   */
  189         BITFIELD_3(unsigned char,
  190                         recv_ring_pointer_hi,   /* Receive Ring ptr, high  */
  191                         reserved0 : 5,
  192                         recv_ring_len : 3);     /* Length: log2(nbuffers)  */
  193         unsigned short  xmit_ring_pointer_lo;   /* Transmit Ring ptr, low  */
  194         BITFIELD_3(unsigned char,
  195                         xmit_ring_pointer_hi,   /* Transmit Ring ptr, high */
  196                         reserved1 : 5,
  197                         xmit_ring_len : 3);     /* Length: log2(nbuffers)  */
  198 };
  199 
  200 typedef volatile struct se_init_block *se_init_block_t;
  201 
  202 /*
  203  * Bit definitions for the MODE word
  204  * (Normally set to 0)
  205  */
  206 
  207 #define LN_MODE_DRX     0x0001  /* Disable Receiver                     */
  208 #define LN_MODE_DTX     0x0002  /* Disable Transmitter                  */
  209 #define LN_MODE_LOOP    0x0004  /* Loopback mode                        */
  210 #define LN_MODE_DTRC    0x0008  /* Disable CRC generation               */
  211 #define LN_MODE_COLL    0x0010  /* Force collision                      */
  212 #define LN_MODE_DRTY    0x0020  /* Disable retry                        */
  213 #define LN_MODE_INTL    0x0040  /* Internal Loopback mode               */
  214 #define LN_MODE_XXXX    0x7f80  /* Reserved                             */
  215 #define LN_MODE_PROM    0x8000  /* Promiscuous mode                     */
  216 
  217 /*
  218  * Bit definitions for the ring pointers
  219  */
  220 
  221 #define LN_RNGP_LOW     0xfffc  /* longword aligned                     */
  222 
  223 
  224 /*
  225  * Buffer Descriptors
  226  * Legend:
  227  *      H-set-by-Host   C-set-by-chip
  228  */
  229 
  230 struct se_desc {
  231         unsigned short  addr_low;               /* (H)  Buffer pointer low  */
  232         BITFIELD_2(unsigned char,
  233                         addr_hi,                /* (H)  Buffer pointer high */
  234                         status);                /* (HC) Buffer status   */
  235         unsigned short  buffer_size;            /* (H)  Buffer length (bytes),*/
  236                                                 /* bits 15..12 must be ones */
  237         union {
  238            struct {
  239                 BITFIELD_2(unsigned short,
  240                         bcnt : 12,              /* (C)  Rcvd data size  */
  241                         res : 4);               /*      Reads as zeroes */
  242            } rcv;
  243            struct {
  244                 BITFIELD_2(unsigned short,
  245                         TDR : 10,               /* (C)  Time Domain Reflectometry */
  246                         flg2 : 6);              /* (C)  Xmit status     */
  247            } xmt;
  248            unsigned short bits;
  249         } desc4;
  250 #define                 message_size    desc4.rcv.bcnt
  251 #define                 tdr             desc4.xmt.TDR
  252 #define                 status2         desc4.xmt.flg2
  253 };
  254 
  255 typedef volatile struct se_desc  *se_desc_t;
  256 
  257 /*
  258  * Bit definition for STATUS byte (receive case)
  259  */
  260 
  261 #define LN_RSTATE_ENP   0x01    /* (C) End of Packet                    */
  262 #define LN_RSTATE_STP   0x02    /* (C) Start of packet                  */
  263 #define LN_RSTATE_BUFF  0x04    /* (C) Buffer error                     */
  264 #define LN_RSTATE_CRC   0x08    /* (C) CRC error                        */
  265 #define LN_RSTATE_OFLO  0x10    /* (C) SILO Overflow                    */
  266 #define LN_RSTATE_FRAM  0x20    /* (C) Framing error                    */
  267 #define LN_RSTATE_ERR   0x40    /* (C) Error summary                    */
  268 #define LN_RSTATE_OWN   0x80    /* (C) Owned by Lance Chip (if set)     */
  269 
  270 
  271 /*
  272  * Bit definition for STATUS byte (transmit case)
  273  */
  274 
  275 #define LN_TSTATE_ENP   0x01    /* (H) End of Packet                    */
  276 #define LN_TSTATE_STP   0x02    /* (H) Start of packet                  */
  277 #define LN_TSTATE_DEF   0x04    /* (C) Deferred                         */
  278 #define LN_TSTATE_ONE   0x08    /* (C) Retried exactly once             */
  279 #define LN_TSTATE_MORE  0x10    /* (C) Retried more than once           */
  280 #define LN_TSTATE_XXXX  0x20    /* Reserved                             */
  281 #define LN_TSTATE_ERR   0x40    /* (C) Error summary (see status2)      */
  282 #define LN_TSTATE_OWN   0x80    /* (H) Owned by Lance Chip (if set)     */
  283 
  284 /*
  285  * Bit definitions for STATUS2 byte (transmit case)
  286  */
  287 
  288 #define LN_TSTATE2_RTRY 0x01    /* (C) Failed after 16 retransmissions  */
  289 #define LN_TSTATE2_LCAR 0x02    /* (C) Loss of Carrier                  */
  290 #define LN_TSTATE2_LCOL 0x04    /* (C) Late collision                   */
  291 #define LN_TSTATE2_XXXX 0x08    /* Reserved                             */
  292 #define LN_TSTATE2_UFLO 0x10    /* (C) Underflow (late memory)          */
  293 #define LN_TSTATE2_BUFF 0x20    /* (C) Buffering error (no ENP)         */
  294 
  295                                 /* Errors that disable the transmitter  */
  296 #define LN_TSTATE2_DISABLE (LN_TSTATE2_UFLO|LN_TSTATE2_BUFF|LN_TSTATE2_RTRY)
  297 
  298 /*
  299  * Other chip characteristics
  300  */
  301 
  302 #define LN_MINBUF_CH    100     /* Minimum size of first lance buffer, if
  303                                    chaining */
  304 
  305 #define LN_MINBUF_NOCH  60      /* Minimum size of a lance buffer, if
  306                                    no chaining and DTCR==1 */
  307 
  308 #define LN_MINBUF_NOCH_RAW 64   /* Minimum size of a lance buffer, if
  309                                    no chaining and DTCR==0 */
  310 
  311 /*
  312  * Information for mapped ether
  313  */
  314 typedef struct mapped_ether_info {
  315         volatile unsigned int   interrupt_count;
  316                                         /* tot interrupts received */
  317         volatile unsigned short saved_csr0;
  318                                         /* copy of csr0 at last intr */
  319         unsigned char           rom_stride;
  320         unsigned char           ram_stride;
  321                                         /* rom&ram strides */
  322         unsigned                buffer_size;
  323                                         /* how much ram for lance */
  324         natural_t               buffer_physaddr;
  325                                         /* where it is in phys memory */
  326         unsigned                wait_event;
  327 } *mapped_ether_info_t;
  328 
  329 #ifdef  KERNEL
  330 extern struct se_switch {
  331         vm_offset_t     regspace;
  332         vm_offset_t     bufspace;
  333         vm_offset_t     ln_bufspace;
  334         vm_offset_t     romspace;
  335         short           romstride;
  336         short           ramstride;
  337         int             ramsize;
  338         void            (*desc_copyin)( vm_offset_t, vm_offset_t, int);
  339         void            (*desc_copyout)( vm_offset_t, vm_offset_t, int);
  340         void            (*data_copyin)( vm_offset_t, vm_offset_t, int);
  341         void            (*data_copyout)( vm_offset_t, vm_offset_t, int);
  342         void            (*bzero)( vm_offset_t, int );
  343         vm_offset_t     (*mapaddr)( vm_offset_t );
  344         vm_size_t       (*mapoffs)( vm_size_t );
  345 } *se_sw;
  346 #endif  KERNEL
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FreeBSD/Linux Kernel Cross Reference sys/chips/lance.h

FreeBSD/Linux Kernel Cross Reference
sys/chips/lance.h
