Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/chips/vs42x_rb.h
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1 /* 2 * Mach Operating System 3 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 4 * All Rights Reserved. 5 * 6 * Permission to use, copy, modify and distribute this software and its 7 * documentation is hereby granted, provided that both the copyright 8 * notice and this permission notice appear in all copies of the 9 * software, derivative works or modified versions, and any portions 10 * thereof, and that both notices appear in supporting documentation. 11 * 12 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 13 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 14 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 15 * 16 * Carnegie Mellon requests users of this software to return to 17 * 18 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 19 * School of Computer Science 20 * Carnegie Mellon University 21 * Pittsburgh PA 15213-3890 22 * 23 * any improvements or extensions that they make and grant Carnegie Mellon 24 * the rights to redistribute these changes. 25 */ 26 /* 27 * HISTORY 28 * $Log: vs42x_rb.h,v $ 29 * Revision 2.2 91/06/19 11:54:31 rvb 30 * Created, from the DEC specs: 31 * "VS42X-RB Storage Controller, Engineering Specification" 32 * January 1989, DEC Maynard Ma. 33 * [91/04/23 af] 34 * 35 */ 36 /* 37 * File: vs42x_rb.h 38 * Author: Alessandro Forin, Carnegie Mellon University 39 * Date: 5/91 40 * 41 * This file contains definitions for the VS42X-RB Storage 42 * controller, which includes a Disk controller and a 43 * SCSI controller. 44 */ 45 46 #ifndef _VS42X_RB_H_ 47 #define _VS42X_RB_H_ 48 49 /* 50 * Phys addresses for the Vax3100 51 */ 52 #define VAX3100_STC_BASE 0x200c0000 53 #define VAX3100_STC_RAM_COMPAT 0x200d0000 54 #define VAX3100_STC_RAM 0x202d0000 55 56 #define VAX3100_STC_HDC9224 0x00000000 /* offsets from BASE */ 57 #define VAX3100_STC_5380_A 0x00000080 58 #define VAX3100_STC_5380_B 0x00000180 59 #define VAX3100_STC_DMAREG_A 0x000000a0 60 #define VAX3100_STC_DMAREG_B 0x000001a0 61 #define VAX3100_STC_RAM_MODE 0x000000e0 62 63 #define VAX3100_STC_DMAREG_OFF (0xa0-0x80) /* offset from 5380 */ 64 65 #define SCI_REG_SIZE 512 66 67 /* 68 * RAM Buffer for this storage system 69 */ 70 #define SCI_RAM_SIZE 128*1024 71 #define SCI_RAM_COMPATSIZE 32*1024 72 #define SCI_RAM_EXPMODE 0x01 /* char-size mode register */ 73 74 /* 75 * DMA controller for the SCSI subsystem 76 * (Defines for the NCR 5380 are elsewhere) 77 */ 78 79 typedef struct { 80 unsigned int sci_dma_adr; /* +000000a0 */ 81 char pad0[0xc0-0xa0-4]; 82 unsigned int sci_dma_count; /* +000000c0 */ 83 unsigned int sci_dma_dir; /* +000000c4 */ 84 char pad1[0xe0-0xc4-4]; 85 unsigned char sci_dma_rammode;/* +000000e0 */ 86 } *sci_dmaregs_t; 87 88 #define SCI_DMADR_PUT(ptr,adr) (ptr)->sci_dma_adr = (unsigned)(adr) & SCI_DMA_COUNT_MASK; 89 #define SCI_DMADR_GET(ptr,adr) (adr) = (ptr)->sci_dma_adr; 90 91 #define SCI_DMA_COUNT_MASK 0x0001ffff 92 #define SCI_TC_GET(ptr,cnt) {\ 93 (cnt) = (ptr)->sci_dma_count;\ 94 if ((cnt) & 0x00010000) (cnt) |= ~SCI_DMA_COUNT_MASK;\ 95 (cnt) = -(cnt);\ 96 } 97 #define SCI_TC_PUT(ptr,cnt) (ptr)->sci_dma_count = -(cnt); 98 99 #define SCI_DMA_DIR_READ 0x00000001 100 #define SCI_DMA_DIR_WRITE 0x00000000 101 102 /* 103 * Disk controller subsytem (ST506/412), uses a 104 * HDC 9224 Universal Disk Controller chip and 105 * addresses up to 4 disks. 106 */ 107 typedef struct { 108 unsigned char hdc_rap; /* rw: reg addres ptr */ 109 char pad0[3]; 110 unsigned char hdc_cmd; /* w: controller command */ 111 #define hdc_status hdc_cmd /* r: interrupt status */ 112 char pad1[3]; 113 } *sci_hdcregs_t; 114 115 /* 116 * Register Address Pointer 117 */ 118 #define UDC_DMA7 0 /* rw: DMA address bits 7:0 */ 119 #define UDC_DMA15 1 /* rw: DMA address bits 15:8 */ 120 #define UDC_DMA23 2 /* rw: DMA address bits 23:16 */ 121 #define UDC_DSECT 3 /* rw: desired sector */ 122 #define UDC_DHEAD 4 /* wo: desired head */ 123 #define UDC_CHEAD 4 /* ro: current head */ 124 #define UDC_DCYL 5 /* wo: desired cylinder */ 125 #define UDC_CCYL 5 /* ro: current cylinder */ 126 #define UDC_SCNT 6 /* wo: sector count */ 127 #define UDC_RTCNT 7 /* wo: retry count */ 128 #define UDC_MODE 8 /* wo: operating mode */ 129 #define UDC_CSTAT 8 /* ro: chip status */ 130 #define UDC_TERM 9 /* wo: termination conditions */ 131 #define UDC_DSTAT 9 /* ro: drive status */ 132 #define UDC_DATA 10 /* rw: data */ 133 134 /* 135 * Controller Commands 136 */ 137 #define HDCC_RESET 0x00 138 139 #define HDCC_SET_REGP 0x40 /* low 4 bits is regnum */ 140 141 #define HDCC_DESELECT 0x01 142 143 #define HDCC_SELECT 0x20 144 # define HDCC_SELECT_IDMASK 0x03 145 # define HDCC_SELECT_DR_HD 0x04 146 # define HDCC_SELECT_DR_SD 0x08 147 # define HDCC_SELECT_DR_DD 0x0c 148 149 #define HDCC_RESTORE_HD 0x03 150 151 #define HDCC_RESTORE_RX 0x02 152 153 #define HDCC_STEP 0x04 154 # define HDCC_STEP_OUT 0x02 155 # define HDCC_STEP_SKWAIT 0x01 156 157 #define HDCC_POLL 0x10 /* low 4 bits is drive mask */ 158 159 #define HDCC_SEEK 0x50 160 # define HDCC_SEEK_STEP 0x04 161 # define HDCC_SEEK_SKWAIT 0x02 162 # define HDCC_SEEK_VFY 0x01 163 164 #define HDCC_FORMAT 0x60 165 # define HDCC_FORMAT_DDMARK 0x10 166 167 #define HDCC_READ_T 0x5a 168 # define HDCC_READ_XDATA 0x01 169 170 #define HDCC_READ_P 0x58 171 172 #define HDCC_READ_L 0x5c 173 # define HDCC_READ_L_BYPASS 0x02 174 175 #define HDCC_WRITE_P 0x80 176 # define HDCC_WRITE_BYPASS 0x40 177 # define HDCC_WRITE_DDMARK 0x10 178 179 #define HDCC_WRITE_L 0xa0 180 181 /* 182 * Interrupt Status Register 183 */ 184 #define HDCI_BADSECT 0x01 185 #define HDCI_OVRUN 0x02 186 #define HDCI_RDYCHNG 0x04 187 #define HDCI_TERMCOD 0x18 188 # define HDC_T_SUCCESS 0x00 189 # define HDC_T_EREAD_ID 0x08 190 # define HDC_T_EVFY 0x10 191 # define HDC_T_EXFER 0x18 192 #define HDCI_DONE 0x20 193 #define HDCI_DMAREQ 0x40 194 #define HDCI_INT 0x80 /* interrupt pending */ 195 196 /* 197 * Desired/Current Head 198 */ 199 #define UDC_HEAD_HMASK 0x0f /* desired head no */ 200 #define UDC_HEAD_CMASK 0x70 /* desired cyl 10:8 */ 201 #define UDC_HEAD_BADSEC 0x80 202 203 /* 204 * Sector Count 205 */ 206 #define HDC_MAXDATA 256*512 207 208 /* 209 * Retry Count 210 */ 211 #define UDC_RTCNT_MASK 0xf0 212 #define UDC_RTCNT_RXDIS 0x08 /* mbz */ 213 #define UDC_RTCNT_INVRDY 0x04 214 #define UDC_RTCNT_MOTOR 0x02 215 #define UDC_RTCNT_LOSPEED 0x01 216 217 /* 218 * Mode 219 */ 220 #define UDC_MODE_HD 0x80 /* hard disk mode mb1 */ 221 #define UDC_MODE_CHKCOD 0x60 /* error checkin code */ 222 # define UDC_MODE_CRC 0x00 223 # define UDC_MODE_EECC 0x20 /* NA */ 224 # define UDC_MODE_IECC 0x40 /* hard disks internal 32 ecc */ 225 # define UDC_MODE_AECC 0x60 /* NA */ 226 #define UDC_MODE_DENS 0x10 /* mbz */ 227 #define UDC_MODE_SRATE 0x07 228 # define UDC_MODE_RATE_HD 0x00 /* hard disk */ 229 # define UDC_MODE_RATE_DD 0x01 /* double den rx23 */ 230 # define UDC_MODE_RATE_SD 0x02 /* single den rz23 */ 231 # define UDC_MODE_RATE_RD 0x06 /* restore drive */ 232 233 #define UDC_MODE_RX23_DD 0x81 234 #define UDC_MODE_RX23_SD 0x82 235 #define UDC_MODE_RDxx 0xc0 236 #define UDC_MODE_RD_RESTORE 0xc6 237 238 /* 239 * Status 240 */ 241 #define UDC_CSTAT_RETRIED 0x80 242 #define UDC_CSTAT_ECC 0x40 243 #define UDC_CSTAT_ECC_ERR 0x20 244 #define UDC_CSTAT_DELDATA 0x10 245 #define UDC_CSTAT_SYN_ERR 0x08 246 #define UDC_CSTAT_COMP_ERR 0x04 247 #define UDC_CSTAT_SELMASK 0x03 248 # define UDC_CSTAT_SELHD0 0x00 249 # define UDC_CSTAT_SELHD1 0x01 250 # define UDC_CSTAT_SELRX 0x02 251 # define UDC_CSTAT_SELHD2 0x03 252 253 /* 254 * Termination 255 */ 256 #define UDC_TERM_CRCPRE 0x80 /* mb1 */ 257 #define UDC_TERM_IDONE 0x20 258 #define UDC_TERM_DELDAT 0x10 259 #define UDC_TERM_STAT3 0x08 /* mbz */ 260 #define UDC_TERM_WPROT 0x04 261 #define UDC_TERM_IRDCHNG 0x02 262 #define UDC_TERM_WFLT 0x01 263 264 /* 265 * Drive status 266 */ 267 #define UDC_DSTAT_SELACK 0x80 268 #define UDC_DSTAT_INDEX 0x40 269 #define UDC_DSTAT_SKCOM 0x20 270 #define UDC_DSTAT_TRK0 0x10 271 #define UDC_DSTAT_STAT3 0x08 /* mbz */ 272 #define UDC_DSTAT_WPROT 0x04 273 #define UDC_DSTAT_READY 0x02 274 #define UDC_DSTAT_WFLT 0x01 275 276 277 #endif _VS42X_RB_H_
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