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sys/contrib/alpine-hal/al_hal_serdes_interface.h
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1 /******************************************************************************* 2 Copyright (C) 2015 Annapurna Labs Ltd. 3 4 This file may be licensed under the terms of the Annapurna Labs Commercial 5 License Agreement. 6 7 Alternatively, this file can be distributed under the terms of the GNU General 8 Public License V2 as published by the Free Software Foundation and can be 9 found at http://www.gnu.org/licenses/gpl-2.0.html 10 11 Alternatively, redistribution and use in source and binary forms, with or 12 without modification, are permitted provided that the following conditions are 13 met: 14 15 * Redistributions of source code must retain the above copyright notice, 16 this list of conditions and the following disclaimer. 17 18 * Redistributions in binary form must reproduce the above copyright 19 notice, this list of conditions and the following disclaimer in 20 the documentation and/or other materials provided with the 21 distribution. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 24 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 27 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 34 *******************************************************************************/ 35 36 /** 37 * @defgroup group_serdes_api API 38 * SerDes HAL driver API 39 * @ingroup group_serdes SerDes 40 * @{ 41 * 42 * @file al_hal_serdes_interface.h 43 * 44 * @brief Header file for the SerDes HAL driver 45 * 46 */ 47 48 #ifndef __AL_HAL_SERDES_INTERFACE_H__ 49 #define __AL_HAL_SERDES_INTERFACE_H__ 50 51 #include "al_hal_common.h" 52 53 /* *INDENT-OFF* */ 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 /* *INDENT-ON* */ 58 59 enum al_serdes_type { 60 AL_SRDS_TYPE_HSSP, 61 AL_SRDS_TYPE_25G, 62 }; 63 64 enum al_serdes_reg_page { 65 /* Relevant to Serdes hssp and 25g */ 66 AL_SRDS_REG_PAGE_0_LANE_0 = 0, 67 AL_SRDS_REG_PAGE_1_LANE_1, 68 /* Relevant to Serdes hssp only */ 69 AL_SRDS_REG_PAGE_2_LANE_2, 70 AL_SRDS_REG_PAGE_3_LANE_3, 71 /* Relevant to Serdes hssp and 25g */ 72 AL_SRDS_REG_PAGE_4_COMMON, 73 /* Relevant to Serdes hssp only */ 74 AL_SRDS_REG_PAGE_0123_LANES_0123 = 7, 75 /* Relevant to Serdes 25g only */ 76 AL_SRDS_REG_PAGE_TOP, 77 }; 78 79 /* Relevant to Serdes hssp only */ 80 enum al_serdes_reg_type { 81 AL_SRDS_REG_TYPE_PMA = 0, 82 AL_SRDS_REG_TYPE_PCS, 83 }; 84 85 enum al_serdes_lane { 86 AL_SRDS_LANE_0 = AL_SRDS_REG_PAGE_0_LANE_0, 87 AL_SRDS_LANE_1 = AL_SRDS_REG_PAGE_1_LANE_1, 88 AL_SRDS_LANE_2 = AL_SRDS_REG_PAGE_2_LANE_2, 89 AL_SRDS_LANE_3 = AL_SRDS_REG_PAGE_3_LANE_3, 90 91 AL_SRDS_NUM_LANES, 92 AL_SRDS_LANES_0123 = AL_SRDS_REG_PAGE_0123_LANES_0123, 93 }; 94 95 /** Serdes loopback mode */ 96 enum al_serdes_lb_mode { 97 /** No loopback */ 98 AL_SRDS_LB_MODE_OFF, 99 100 /** 101 * Transmits the untimed, partial equalized RX signal out the transmit 102 * IO pins. 103 * No clock used (untimed) 104 */ 105 AL_SRDS_LB_MODE_PMA_IO_UN_TIMED_RX_TO_TX, 106 107 /** 108 * Loops back the TX serializer output into the CDR. 109 * CDR recovered bit clock used (without attenuation) 110 */ 111 AL_SRDS_LB_MODE_PMA_INTERNALLY_BUFFERED_SERIAL_TX_TO_RX, 112 113 /** 114 * Loops back the TX driver IO signal to the RX IO pins 115 * CDR recovered bit clock used (only through IO) 116 */ 117 AL_SRDS_LB_MODE_PMA_SERIAL_TX_IO_TO_RX_IO, 118 119 /** 120 * Parallel loopback from the PMA receive lane data ports, to the 121 * transmit lane data ports 122 * CDR recovered bit clock used 123 */ 124 AL_SRDS_LB_MODE_PMA_PARALLEL_RX_TO_TX, 125 126 /** Loops received data after elastic buffer to transmit path */ 127 AL_SRDS_LB_MODE_PCS_PIPE, 128 129 /** Loops TX data (to PMA) to RX path (instead of PMA data) */ 130 AL_SRDS_LB_MODE_PCS_NEAR_END, 131 132 /** Loops receive data prior to interface block to transmit path */ 133 AL_SRDS_LB_MODE_PCS_FAR_END, 134 }; 135 136 enum al_serdes_clk_freq { 137 AL_SRDS_CLK_FREQ_NA, 138 AL_SRDS_CLK_FREQ_100_MHZ, 139 AL_SRDS_CLK_FREQ_125_MHZ, 140 AL_SRDS_CLK_FREQ_156_MHZ, 141 }; 142 143 enum al_serdes_clk_src { 144 AL_SRDS_CLK_SRC_LOGIC_0, 145 AL_SRDS_CLK_SRC_REF_PINS, 146 AL_SRDS_CLK_SRC_R2L, 147 AL_SRDS_CLK_SRC_R2L_PLL, 148 AL_SRDS_CLK_SRC_L2R, 149 }; 150 151 /** Serdes BIST pattern */ 152 enum al_serdes_bist_pattern { 153 AL_SRDS_BIST_PATTERN_USER, 154 AL_SRDS_BIST_PATTERN_PRBS7, 155 AL_SRDS_BIST_PATTERN_PRBS23, 156 AL_SRDS_BIST_PATTERN_PRBS31, 157 AL_SRDS_BIST_PATTERN_CLK1010, 158 }; 159 160 /** SerDes group rate */ 161 enum al_serdes_rate { 162 AL_SRDS_RATE_1_8, 163 AL_SRDS_RATE_1_4, 164 AL_SRDS_RATE_1_2, 165 AL_SRDS_RATE_FULL, 166 }; 167 168 /** SerDes power mode */ 169 enum al_serdes_pm { 170 AL_SRDS_PM_PD, 171 AL_SRDS_PM_P2, 172 AL_SRDS_PM_P1, 173 AL_SRDS_PM_P0S, 174 AL_SRDS_PM_P0, 175 }; 176 177 /** 178 * Tx de-emphasis parameters 179 */ 180 enum al_serdes_tx_deemph_param { 181 AL_SERDES_TX_DEEMP_C_ZERO, /*< c(0) */ 182 AL_SERDES_TX_DEEMP_C_PLUS, /*< c(1) */ 183 AL_SERDES_TX_DEEMP_C_MINUS, /*< c(-1) */ 184 }; 185 186 struct al_serdes_adv_tx_params { 187 /* 188 * select the input values location. 189 * When set to true the values will be taken from the internal registers 190 * that will be override with the next following parameters. 191 * When set to false the values will be taken from external pins (the 192 * other parameters in this case is not needed) 193 */ 194 al_bool override; 195 /* 196 * Transmit Amplitude control signal. Used to define the full-scale 197 * maximum swing of the driver. 198 * 000 - Not Supported 199 * 001 - 952mVdiff-pkpk 200 * 010 - 1024mVdiff-pkpk 201 * 011 - 1094mVdiff-pkpk 202 * 100 - 1163mVdiff-pkpk 203 * 101 - 1227mVdiff-pkpk 204 * 110 - 1283mVdiff-pkpk 205 * 111 - 1331mVdiff-pkpk 206 */ 207 uint8_t amp; 208 /* Defines the total number of driver units allocated in the driver */ 209 uint8_t total_driver_units; 210 /* Defines the total number of driver units allocated to the 211 * first post-cursor (C+1) tap. */ 212 uint8_t c_plus_1; 213 /* Defines the total number of driver units allocated to the 214 * second post-cursor (C+2) tap. */ 215 uint8_t c_plus_2; 216 /* Defines the total number of driver units allocated to the 217 * first pre-cursor (C-1) tap. */ 218 uint8_t c_minus_1; 219 /* TX driver Slew Rate control: 220 * 00 - 31ps 221 * 01 - 33ps 222 * 10 - 68ps 223 * 11 - 170ps 224 */ 225 uint8_t slew_rate; 226 }; 227 228 struct al_serdes_adv_rx_params { 229 /* 230 * select the input values location. 231 * When set to true the values will be taken from the internal registers 232 * that will be override with the next following parameters. 233 * When set to false the values will be taken based in the equalization 234 * results (the other parameters in this case is not needed) 235 */ 236 al_bool override; 237 /* RX agc high frequency dc gain: 238 * -3'b000: -3dB 239 * -3'b001: -2.5dB 240 * -3'b010: -2dB 241 * -3'b011: -1.5dB 242 * -3'b100: -1dB 243 * -3'b101: -0.5dB 244 * -3'b110: -0dB 245 * -3'b111: 0.5dB 246 */ 247 uint8_t dcgain; 248 /* DFE post-shaping tap 3dB frequency 249 * -3'b000: 684MHz 250 * -3'b001: 576MHz 251 * -3'b010: 514MHz 252 * -3'b011: 435MHz 253 * -3'b100: 354MHz 254 * -3'b101: 281MHz 255 * -3'b110: 199MHz 256 * -3'b111: 125MHz 257 */ 258 uint8_t dfe_3db_freq; 259 /* DFE post-shaping tap gain 260 * 0: no pulse shaping tap 261 * 1: -24mVpeak 262 * 2: -45mVpeak 263 * 3: -64mVpeak 264 * 4: -80mVpeak 265 * 5: -93mVpeak 266 * 6: -101mVpeak 267 * 7: -105mVpeak 268 */ 269 uint8_t dfe_gain; 270 /* DFE first tap gain control 271 * -4'b0000: +1mVpeak 272 * -4'b0001: +10mVpeak 273 * .... 274 * -4'b0110: +55mVpeak 275 * -4'b0111: +64mVpeak 276 * -4'b1000: -1mVpeak 277 * -4'b1001: -10mVpeak 278 * .... 279 * -4'b1110: -55mVpeak 280 * -4'b1111: -64mVpeak 281 */ 282 uint8_t dfe_first_tap_ctrl; 283 /* DFE second tap gain control 284 * -4'b0000: +0mVpeak 285 * -4'b0001: +9mVpeak 286 * .... 287 * -4'b0110: +46mVpeak 288 * -4'b0111: +53mVpeak 289 * -4'b1000: -0mVpeak 290 * -4'b1001: -9mVpeak 291 * .... 292 * -4'b1110: -46mVpeak 293 * -4'b1111: -53mVpeak 294 */ 295 uint8_t dfe_secound_tap_ctrl; 296 /* DFE third tap gain control 297 * -4'b0000: +0mVpeak 298 * -4'b0001: +7mVpeak 299 * .... 300 * -4'b0110: +38mVpeak 301 * -4'b0111: +44mVpeak 302 * -4'b1000: -0mVpeak 303 * -4'b1001: -7mVpeak 304 * .... 305 * -4'b1110: -38mVpeak 306 * -4'b1111: -44mVpeak 307 */ 308 uint8_t dfe_third_tap_ctrl; 309 /* DFE fourth tap gain control 310 * -4'b0000: +0mVpeak 311 * -4'b0001: +6mVpeak 312 * .... 313 * -4'b0110: +29mVpeak 314 * -4'b0111: +33mVpeak 315 * -4'b1000: -0mVpeak 316 * -4'b1001: -6mVpeak 317 * .... 318 * -4'b1110: -29mVpeak 319 * -4'b1111: -33mVpeak 320 */ 321 uint8_t dfe_fourth_tap_ctrl; 322 /* Low frequency agc gain (att) select 323 * -3'b000: Disconnected 324 * -3'b001: -18.5dB 325 * -3'b010: -12.5dB 326 * -3'b011: -9dB 327 * -3'b100: -6.5dB 328 * -3'b101: -4.5dB 329 * -3'b110: -2.9dB 330 * -3'b111: -1.6dB 331 */ 332 uint8_t low_freq_agc_gain; 333 /* Provides a RX Equalizer pre-hint, prior to beginning 334 * adaptive equalization */ 335 uint8_t precal_code_sel; 336 /* High frequency agc boost control 337 * Min d0: Boost ~4dB 338 * Max d31: Boost ~20dB 339 */ 340 uint8_t high_freq_agc_boost; 341 }; 342 343 struct al_serdes_25g_adv_rx_params { 344 /* ATT (PLE Flat-Band Gain) */ 345 uint8_t att; 346 /* APG (CTLE's Flat-Band Gain) */ 347 uint8_t apg; 348 /* LFG (Low-Freq Gain) */ 349 uint8_t lfg; 350 /* HFG (High-Freq Gain) */ 351 uint8_t hfg; 352 /* MBG (MidBand-Freq-knob Gain) */ 353 uint8_t mbg; 354 /* MBF (MidBand-Freq-knob Frequency position Gain) */ 355 uint8_t mbf; 356 /* DFE Tap1 even#0 Value */ 357 int8_t dfe_first_tap_even0_ctrl; 358 /* DFE Tap1 even#1 Value */ 359 int8_t dfe_first_tap_even1_ctrl; 360 /* DFE Tap1 odd#0 Value */ 361 int8_t dfe_first_tap_odd0_ctrl; 362 /* DFE Tap1 odd#1 Value */ 363 int8_t dfe_first_tap_odd1_ctrl; 364 /* DFE Tap2 Value */ 365 int8_t dfe_second_tap_ctrl; 366 /* DFE Tap3 Value */ 367 int8_t dfe_third_tap_ctrl; 368 /* DFE Tap4 Value */ 369 int8_t dfe_fourth_tap_ctrl; 370 /* DFE Tap5 Value */ 371 int8_t dfe_fifth_tap_ctrl; 372 }; 373 374 struct al_serdes_25g_tx_diag_info { 375 uint8_t regulated_supply; 376 int8_t dcd_trim; 377 uint8_t clk_delay; 378 uint8_t calp_multiplied_by_2; 379 uint8_t caln_multiplied_by_2; 380 }; 381 382 struct al_serdes_25g_rx_diag_info { 383 int8_t los_offset; 384 int8_t agc_offset; 385 int8_t leq_gainstage_offset; 386 int8_t leq_eq1_offset; 387 int8_t leq_eq2_offset; 388 int8_t leq_eq3_offset; 389 int8_t leq_eq4_offset; 390 int8_t leq_eq5_offset; 391 int8_t summer_even_offset; 392 int8_t summer_odd_offset; 393 int8_t vscan_even_offset; 394 int8_t vscan_odd_offset; 395 int8_t data_slicer_even0_offset; 396 int8_t data_slicer_even1_offset; 397 int8_t data_slicer_odd0_offset; 398 int8_t data_slicer_odd1_offset; 399 int8_t edge_slicer_even_offset; 400 int8_t edge_slicer_odd_offset; 401 int8_t eye_slicer_even_offset; 402 int8_t eye_slicer_odd_offset; 403 uint8_t cdr_clk_i; 404 uint8_t cdr_clk_q; 405 uint8_t cdr_dll; 406 uint8_t cdr_vco_dosc; 407 uint8_t cdr_vco_fr; 408 uint16_t cdr_dlpf; 409 uint8_t ple_resistance; 410 uint8_t rx_term_mode; 411 uint8_t rx_coupling; 412 uint8_t rx_term_cal_code; 413 uint8_t rx_sheet_res_cal_code; 414 }; 415 416 /** 417 * SRIS parameters 418 */ 419 struct al_serdes_sris_params { 420 /* Controls the frequency accuracy threshold (ppm) for lock detection CDR */ 421 uint16_t ppm_drift_count; 422 /* Controls the frequency accuracy threshold (ppm) for lock detection in the CDR */ 423 uint16_t ppm_drift_max; 424 /* Controls the frequency accuracy threshold (ppm) for lock detection in PLL */ 425 uint16_t synth_ppm_drift_max; 426 /* Elastic buffer full threshold for PCIE modes: GEN1/GEN2 */ 427 uint8_t full_d2r1; 428 /* Elastic buffer full threshold for PCIE modes: GEN3 */ 429 uint8_t full_pcie_g3; 430 /* Elastic buffer midpoint threshold. 431 * Sets the depth of the buffer while in PCIE mode, GEN1/GEN2 432 */ 433 uint8_t rd_threshold_d2r1; 434 /* Elastic buffer midpoint threshold. 435 * Sets the depth of the buffer while in PCIE mode, GEN3 436 */ 437 uint8_t rd_threshold_pcie_g3; 438 }; 439 440 /** SerDes PCIe Rate - values are important for proper behavior */ 441 enum al_serdes_pcie_rate { 442 AL_SRDS_PCIE_RATE_GEN1 = 0, 443 AL_SRDS_PCIE_RATE_GEN2, 444 AL_SRDS_PCIE_RATE_GEN3, 445 }; 446 447 struct al_serdes_grp_obj { 448 void __iomem *regs_base; 449 450 /** 451 * get the type of the serdes. 452 * Must be implemented for all SerDes unit. 453 * 454 * @return the serdes type. 455 */ 456 enum al_serdes_type (*type_get)(void); 457 458 /** 459 * Reads a SERDES internal register 460 * 461 * @param obj The object context 462 * @param page The SERDES register page within the group 463 * @param type The SERDES register type (PMA /PCS) 464 * @param offset The SERDES register offset (0 - 4095) 465 * @param data The read data 466 * 467 * @return 0 if no error found. 468 */ 469 int (*reg_read)(struct al_serdes_grp_obj *, enum al_serdes_reg_page, 470 enum al_serdes_reg_type, uint16_t, uint8_t *); 471 472 /** 473 * Writes a SERDES internal register 474 * 475 * @param obj The object context 476 * @param page The SERDES register page within the group 477 * @param type The SERDES register type (PMA /PCS) 478 * @param offset The SERDES register offset (0 - 4095) 479 * @param data The data to write 480 * 481 * @return 0 if no error found. 482 */ 483 int (*reg_write)(struct al_serdes_grp_obj *, enum al_serdes_reg_page, 484 enum al_serdes_reg_type, uint16_t, uint8_t); 485 486 /** 487 * Enable BIST required overrides 488 * 489 * @param obj The object context 490 * @param grp The SERDES group 491 * @param rate The required speed rate 492 */ 493 void (*bist_overrides_enable)(struct al_serdes_grp_obj *, enum al_serdes_rate); 494 /** 495 * Disable BIST required overrides 496 * 497 * @param obj The object context 498 * @param grp The SERDES group 499 * @param rate The required speed rate 500 */ 501 void (*bist_overrides_disable)(struct al_serdes_grp_obj *); 502 /** 503 * Rx rate change 504 * 505 * @param obj The object context 506 * @param grp The SERDES group 507 * @param rate The Rx required rate 508 */ 509 void (*rx_rate_change)(struct al_serdes_grp_obj *, enum al_serdes_rate); 510 /** 511 * SERDES lane Rx rate change software flow enable 512 * 513 * @param obj The object context 514 * @param lane The SERDES lane within the group 515 */ 516 void (*rx_rate_change_sw_flow_en)(struct al_serdes_grp_obj *, enum al_serdes_lane); 517 /** 518 * SERDES lane Rx rate change software flow disable 519 * 520 * @param obj The object context 521 * @param lane The SERDES lane within the group 522 */ 523 void (*rx_rate_change_sw_flow_dis)(struct al_serdes_grp_obj *, enum al_serdes_lane); 524 /** 525 * PCIe lane rate override check 526 * 527 * @param obj The object context 528 * @param grp The SERDES group 529 * @param lane The SERDES lane within the group 530 * 531 * @returns AL_TRUE if the override is enabled 532 */ 533 al_bool (*pcie_rate_override_is_enabled)(struct al_serdes_grp_obj *, enum al_serdes_lane); 534 /** 535 * PCIe lane rate override control 536 * 537 * @param obj The object context 538 * @param lane The SERDES lane within the group 539 * @param en Enable/disable 540 */ 541 void (*pcie_rate_override_enable_set)(struct al_serdes_grp_obj *, enum al_serdes_lane, 542 al_bool en); 543 /** 544 * PCIe lane rate get 545 * 546 * @param obj The object context 547 * @param lane The SERDES lane within the group 548 */ 549 enum al_serdes_pcie_rate (*pcie_rate_get)(struct al_serdes_grp_obj *, enum al_serdes_lane); 550 /** 551 * PCIe lane rate set 552 * 553 * @param obj The object context 554 * @param lane The SERDES lane within the group 555 * @param rate The required rate 556 */ 557 void (*pcie_rate_set)(struct al_serdes_grp_obj *, enum al_serdes_lane, 558 enum al_serdes_pcie_rate rate); 559 /** 560 * SERDES group power mode control 561 * 562 * @param obj The object context 563 * @param grp The SERDES group 564 * @param pm The required power mode 565 */ 566 void (*group_pm_set)(struct al_serdes_grp_obj *, enum al_serdes_pm); 567 /** 568 * SERDES lane power mode control 569 * 570 * @param obj The object context 571 * @param grp The SERDES group 572 * @param lane The SERDES lane within the group 573 * @param rx_pm The required RX power mode 574 * @param tx_pm The required TX power mode 575 */ 576 void (*lane_pm_set)(struct al_serdes_grp_obj *, enum al_serdes_lane, 577 enum al_serdes_pm, enum al_serdes_pm); 578 579 /** 580 * SERDES group PMA hard reset 581 * Controls Serdes group PMA hard reset 582 * 583 * @param obj The object context 584 * @param grp The SERDES group 585 * @param enable Enable/disable hard reset 586 */ 587 void (*pma_hard_reset_group)(struct al_serdes_grp_obj *, al_bool); 588 /** 589 * SERDES lane PMA hard reset 590 * Controls Serdes lane PMA hard reset 591 * 592 * @param obj The object context 593 * @param lane The SERDES lane within the group 594 * @param enable Enable/disable hard reset 595 */ 596 void (*pma_hard_reset_lane)(struct al_serdes_grp_obj *, enum al_serdes_lane, al_bool); 597 /** 598 * Configure SERDES loopback 599 * Controls the loopback 600 * 601 * @param obj The object context 602 * @param lane The SERDES lane within the group 603 * @param mode The requested loopback mode 604 */ 605 void (*loopback_control)(struct al_serdes_grp_obj *, enum al_serdes_lane, 606 enum al_serdes_lb_mode); 607 /** 608 * SERDES BIST pattern selection 609 * Selects the BIST pattern to be used 610 * 611 * @param obj The object context 612 * @param pattern The pattern to set 613 * @param user_data The pattern user data (when pattern == AL_SRDS_BIST_PATTERN_USER) 614 * 80 bits (8 bytes array) 615 */ 616 void (*bist_pattern_select)(struct al_serdes_grp_obj *, 617 enum al_serdes_bist_pattern, uint8_t *); 618 /** 619 * SERDES BIST TX Enable 620 * Enables/disables TX BIST per lane 621 * 622 * @param obj The object context 623 * @param lane The SERDES lane within the group 624 * @param enable Enable or disable TX BIST 625 */ 626 void (*bist_tx_enable)(struct al_serdes_grp_obj *, enum al_serdes_lane, al_bool); 627 /** 628 * SERDES BIST TX single bit error injection 629 * Injects single bit error during a TX BIST 630 * 631 * @param obj The object context 632 */ 633 void (*bist_tx_err_inject)(struct al_serdes_grp_obj *); 634 /** 635 * SERDES BIST RX Enable 636 * Enables/disables RX BIST per lane 637 * 638 * @param obj The object context 639 * @param lane The SERDES lane within the group 640 * @param enable Enable or disable TX BIST 641 */ 642 void (*bist_rx_enable)(struct al_serdes_grp_obj *, enum al_serdes_lane, al_bool); 643 /** 644 * SERDES BIST RX status 645 * Checks the RX BIST status for a specific SERDES lane 646 * 647 * @param obj The object context 648 * @param lane The SERDES lane within the group 649 * @param is_locked An indication whether RX BIST is locked 650 * @param err_cnt_overflow An indication whether error count overflow occured 651 * @param err_cnt Current bit error count 652 */ 653 void (*bist_rx_status)(struct al_serdes_grp_obj *, enum al_serdes_lane, al_bool *, 654 al_bool *, uint32_t *); 655 656 /** 657 * Set the tx de-emphasis to preset values 658 * 659 * @param obj The object context 660 * @param lane The SERDES lane within the group 661 * 662 */ 663 void (*tx_deemph_preset)(struct al_serdes_grp_obj *, enum al_serdes_lane); 664 /** 665 * Increase tx de-emphasis param. 666 * 667 * @param obj The object context 668 * @param lane The SERDES lane within the group 669 * @param param which tx de-emphasis to change 670 * 671 * @return false in case max is reached. true otherwise. 672 */ 673 al_bool (*tx_deemph_inc)(struct al_serdes_grp_obj *, enum al_serdes_lane, 674 enum al_serdes_tx_deemph_param); 675 /** 676 * Decrease tx de-emphasis param. 677 * 678 * @param obj The object context 679 * @param lane The SERDES lane within the group 680 * @param param which tx de-emphasis to change 681 * 682 * @return false in case min is reached. true otherwise. 683 */ 684 al_bool (*tx_deemph_dec)(struct al_serdes_grp_obj *, enum al_serdes_lane, 685 enum al_serdes_tx_deemph_param); 686 /** 687 * run Rx eye measurement. 688 * 689 * @param obj The object context 690 * @param lane The SERDES lane within the group 691 * @param timeout timeout in uSec 692 * @param value Rx eye measurement value 693 * (0 - completely closed eye, 0xffff - completely open eye). 694 * 695 * @return 0 if no error found. 696 */ 697 int (*eye_measure_run)(struct al_serdes_grp_obj *, enum al_serdes_lane, 698 uint32_t, unsigned int *); 699 /** 700 * Eye diagram single sampling 701 * 702 * @param obj The object context 703 * @param lane The SERDES lane within the group 704 * @param x Sampling X position (0 - 63 --> -1.00 UI ... 1.00 UI) 705 * @param y Sampling Y position (0 - 62 --> 500mV ... -500mV) 706 * @param timeout timeout in uSec 707 * @param value Eye diagram sample value (BER - 0x0000 - 0xffff) 708 * 709 * @return 0 if no error found. 710 */ 711 int (*eye_diag_sample)(struct al_serdes_grp_obj *, enum al_serdes_lane, 712 unsigned int, int, unsigned int, unsigned int *); 713 714 /** 715 * Eye diagram full run 716 * 717 * @param obj The object context 718 * @param lane The SERDES lane within the group 719 * @param x_start Sampling from X position 720 * @param x_stop Sampling to X position 721 * @param x_step jump in x_step 722 * @param y_start Sampling from Y position 723 * @param y_stop Sampling to Y position 724 * @param y_step jump in y_step 725 * @param num_bits_per_sample How many bits to check 726 * @param buf array of results 727 * @param buf_size array size - must be equal to 728 * (((y_stop - y_start) / y_step) + 1) * 729 * (((x_stop - x_start) / x_step) + 1) 730 * 731 * @return 0 if no error found. 732 */ 733 int (*eye_diag_run)(struct al_serdes_grp_obj *, enum al_serdes_lane, 734 int, int, unsigned int, int, int, unsigned int, uint64_t, uint64_t *, 735 uint32_t); 736 /** 737 * Check if signal is detected 738 * 739 * @param obj The object context 740 * @param lane The SERDES lane within the group 741 * 742 * @return true if signal is detected. false otherwise. 743 */ 744 al_bool (*signal_is_detected)(struct al_serdes_grp_obj *, enum al_serdes_lane); 745 746 /** 747 * Check if CDR is locked 748 * 749 * @param obj The object context 750 * @param lane The SERDES lane within the group 751 * 752 * @return true if cdr is locked. false otherwise. 753 */ 754 al_bool (*cdr_is_locked)(struct al_serdes_grp_obj *, enum al_serdes_lane); 755 756 /** 757 * Check if rx is valid for this lane 758 * 759 * @param obj The object context 760 * @param lane The SERDES lane within the group 761 * 762 * @return true if rx is valid. false otherwise. 763 */ 764 al_bool (*rx_valid)(struct al_serdes_grp_obj *, enum al_serdes_lane); 765 766 /** 767 * configure tx advanced parameters 768 * 769 * @param obj The object context 770 * @param lane The SERDES lane within the group 771 * @param params pointer to the tx parameters 772 */ 773 void (*tx_advanced_params_set)(struct al_serdes_grp_obj *, enum al_serdes_lane, void *); 774 /** 775 * read tx advanced parameters 776 * 777 * @param obj The object context 778 * @param lane The SERDES lane within the group 779 * @param params pointer to the tx parameters 780 */ 781 void (*tx_advanced_params_get)(struct al_serdes_grp_obj *, enum al_serdes_lane, void *); 782 /** 783 * configure rx advanced parameters 784 * 785 * @param obj The object context 786 * @param lane The SERDES lane within the group 787 * @param params pointer to the rx parameters 788 */ 789 void (*rx_advanced_params_set)(struct al_serdes_grp_obj *, enum al_serdes_lane, void *); 790 /** 791 * read rx advanced parameters 792 * 793 * @param obj The object context 794 * @param lane The SERDES lane within the group 795 * @param params pointer to the rx parameters 796 */ 797 void (*rx_advanced_params_get)(struct al_serdes_grp_obj *, enum al_serdes_lane, void *); 798 /** 799 * Switch entire SerDes group to SGMII mode based on 156.25 Mhz reference clock 800 * 801 * @param obj The object context 802 * 803 */ 804 void (*mode_set_sgmii)(struct al_serdes_grp_obj *); 805 /** 806 * Switch entire SerDes group to KR mode based on 156.25 Mhz reference clock 807 * 808 * @param obj The object context 809 * 810 */ 811 void (*mode_set_kr)(struct al_serdes_grp_obj *); 812 /** 813 * performs SerDes HW equalization test and update equalization parameters 814 * 815 * @param obj the object context 816 * @param lane The SERDES lane within the group 817 */ 818 int (*rx_equalization)(struct al_serdes_grp_obj *, enum al_serdes_lane); 819 /** 820 * performs Rx equalization and compute the width and height of the eye 821 * 822 * @param obj the object context 823 * @param lane The SERDES lane within the group 824 * @param width the output width of the eye 825 * @param height the output height of the eye 826 */ 827 int (*calc_eye_size)(struct al_serdes_grp_obj *, enum al_serdes_lane, int *, int *); 828 /** 829 * SRIS: Separate Refclk Independent SSC (Spread Spectrum Clocking) 830 * Currently available only for PCIe interfaces. 831 * When working with local Refclk, same SRIS configuration in both serdes sides 832 * (EP and RC in PCIe interface) is required. 833 * 834 * performs SRIS configuration according to params 835 * 836 * @param obj the object context 837 * @param params the SRIS parameters 838 */ 839 void (*sris_config)(struct al_serdes_grp_obj *, void *); 840 /** 841 * set SERDES dcgain parameter 842 * 843 * @param obj the object context 844 * @param dcgain dcgain value to set 845 */ 846 void (*dcgain_set)(struct al_serdes_grp_obj *, uint8_t); 847 /** 848 * read tx diagnostics info 849 * 850 * @param obj The object context 851 * @param lane The SERDES lane within the group 852 * @param params pointer to the tx diagnostics info structure 853 */ 854 void (*tx_diag_info_get)(struct al_serdes_grp_obj *, enum al_serdes_lane, void*); 855 /** 856 * read rx diagnostics info 857 * 858 * @param obj The object context 859 * @param lane The SERDES lane within the group 860 * @param params pointer to the rx diagnostics info structure 861 */ 862 void (*rx_diag_info_get)(struct al_serdes_grp_obj *, enum al_serdes_lane, void*); 863 }; 864 865 866 /* *INDENT-OFF* */ 867 #ifdef __cplusplus 868 } 869 #endif 870 871 /* *INDENT-ON* */ 872 #endif /* __AL_HAL_SERDES_INTERFACE_H__ */ 873 874 /** @} end of SERDES group */ 875
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