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sys/contrib/alpine-hal/al_hal_udma_debug.c
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1 /*- 2 ******************************************************************************* 3 Copyright (C) 2015 Annapurna Labs Ltd. 4 5 This file may be licensed under the terms of the Annapurna Labs Commercial 6 License Agreement. 7 8 Alternatively, this file can be distributed under the terms of the GNU General 9 Public License V2 as published by the Free Software Foundation and can be 10 found at http://www.gnu.org/licenses/gpl-2.0.html 11 12 Alternatively, redistribution and use in source and binary forms, with or 13 without modification, are permitted provided that the following conditions are 14 met: 15 16 * Redistributions of source code must retain the above copyright notice, 17 this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20 notice, this list of conditions and the following disclaimer in 21 the documentation and/or other materials provided with the 22 distribution. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35 *******************************************************************************/ 36 37 /** 38 * @file al_hal_udma_debug.c 39 * 40 * @brief Universal DMA HAL driver for debug 41 * 42 */ 43 44 #define DEBUG 45 46 #include <al_hal_common.h> 47 #include <al_hal_udma_regs.h> 48 #include <al_hal_udma_debug.h> 49 50 static void al_udma_regs_m2s_axi_print(struct al_udma *udma) 51 { 52 al_dbg("M2S AXI regs:\n"); 53 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, comp_wr_cfg_1); 54 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, comp_wr_cfg_2); 55 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, data_rd_cfg_1); 56 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, data_rd_cfg_2); 57 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, desc_rd_cfg_1); 58 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, desc_rd_cfg_2); 59 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, data_rd_cfg); 60 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, desc_rd_cfg_3); 61 62 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, desc_wr_cfg_1); 63 AL_UDMA_PRINT_REG_FIELD(udma, " ", "\n", "%d", m2s, axi_m2s, 64 desc_wr_cfg_1, 65 max_axi_beats, 66 UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS); 67 AL_UDMA_PRINT_REG_FIELD(udma, " ", "\n", "%d", m2s, axi_m2s, 68 desc_wr_cfg_1, 69 min_axi_beats, 70 UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS); 71 72 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, ostand_cfg); 73 } 74 75 static void al_udma_regs_m2s_general_print(struct al_udma *udma) 76 { 77 al_dbg("M2S general regs:\n"); 78 79 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, state); 80 AL_UDMA_PRINT_REG_FIELD(udma, " ", "\n", "%d", m2s, m2s, state, 81 comp_ctrl, 82 UDMA_M2S_STATE_COMP_CTRL); 83 AL_UDMA_PRINT_REG_FIELD(udma, " ", "\n", "%d", m2s, m2s, state, 84 stream_if, 85 UDMA_M2S_STATE_STREAM_IF); 86 AL_UDMA_PRINT_REG_FIELD(udma, " ", "\n", "%d", m2s, m2s, state, 87 rd_ctrl, 88 UDMA_M2S_STATE_DATA_RD_CTRL); 89 AL_UDMA_PRINT_REG_FIELD(udma, " ", "\n", "%d", m2s, m2s, state, 90 desc_pref, 91 UDMA_M2S_STATE_DESC_PREF); 92 93 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, err_log_mask); 94 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, log_0); 95 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, log_1); 96 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, log_2); 97 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, log_3); 98 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, data_fifo_status); 99 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, header_fifo_status); 100 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, unack_fifo_status); 101 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, check_en); 102 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, fifo_en); 103 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, cfg_len); 104 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, stream_cfg); 105 } 106 107 static void al_udma_regs_m2s_rd_print(struct al_udma *udma) 108 { 109 al_dbg("M2S read regs:\n"); 110 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rd, desc_pref_cfg_1); 111 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rd, desc_pref_cfg_2); 112 113 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rd, desc_pref_cfg_3); 114 AL_UDMA_PRINT_REG_FIELD(udma, " ", "\n", "%d", m2s, m2s_rd, 115 desc_pref_cfg_3, 116 min_burst_below_thr, 117 UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR); 118 AL_UDMA_PRINT_REG_FIELD(udma, " ", "\n", "%d", m2s, m2s_rd, 119 desc_pref_cfg_3, 120 min_burst_above_thr, 121 UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR); 122 AL_UDMA_PRINT_REG_FIELD(udma, " ", "\n", "%d", m2s, m2s_rd, 123 desc_pref_cfg_3, 124 pref_thr, 125 UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR); 126 127 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rd, data_cfg); 128 } 129 130 static void al_udma_regs_m2s_dwrr_print(struct al_udma *udma) 131 { 132 al_dbg("M2S DWRR regs:\n"); 133 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_dwrr, cfg_sched); 134 } 135 136 static void al_udma_regs_m2s_rate_limiter_print(struct al_udma *udma) 137 { 138 al_dbg("M2S rate limiter regs:\n"); 139 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rate_limiter, gen_cfg); 140 } 141 142 static void al_udma_regs_m2s_stream_rate_limiter_print(struct al_udma *udma) 143 { 144 al_dbg("M2S stream rate limiter regs:\n"); 145 146 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter, 147 rlimit.cfg_1s); 148 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter, 149 rlimit.cfg_cycle); 150 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter, 151 rlimit.cfg_token_size_1); 152 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter, 153 rlimit.cfg_token_size_2); 154 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter, 155 rlimit.mask); 156 } 157 158 static void al_udma_regs_m2s_comp_print(struct al_udma *udma) 159 { 160 al_dbg("M2S completion regs:\n"); 161 162 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_comp, cfg_1c); 163 164 AL_UDMA_PRINT_REG_FIELD(udma, " ", "\n", "%d", m2s, m2s_comp, cfg_1c, 165 comp_fifo_depth, 166 UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH); 167 AL_UDMA_PRINT_REG_FIELD(udma, " ", "\n", "%d", m2s, m2s_comp, cfg_1c, 168 unack_fifo_depth, 169 UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH); 170 AL_UDMA_PRINT_REG_BIT(udma, " ", "\n", m2s, m2s_comp, cfg_1c, 171 q_promotion, 172 UDMA_M2S_COMP_CFG_1C_Q_PROMOTION); 173 AL_UDMA_PRINT_REG_BIT(udma, " ", "\n", m2s, m2s_comp, cfg_1c, 174 force_rr, 175 UDMA_M2S_COMP_CFG_1C_FORCE_RR); 176 AL_UDMA_PRINT_REG_FIELD(udma, " ", "\n", "%d", m2s, m2s_comp, cfg_1c, 177 q_free_min, 178 UDMA_M2S_COMP_CFG_1C_Q_FREE_MIN); 179 180 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_comp, cfg_coal); 181 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_comp, cfg_application_ack); 182 } 183 184 static void al_udma_regs_m2s_stat_print(struct al_udma *udma) 185 { 186 al_dbg("M2S statistics regs:\n"); 187 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, cfg_st); 188 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, tx_pkt); 189 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, tx_bytes_low); 190 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, tx_bytes_high); 191 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, prefed_desc); 192 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, comp_pkt); 193 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, comp_desc); 194 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, ack_pkts); 195 } 196 197 static void al_udma_regs_m2s_feature_print(struct al_udma *udma) 198 { 199 al_dbg("M2S feature regs:\n"); 200 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_feature, reg_1); 201 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_feature, reg_3); 202 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_feature, reg_4); 203 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_feature, reg_5); 204 } 205 206 static void al_udma_regs_m2s_q_print(struct al_udma *udma, uint32_t qid) 207 { 208 al_dbg("M2S Q[%d] status regs:\n", qid); 209 al_reg_write32(&udma->udma_regs->m2s.m2s.indirect_ctrl, qid); 210 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, sel_pref_fifo_status); 211 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, sel_comp_fifo_status); 212 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, sel_rate_limit_status); 213 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, sel_dwrr_status); 214 215 al_dbg("M2S Q[%d] regs:\n", qid); 216 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], cfg); 217 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], status); 218 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrbp_low); 219 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrbp_high); 220 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrl); 221 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrhp); 222 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrtp); 223 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdcp); 224 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tcrbp_low); 225 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tcrbp_high); 226 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tcrhp); 227 228 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], rlimit.cfg_1s); 229 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], rlimit.cfg_cycle); 230 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], 231 rlimit.cfg_token_size_1); 232 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], 233 rlimit.cfg_token_size_2); 234 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], rlimit.mask); 235 236 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], dwrr_cfg_1); 237 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], dwrr_cfg_2); 238 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], dwrr_cfg_3); 239 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], comp_cfg); 240 AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], q_tx_pkt); 241 } 242 243 static void al_udma_regs_s2m_axi_print(struct al_udma *udma) 244 { 245 al_dbg("S2M AXI regs:\n"); 246 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, data_wr_cfg_1); 247 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, data_wr_cfg_2); 248 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, desc_rd_cfg_4); 249 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, desc_rd_cfg_5); 250 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, comp_wr_cfg_1); 251 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, comp_wr_cfg_2); 252 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, data_wr_cfg); 253 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, desc_rd_cfg_3); 254 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, desc_wr_cfg_1); 255 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, ostand_cfg_rd); 256 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, ostand_cfg_wr); 257 } 258 259 static void al_udma_regs_s2m_general_print(struct al_udma *udma) 260 { 261 al_dbg("S2M general regs:\n"); 262 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, state); 263 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, err_log_mask); 264 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, log_0); 265 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, log_1); 266 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, log_2); 267 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, log_3); 268 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, s_data_fifo_status); 269 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, s_header_fifo_status); 270 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, axi_data_fifo_status); 271 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, unack_fifo_status); 272 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, check_en); 273 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, fifo_en); 274 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, stream_cfg); 275 } 276 277 static void al_udma_regs_s2m_rd_print(struct al_udma *udma) 278 { 279 al_dbg("S2M read regs:\n"); 280 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_rd, desc_pref_cfg_1); 281 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_rd, desc_pref_cfg_2); 282 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_rd, desc_pref_cfg_3); 283 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_rd, desc_pref_cfg_4); 284 } 285 286 static void al_udma_regs_s2m_wr_print(struct al_udma *udma) 287 { 288 al_dbg("S2M write regs:\n"); 289 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_wr, data_cfg_1); 290 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_wr, data_cfg_1); 291 } 292 293 static void al_udma_regs_s2m_comp_print(struct al_udma *udma) 294 { 295 al_dbg("S2M completion regs:\n"); 296 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_comp, cfg_1c); 297 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_comp, cfg_2c); 298 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_comp, cfg_application_ack); 299 } 300 301 static void al_udma_regs_s2m_stat_print(struct al_udma *udma) 302 { 303 al_dbg("S2M statistics regs:\n"); 304 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, drop_pkt); 305 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, rx_bytes_low); 306 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, rx_bytes_high); 307 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, prefed_desc); 308 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, comp_pkt); 309 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, comp_desc); 310 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, ack_pkts); 311 } 312 313 static void al_udma_regs_s2m_feature_print(struct al_udma *udma) 314 { 315 al_dbg("S2M feature regs:\n"); 316 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_1); 317 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_3); 318 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_4); 319 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_5); 320 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_6); 321 } 322 323 static void al_udma_regs_s2m_q_print(struct al_udma *udma, uint32_t qid) 324 { 325 al_dbg("S2M Q[%d] status regs:\n", qid); 326 al_reg_write32(&udma->udma_regs->m2s.m2s.indirect_ctrl, qid); 327 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, sel_pref_fifo_status); 328 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, sel_comp_fifo_status); 329 330 al_dbg("S2M Q[%d] regs:\n", qid); 331 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], cfg); 332 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], status); 333 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrbp_low); 334 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrbp_high); 335 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrl); 336 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrhp); 337 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrtp); 338 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdcp); 339 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rcrbp_low); 340 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rcrbp_high); 341 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rcrhp); 342 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rcrhp_internal); 343 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], comp_cfg); 344 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], comp_cfg_2); 345 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], pkt_cfg); 346 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], qos_cfg); 347 AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], q_rx_pkt); 348 } 349 350 void al_udma_regs_print(struct al_udma *udma, unsigned int mask) 351 { 352 uint32_t i; 353 354 if (!udma) 355 return; 356 357 if (udma->type == UDMA_TX) { 358 if (mask & AL_UDMA_DEBUG_AXI) 359 al_udma_regs_m2s_axi_print(udma); 360 if (mask & AL_UDMA_DEBUG_GENERAL) 361 al_udma_regs_m2s_general_print(udma); 362 if (mask & AL_UDMA_DEBUG_READ) 363 al_udma_regs_m2s_rd_print(udma); 364 if (mask & AL_UDMA_DEBUG_DWRR) 365 al_udma_regs_m2s_dwrr_print(udma); 366 if (mask & AL_UDMA_DEBUG_RATE_LIMITER) 367 al_udma_regs_m2s_rate_limiter_print(udma); 368 if (mask & AL_UDMA_DEBUG_STREAM_RATE_LIMITER) 369 al_udma_regs_m2s_stream_rate_limiter_print(udma); 370 if (mask & AL_UDMA_DEBUG_COMP) 371 al_udma_regs_m2s_comp_print(udma); 372 if (mask & AL_UDMA_DEBUG_STAT) 373 al_udma_regs_m2s_stat_print(udma); 374 if (mask & AL_UDMA_DEBUG_FEATURE) 375 al_udma_regs_m2s_feature_print(udma); 376 for (i = 0; i < DMA_MAX_Q; i++) { 377 if (mask & AL_UDMA_DEBUG_QUEUE(i)) 378 al_udma_regs_m2s_q_print(udma, i); 379 } 380 } else { 381 if (mask & AL_UDMA_DEBUG_AXI) 382 al_udma_regs_s2m_axi_print(udma); 383 if (mask & AL_UDMA_DEBUG_GENERAL) 384 al_udma_regs_s2m_general_print(udma); 385 if (mask & AL_UDMA_DEBUG_READ) 386 al_udma_regs_s2m_rd_print(udma); 387 if (mask & AL_UDMA_DEBUG_WRITE) 388 al_udma_regs_s2m_wr_print(udma); 389 if (mask & AL_UDMA_DEBUG_COMP) 390 al_udma_regs_s2m_comp_print(udma); 391 if (mask & AL_UDMA_DEBUG_STAT) 392 al_udma_regs_s2m_stat_print(udma); 393 if (mask & AL_UDMA_DEBUG_FEATURE) 394 al_udma_regs_s2m_feature_print(udma); 395 for (i = 0; i < DMA_MAX_Q; i++) { 396 if (mask & AL_UDMA_DEBUG_QUEUE(i)) 397 al_udma_regs_s2m_q_print(udma, i); 398 } 399 } 400 } 401 402 void al_udma_q_struct_print(struct al_udma *udma, uint32_t qid) 403 { 404 struct al_udma_q *queue; 405 406 if (!udma) 407 return; 408 409 if (qid >= DMA_MAX_Q) 410 return; 411 412 queue = &udma->udma_q[qid]; 413 414 al_dbg("Q[%d] struct:\n", qid); 415 al_dbg(" size_mask = 0x%08x\n", (uint32_t)queue->size_mask); 416 al_dbg(" q_regs = %p\n", queue->q_regs); 417 al_dbg(" desc_base_ptr = %p\n", queue->desc_base_ptr); 418 al_dbg(" next_desc_idx = %d\n", (uint16_t)queue->next_desc_idx); 419 al_dbg(" desc_ring_id = %d\n", (uint32_t)queue->desc_ring_id); 420 al_dbg(" cdesc_base_ptr = %p\n", queue->cdesc_base_ptr); 421 al_dbg(" cdesc_size = %d\n", (uint32_t)queue->cdesc_size); 422 al_dbg(" next_cdesc_idx = %d\n", (uint16_t)queue->next_cdesc_idx); 423 al_dbg(" end_cdesc_ptr = %p\n", queue->end_cdesc_ptr); 424 al_dbg(" comp_head_idx = %d\n", (uint16_t)queue->comp_head_idx); 425 al_dbg(" comp_head_ptr = %p\n", queue->comp_head_ptr); 426 al_dbg(" pkt_crnt_descs = %d\n", (uint32_t)queue->pkt_crnt_descs); 427 al_dbg(" comp_ring_id = %d\n", (uint32_t)queue->comp_ring_id); 428 al_dbg(" desc_phy_base = 0x%016jx\n", (uintmax_t)queue->desc_phy_base); 429 al_dbg(" cdesc_phy_base = 0x%016jx\n", 430 (uintmax_t)queue->cdesc_phy_base); 431 al_dbg(" flags = 0x%08x\n", (uint32_t)queue->flags); 432 al_dbg(" size = %d\n", (uint32_t)queue->size); 433 al_dbg(" status = %d\n", (uint32_t)queue->status); 434 al_dbg(" udma = %p\n", queue->udma); 435 al_dbg(" qid = %d\n", (uint32_t)queue->qid); 436 } 437 438 void al_udma_ring_print(struct al_udma *udma, uint32_t qid, 439 enum al_udma_ring_type rtype) 440 { 441 struct al_udma_q *queue; 442 uint32_t desc_size; 443 void *base_ptr; 444 uint32_t i; 445 446 if (!udma) 447 return; 448 449 if (qid >= DMA_MAX_Q) 450 return; 451 452 queue = &udma->udma_q[qid]; 453 if (rtype == AL_RING_SUBMISSION) { 454 base_ptr = queue->desc_base_ptr; 455 desc_size = sizeof(union al_udma_desc); 456 if (base_ptr) 457 al_dbg("Q[%d] submission ring pointers:\n", qid); 458 else { 459 al_dbg("Q[%d] submission ring is not allocated\n", qid); 460 return; 461 } 462 } else { 463 base_ptr = queue->cdesc_base_ptr; 464 desc_size = queue->cdesc_size; 465 if (base_ptr) 466 al_dbg("Q[%d] completion ring pointers:\n", qid); 467 else { 468 al_dbg("Q[%d] completion ring is not allocated\n", qid); 469 return; 470 } 471 } 472 473 for (i = 0; i < queue->size; i++) { 474 uint32_t *curr_addr = (void*)((uintptr_t)base_ptr + i * desc_size); 475 if (desc_size == 16) 476 al_dbg("[%04d](%p): %08x %08x %08x %08x\n", 477 i, 478 curr_addr, 479 (uint32_t)*curr_addr, 480 (uint32_t)*(curr_addr+1), 481 (uint32_t)*(curr_addr+2), 482 (uint32_t)*(curr_addr+3)); 483 else if (desc_size == 8) 484 al_dbg("[%04d](%p): %08x %08x\n", 485 i, 486 curr_addr, 487 (uint32_t)*curr_addr, 488 (uint32_t)*(curr_addr+1)); 489 else if (desc_size == 4) 490 al_dbg("[%04d](%p): %08x\n", 491 i, 492 curr_addr, 493 (uint32_t)*curr_addr); 494 else 495 break; 496 } 497 }
Cache object: 7e7bf7b6b2e024bf55855dfb7c1baf24
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