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sys/contrib/alpine-hal/eth/al_hal_eth_mac_regs.h
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1 /*- 2 ******************************************************************************* 3 Copyright (C) 2015 Annapurna Labs Ltd. 4 5 This file may be licensed under the terms of the Annapurna Labs Commercial 6 License Agreement. 7 8 Alternatively, this file can be distributed under the terms of the GNU General 9 Public License V2 as published by the Free Software Foundation and can be 10 found at http://www.gnu.org/licenses/gpl-2.0.html 11 12 Alternatively, redistribution and use in source and binary forms, with or 13 without modification, are permitted provided that the following conditions are 14 met: 15 16 * Redistributions of source code must retain the above copyright notice, 17 this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20 notice, this list of conditions and the following disclaimer in 21 the documentation and/or other materials provided with the 22 distribution. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35 *******************************************************************************/ 36 37 /** 38 * @{ 39 * @file al_hal_eth_mac_regs.h 40 * 41 * @brief Ethernet MAC registers 42 * 43 */ 44 45 #ifndef __AL_HAL_ETH_MAC_REGS_H__ 46 #define __AL_HAL_ETH_MAC_REGS_H__ 47 48 #include "al_hal_plat_types.h" 49 50 #ifdef __cplusplus 51 extern "C" { 52 #endif 53 /* 54 * Unit Registers 55 */ 56 57 struct al_eth_mac_1g_stats { 58 uint32_t reserved1[2]; 59 uint32_t aFramesTransmittedOK; /* 0x68 */ 60 uint32_t aFramesReceivedOK; /* 0x6c */ 61 uint32_t aFrameCheckSequenceErrors; /* 0x70 */ 62 uint32_t aAlignmentErrors; /* 0x74 */ 63 uint32_t aOctetsTransmittedOK; /* 0x78 */ 64 uint32_t aOctetsReceivedOK; /* 0x7c */ 65 uint32_t aPAUSEMACCtrlFramesTransmitted; /* 0x80 */ 66 uint32_t aPAUSEMACCtrlFramesReceived; /* 0x84 */ 67 uint32_t ifInErrors ; /* 0x88 */ 68 uint32_t ifOutErrors; /* 0x8c */ 69 uint32_t ifInUcastPkts; /* 0x90 */ 70 uint32_t ifInMulticastPkts; /* 0x94 */ 71 uint32_t ifInBroadcastPkts; /* 0x98 */ 72 uint32_t reserved2; 73 uint32_t ifOutUcastPkts; /* 0xa0 */ 74 uint32_t ifOutMulticastPkts; /* 0xa4 */ 75 uint32_t ifOutBroadcastPkts; /* 0xa8 */ 76 uint32_t etherStatsDropEvents; /* 0xac */ 77 uint32_t etherStatsOctets; /* 0xb0 */ 78 uint32_t etherStatsPkts; /* 0xb4 */ 79 uint32_t etherStatsUndersizePkts; /* 0xb8 */ 80 uint32_t etherStatsOversizePkts; /* 0xbc */ 81 uint32_t etherStatsPkts64Octets; /* 0xc0 */ 82 uint32_t etherStatsPkts65to127Octets; /* 0xc4 */ 83 uint32_t etherStatsPkts128to255Octets; /* 0xc8 */ 84 uint32_t etherStatsPkts256to511Octets; /* 0xcc */ 85 uint32_t etherStatsPkts512to1023Octets; /* 0xd0 */ 86 uint32_t etherStatsPkts1024to1518Octets; /* 0xd4 */ 87 uint32_t etherStatsPkts1519toX; /* 0xd8 */ 88 uint32_t etherStatsJabbers; /* 0xdc */ 89 uint32_t etherStatsFragments; /* 0xe0 */ 90 uint32_t reserved3[71]; 91 }; 92 93 struct al_eth_mac_1g { 94 /* [0x0] */ 95 uint32_t rev; 96 uint32_t scratch; 97 uint32_t cmd_cfg; 98 uint32_t mac_0; 99 /* [0x10] */ 100 uint32_t mac_1; 101 uint32_t frm_len; 102 uint32_t pause_quant; 103 uint32_t rx_section_empty; 104 /* [0x20] */ 105 uint32_t rx_section_full; 106 uint32_t tx_section_empty; 107 uint32_t tx_section_full; 108 uint32_t rx_almost_empty; 109 /* [0x30] */ 110 uint32_t rx_almost_full; 111 uint32_t tx_almost_empty; 112 uint32_t tx_almost_full; 113 uint32_t mdio_addr0; 114 /* [0x40] */ 115 uint32_t mdio_addr1; 116 uint32_t Reserved[5]; 117 /* [0x58] */ 118 uint32_t reg_stat; 119 uint32_t tx_ipg_len; 120 /* [0x60] */ 121 struct al_eth_mac_1g_stats stats; 122 /* [0x200] */ 123 uint32_t phy_regs_base; 124 uint32_t Reserved2[127]; 125 }; 126 127 struct al_eth_mac_10g_stats_v2 { 128 uint32_t aFramesTransmittedOK; /* 0x80 */ 129 uint32_t reserved1; 130 uint32_t aFramesReceivedOK; /* 0x88 */ 131 uint32_t reserved2; 132 uint32_t aFrameCheckSequenceErrors; /* 0x90 */ 133 uint32_t reserved3; 134 uint32_t aAlignmentErrors; /* 0x98 */ 135 uint32_t reserved4; 136 uint32_t aPAUSEMACCtrlFramesTransmitted; /* 0xa0 */ 137 uint32_t reserved5; 138 uint32_t aPAUSEMACCtrlFramesReceived; /* 0xa8 */ 139 uint32_t reserved6; 140 uint32_t aFrameTooLongErrors; /* 0xb0 */ 141 uint32_t reserved7; 142 uint32_t aInRangeLengthErrors; /* 0xb8 */ 143 uint32_t reserved8; 144 uint32_t VLANTransmittedOK; /* 0xc0 */ 145 uint32_t reserved9; 146 uint32_t VLANReceivedOK; /* 0xc8 */ 147 uint32_t reserved10; 148 uint32_t ifOutOctetsL; /* 0xd0 */ 149 uint32_t ifOutOctetsH; /* 0xd4 */ 150 uint32_t ifInOctetsL; /* 0xd8 */ 151 uint32_t ifInOctetsH; /* 0xdc */ 152 uint32_t ifInUcastPkts; /* 0xe0 */ 153 uint32_t reserved11; 154 uint32_t ifInMulticastPkts; /* 0xe8 */ 155 uint32_t reserved12; 156 uint32_t ifInBroadcastPkts; /* 0xf0 */ 157 uint32_t reserved13; 158 uint32_t ifOutErrors; /* 0xf8 */ 159 uint32_t reserved14[3]; 160 uint32_t ifOutUcastPkts; /* 0x108 */ 161 uint32_t reserved15; 162 uint32_t ifOutMulticastPkts; /* 0x110 */ 163 uint32_t reserved16; 164 uint32_t ifOutBroadcastPkts; /* 0x118 */ 165 uint32_t reserved17; 166 uint32_t etherStatsDropEvents; /* 0x120 */ 167 uint32_t reserved18; 168 uint32_t etherStatsOctets; /* 0x128 */ 169 uint32_t reserved19; 170 uint32_t etherStatsPkts; /* 0x130 */ 171 uint32_t reserved20; 172 uint32_t etherStatsUndersizePkts; /* 0x138 */ 173 uint32_t reserved21; 174 uint32_t etherStatsPkts64Octets; /* 0x140 */ 175 uint32_t reserved22; 176 uint32_t etherStatsPkts65to127Octets; /* 0x148 */ 177 uint32_t reserved23; 178 uint32_t etherStatsPkts128to255Octets; /* 0x150 */ 179 uint32_t reserved24; 180 uint32_t etherStatsPkts256to511Octets; /* 0x158 */ 181 uint32_t reserved25; 182 uint32_t etherStatsPkts512to1023Octets; /* 0x160 */ 183 uint32_t reserved26; 184 uint32_t etherStatsPkts1024to1518Octets; /* 0x168 */ 185 uint32_t reserved27; 186 uint32_t etherStatsPkts1519toX; /* 0x170 */ 187 uint32_t reserved28; 188 uint32_t etherStatsOversizePkts; /* 0x178 */ 189 uint32_t reserved29; 190 uint32_t etherStatsJabbers; /* 0x180 */ 191 uint32_t reserved30; 192 uint32_t etherStatsFragments; /* 0x188 */ 193 uint32_t reserved31; 194 uint32_t ifInErrors; /* 0x190 */ 195 uint32_t reserved32[91]; 196 }; 197 198 struct al_eth_mac_10g_stats_v3_rx { 199 uint32_t etherStatsOctets; /* 0x00 */ 200 uint32_t reserved2; 201 uint32_t ifOctetsL; /* 0x08 */ 202 uint32_t ifOctetsH; /* 0x0c */ 203 uint32_t aAlignmentErrors; /* 0x10 */ 204 uint32_t reserved4; 205 uint32_t aPAUSEMACCtrlFrames; /* 0x18 */ 206 uint32_t reserved5; 207 uint32_t FramesOK; /* 0x20 */ 208 uint32_t reserved6; 209 uint32_t CRCErrors; /* 0x28 */ 210 uint32_t reserved7; 211 uint32_t VLANOK; /* 0x30 */ 212 uint32_t reserved8; 213 uint32_t ifInErrors; /* 0x38 */ 214 uint32_t reserved9; 215 uint32_t ifInUcastPkts; /* 0x40 */ 216 uint32_t reserved10; 217 uint32_t ifInMulticastPkts; /* 0x48 */ 218 uint32_t reserved11; 219 uint32_t ifInBroadcastPkts; /* 0x50 */ 220 uint32_t reserved12; 221 uint32_t etherStatsDropEvents; /* 0x58 */ 222 uint32_t reserved13; 223 uint32_t etherStatsPkts; /* 0x60 */ 224 uint32_t reserved14; 225 uint32_t etherStatsUndersizePkts; /* 0x68 */ 226 uint32_t reserved15; 227 uint32_t etherStatsPkts64Octets; /* 0x70 */ 228 uint32_t reserved16; 229 uint32_t etherStatsPkts65to127Octets; /* 0x78 */ 230 uint32_t reserved17; 231 uint32_t etherStatsPkts128to255Octets; /* 0x80 */ 232 uint32_t reserved18; 233 uint32_t etherStatsPkts256to511Octets; /* 0x88 */ 234 uint32_t reserved19; 235 uint32_t etherStatsPkts512to1023Octets; /* 0x90 */ 236 uint32_t reserved20; 237 uint32_t etherStatsPkts1024to1518Octets; /* 0x98 */ 238 uint32_t reserved21; 239 uint32_t etherStatsPkts1519toMax; /* 0xa0 */ 240 uint32_t reserved22; 241 uint32_t etherStatsOversizePkts; /* 0xa8 */ 242 uint32_t reserved23; 243 uint32_t etherStatsJabbers; /* 0xb0 */ 244 uint32_t reserved24; 245 uint32_t etherStatsFragments; /* 0xb8 */ 246 uint32_t reserved25; 247 uint32_t aMACControlFramesReceived; /* 0xc0 */ 248 uint32_t reserved26; 249 uint32_t aFrameTooLong; /* 0xc8 */ 250 uint32_t reserved27; 251 uint32_t aInRangeLengthErrors; /* 0xd0 */ 252 uint32_t reserved28; 253 uint32_t reserved29[10]; 254 }; 255 256 struct al_eth_mac_10g_stats_v3_tx { 257 uint32_t etherStatsOctets; /* 0x00 */ 258 uint32_t reserved30; 259 uint32_t ifOctetsL; /* 0x08 */ 260 uint32_t ifOctetsH; /* 0x0c */ 261 uint32_t aAlignmentErrors; /* 0x10 */ 262 uint32_t reserved32; 263 uint32_t aPAUSEMACCtrlFrames; /* 0x18 */ 264 uint32_t reserved33; 265 uint32_t FramesOK; /* 0x20 */ 266 uint32_t reserved34; 267 uint32_t CRCErrors; /* 0x28 */ 268 uint32_t reserved35; 269 uint32_t VLANOK; /* 0x30 */ 270 uint32_t reserved36; 271 uint32_t ifOutErrors; /* 0x38 */ 272 uint32_t reserved37; 273 uint32_t ifUcastPkts; /* 0x40 */ 274 uint32_t reserved38; 275 uint32_t ifMulticastPkts; /* 0x48 */ 276 uint32_t reserved39; 277 uint32_t ifBroadcastPkts; /* 0x50 */ 278 uint32_t reserved40; 279 uint32_t etherStatsDropEvents; /* 0x58 */ 280 uint32_t reserved41; 281 uint32_t etherStatsPkts; /* 0x60 */ 282 uint32_t reserved42; 283 uint32_t etherStatsUndersizePkts; /* 0x68 */ 284 uint32_t reserved43; 285 uint32_t etherStatsPkts64Octets; /* 0x70 */ 286 uint32_t reserved44; 287 uint32_t etherStatsPkts65to127Octets; /* 0x78 */ 288 uint32_t reserved45; 289 uint32_t etherStatsPkts128to255Octets; /* 0x80 */ 290 uint32_t reserved46; 291 uint32_t etherStatsPkts256to511Octets; /* 0x88 */ 292 uint32_t reserved47; 293 uint32_t etherStatsPkts512to1023Octets; /* 0x90 */ 294 uint32_t reserved48; 295 uint32_t etherStatsPkts1024to1518Octets; /* 0x98 */ 296 uint32_t reserved49; 297 uint32_t etherStatsPkts1519toTX_MTU; /* 0xa0 */ 298 uint32_t reserved50; 299 uint32_t reserved51[4]; 300 uint32_t aMACControlFrames; /* 0xc0 */ 301 uint32_t reserved52[15]; 302 }; 303 304 struct al_eth_mac_10g_stats_v3 { 305 uint32_t reserved1[32]; 306 /* 0x100 */ 307 struct al_eth_mac_10g_stats_v3_rx rx; 308 /* 0x200 */ 309 struct al_eth_mac_10g_stats_v3_tx tx; 310 }; 311 312 union al_eth_mac_10g_stats { 313 struct al_eth_mac_10g_stats_v2 v2; 314 struct al_eth_mac_10g_stats_v3 v3; 315 }; 316 317 struct al_eth_mac_10g { 318 /* [0x0] */ 319 uint32_t rev; 320 uint32_t scratch; 321 uint32_t cmd_cfg; 322 uint32_t mac_0; 323 /* [0x10] */ 324 uint32_t mac_1; 325 uint32_t frm_len; 326 uint32_t Reserved; 327 uint32_t rx_fifo_sections; 328 /* [0x20] */ 329 uint32_t tx_fifo_sections; 330 uint32_t rx_fifo_almost_f_e; 331 uint32_t tx_fifo_almost_f_e; 332 uint32_t hashtable_load; 333 /* [0x30] */ 334 uint32_t mdio_cfg_status; 335 uint16_t mdio_cmd; 336 uint16_t reserved1; 337 uint16_t mdio_data; 338 uint16_t reserved2; 339 uint16_t mdio_regaddr; 340 uint16_t reserved3; 341 /* [0x40] */ 342 uint32_t status; 343 uint32_t tx_ipg_len; 344 uint32_t Reserved1[3]; 345 /* [0x54] */ 346 uint32_t cl01_pause_quanta; 347 uint32_t cl23_pause_quanta; 348 uint32_t cl45_pause_quanta; 349 /* [0x60] */ 350 uint32_t cl67_pause_quanta; 351 uint32_t cl01_quanta_thresh; 352 uint32_t cl23_quanta_thresh; 353 uint32_t cl45_quanta_thresh; 354 /* [0x70] */ 355 uint32_t cl67_quanta_thresh; 356 uint32_t rx_pause_status; 357 uint32_t Reserved2; 358 uint32_t ts_timestamp; 359 /* [0x80] */ 360 union al_eth_mac_10g_stats stats; 361 362 /* [0x300] */ 363 uint32_t control; 364 uint32_t status_reg; 365 uint32_t phy_id[2]; 366 /* [0x310] */ 367 uint32_t dev_ability; 368 uint32_t partner_ability; 369 uint32_t an_expansion; 370 uint32_t device_np; 371 /* [0x320] */ 372 uint32_t partner_np; 373 uint32_t Reserved4[9]; 374 375 /* [0x348] */ 376 uint32_t link_timer_lo; 377 uint32_t link_timer_hi; 378 /* [0x350] */ 379 uint32_t if_mode; 380 381 uint32_t Reserved5[43]; 382 }; 383 384 struct al_eth_mac_gen { 385 /* [0x0] Ethernet Controller Version */ 386 uint32_t version; 387 uint32_t rsrvd_0[2]; 388 /* [0xc] MAC selection configuration */ 389 uint32_t cfg; 390 /* [0x10] 10/100/1000 MAC external configuration */ 391 uint32_t mac_1g_cfg; 392 /* [0x14] 10/100/1000 MAC status */ 393 uint32_t mac_1g_stat; 394 /* [0x18] RGMII external configuration */ 395 uint32_t rgmii_cfg; 396 /* [0x1c] RGMII status */ 397 uint32_t rgmii_stat; 398 /* [0x20] 1/2.5/10G MAC external configuration */ 399 uint32_t mac_10g_cfg; 400 /* [0x24] 1/2.5/10G MAC status */ 401 uint32_t mac_10g_stat; 402 /* [0x28] XAUI PCS configuration */ 403 uint32_t xaui_cfg; 404 /* [0x2c] XAUI PCS status */ 405 uint32_t xaui_stat; 406 /* [0x30] RXAUI PCS configuration */ 407 uint32_t rxaui_cfg; 408 /* [0x34] RXAUI PCS status */ 409 uint32_t rxaui_stat; 410 /* [0x38] Signal detect configuration */ 411 uint32_t sd_cfg; 412 /* [0x3c] MDIO control register for MDIO interface 1 */ 413 uint32_t mdio_ctrl_1; 414 /* [0x40] MDIO information register for MDIO interface 1 */ 415 uint32_t mdio_1; 416 /* [0x44] MDIO control register for MDIO interface 2 */ 417 uint32_t mdio_ctrl_2; 418 /* [0x48] MDIO information register for MDIO interface 2 */ 419 uint32_t mdio_2; 420 /* [0x4c] XGMII 32 to 64 data FIFO control */ 421 uint32_t xgmii_dfifo_32_64; 422 /* [0x50] Reserved 1 out */ 423 uint32_t mac_res_1_out; 424 /* [0x54] XGMII 64 to 32 data FIFO control */ 425 uint32_t xgmii_dfifo_64_32; 426 /* [0x58] Reserved 1 in */ 427 uint32_t mac_res_1_in; 428 /* [0x5c] SerDes TX FIFO control */ 429 uint32_t sd_fifo_ctrl; 430 /* [0x60] SerDes TX FIFO status */ 431 uint32_t sd_fifo_stat; 432 /* [0x64] SerDes in/out selection */ 433 uint32_t mux_sel; 434 /* [0x68] Clock configuration */ 435 uint32_t clk_cfg; 436 uint32_t rsrvd_1; 437 /* [0x70] LOS and SD selection */ 438 uint32_t los_sel; 439 /* [0x74] RGMII selection configuration */ 440 uint32_t rgmii_sel; 441 /* [0x78] Ethernet LED configuration */ 442 uint32_t led_cfg; 443 uint32_t rsrvd[33]; 444 }; 445 struct al_eth_mac_kr { 446 /* [0x0] PCS register file address */ 447 uint32_t pcs_addr; 448 /* [0x4] PCS register file data */ 449 uint32_t pcs_data; 450 /* [0x8] AN register file address */ 451 uint32_t an_addr; 452 /* [0xc] AN register file data */ 453 uint32_t an_data; 454 /* [0x10] PMA register file address */ 455 uint32_t pma_addr; 456 /* [0x14] PMA register file data */ 457 uint32_t pma_data; 458 /* [0x18] MTIP register file address */ 459 uint32_t mtip_addr; 460 /* [0x1c] MTIP register file data */ 461 uint32_t mtip_data; 462 /* [0x20] KR PCS config */ 463 uint32_t pcs_cfg; 464 /* [0x24] KR PCS status */ 465 uint32_t pcs_stat; 466 uint32_t rsrvd[54]; 467 }; 468 struct al_eth_mac_sgmii { 469 /* [0x0] PCS register file address */ 470 uint32_t reg_addr; 471 /* [0x4] PCS register file data */ 472 uint32_t reg_data; 473 /* [0x8] PCS clock divider configuration */ 474 uint32_t clk_div; 475 /* [0xc] PCS Status */ 476 uint32_t link_stat; 477 uint32_t rsrvd[60]; 478 }; 479 struct al_eth_mac_stat { 480 /* [0x0] Receive rate matching error */ 481 uint32_t match_fault; 482 /* [0x4] EEE, number of times the MAC went into low power mode */ 483 uint32_t eee_in; 484 /* [0x8] EEE, number of times the MAC went out of low power mode */ 485 uint32_t eee_out; 486 /* 487 * [0xc] 40G PCS, 488 * FEC corrected error indication 489 */ 490 uint32_t v3_pcs_40g_ll_cerr_0; 491 /* 492 * [0x10] 40G PCS, 493 * FEC corrected error indication 494 */ 495 uint32_t v3_pcs_40g_ll_cerr_1; 496 /* 497 * [0x14] 40G PCS, 498 * FEC corrected error indication 499 */ 500 uint32_t v3_pcs_40g_ll_cerr_2; 501 /* 502 * [0x18] 40G PCS, 503 * FEC corrected error indication 504 */ 505 uint32_t v3_pcs_40g_ll_cerr_3; 506 /* 507 * [0x1c] 40G PCS, 508 * FEC uncorrectable error indication 509 */ 510 uint32_t v3_pcs_40g_ll_ncerr_0; 511 /* 512 * [0x20] 40G PCS, 513 * FEC uncorrectable error indication 514 */ 515 uint32_t v3_pcs_40g_ll_ncerr_1; 516 /* 517 * [0x24] 40G PCS, 518 * FEC uncorrectable error indication 519 */ 520 uint32_t v3_pcs_40g_ll_ncerr_2; 521 /* 522 * [0x28] 40G PCS, 523 * FEC uncorrectable error indication 524 */ 525 uint32_t v3_pcs_40g_ll_ncerr_3; 526 /* 527 * [0x2c] 10G_LL PCS, 528 * FEC corrected error indication 529 */ 530 uint32_t v3_pcs_10g_ll_cerr; 531 /* 532 * [0x30] 10G_LL PCS, 533 * FEC uncorrectable error indication 534 */ 535 uint32_t v3_pcs_10g_ll_ncerr; 536 uint32_t rsrvd[51]; 537 }; 538 struct al_eth_mac_stat_lane { 539 /* [0x0] Character error */ 540 uint32_t char_err; 541 /* [0x4] Disparity error */ 542 uint32_t disp_err; 543 /* [0x8] Comma detection */ 544 uint32_t pat; 545 uint32_t rsrvd[13]; 546 }; 547 struct al_eth_mac_gen_v3 { 548 /* [0x0] ASYNC FIFOs control */ 549 uint32_t afifo_ctrl; 550 /* [0x4] TX ASYNC FIFO configuration */ 551 uint32_t tx_afifo_cfg_1; 552 /* [0x8] TX ASYNC FIFO configuration */ 553 uint32_t tx_afifo_cfg_2; 554 /* [0xc] TX ASYNC FIFO configuration */ 555 uint32_t tx_afifo_cfg_3; 556 /* [0x10] TX ASYNC FIFO configuration */ 557 uint32_t tx_afifo_cfg_4; 558 /* [0x14] TX ASYNC FIFO configuration */ 559 uint32_t tx_afifo_cfg_5; 560 /* [0x18] RX ASYNC FIFO configuration */ 561 uint32_t rx_afifo_cfg_1; 562 /* [0x1c] RX ASYNC FIFO configuration */ 563 uint32_t rx_afifo_cfg_2; 564 /* [0x20] RX ASYNC FIFO configuration */ 565 uint32_t rx_afifo_cfg_3; 566 /* [0x24] RX ASYNC FIFO configuration */ 567 uint32_t rx_afifo_cfg_4; 568 /* [0x28] RX ASYNC FIFO configuration */ 569 uint32_t rx_afifo_cfg_5; 570 /* [0x2c] MAC selection configuration */ 571 uint32_t mac_sel; 572 /* [0x30] 10G LL MAC configuration */ 573 uint32_t mac_10g_ll_cfg; 574 /* [0x34] 10G LL MAC control */ 575 uint32_t mac_10g_ll_ctrl; 576 /* [0x38] 10G LL PCS configuration */ 577 uint32_t pcs_10g_ll_cfg; 578 /* [0x3c] 10G LL PCS status */ 579 uint32_t pcs_10g_ll_status; 580 /* [0x40] 40G LL PCS configuration */ 581 uint32_t pcs_40g_ll_cfg; 582 /* [0x44] 40G LL PCS status */ 583 uint32_t pcs_40g_ll_status; 584 /* [0x48] PCS 40G register file address */ 585 uint32_t pcs_40g_ll_addr; 586 /* [0x4c] PCS 40G register file data */ 587 uint32_t pcs_40g_ll_data; 588 /* [0x50] 40G LL MAC configuration */ 589 uint32_t mac_40g_ll_cfg; 590 /* [0x54] 40G LL MAC status */ 591 uint32_t mac_40g_ll_status; 592 /* [0x58] Preamble configuration (high [55:32]) */ 593 uint32_t preamble_cfg_high; 594 /* [0x5c] Preamble configuration (low [31:0]) */ 595 uint32_t preamble_cfg_low; 596 /* [0x60] MAC 40G register file address */ 597 uint32_t mac_40g_ll_addr; 598 /* [0x64] MAC 40G register file data */ 599 uint32_t mac_40g_ll_data; 600 /* [0x68] 40G LL MAC control */ 601 uint32_t mac_40g_ll_ctrl; 602 /* [0x6c] PCS 40G register file address */ 603 uint32_t pcs_40g_fec_91_ll_addr; 604 /* [0x70] PCS 40G register file data */ 605 uint32_t pcs_40g_fec_91_ll_data; 606 /* [0x74] 40G LL PCS EEE configuration */ 607 uint32_t pcs_40g_ll_eee_cfg; 608 /* [0x78] 40G LL PCS EEE status */ 609 uint32_t pcs_40g_ll_eee_status; 610 /* 611 * [0x7c] SERDES 32-bit interface shift configuration (when swap is 612 * enabled) 613 */ 614 uint32_t serdes_32_tx_shift; 615 /* 616 * [0x80] SERDES 32-bit interface shift configuration (when swap is 617 * enabled) 618 */ 619 uint32_t serdes_32_rx_shift; 620 /* 621 * [0x84] SERDES 32-bit interface bit selection 622 */ 623 uint32_t serdes_32_tx_sel; 624 /* 625 * [0x88] SERDES 32-bit interface bit selection 626 */ 627 uint32_t serdes_32_rx_sel; 628 /* [0x8c] AN/LT wrapper control */ 629 uint32_t an_lt_ctrl; 630 /* [0x90] AN/LT wrapper register file address */ 631 uint32_t an_lt_0_addr; 632 /* [0x94] AN/LT wrapper register file data */ 633 uint32_t an_lt_0_data; 634 /* [0x98] AN/LT wrapper register file address */ 635 uint32_t an_lt_1_addr; 636 /* [0x9c] AN/LT wrapper register file data */ 637 uint32_t an_lt_1_data; 638 /* [0xa0] AN/LT wrapper register file address */ 639 uint32_t an_lt_2_addr; 640 /* [0xa4] AN/LT wrapper register file data */ 641 uint32_t an_lt_2_data; 642 /* [0xa8] AN/LT wrapper register file address */ 643 uint32_t an_lt_3_addr; 644 /* [0xac] AN/LT wrapper register file data */ 645 uint32_t an_lt_3_data; 646 /* [0xb0] External SERDES control */ 647 uint32_t ext_serdes_ctrl; 648 /* [0xb4] spare bits */ 649 uint32_t spare; 650 uint32_t rsrvd[18]; 651 }; 652 653 struct al_eth_mac_regs { 654 struct al_eth_mac_1g mac_1g; /* [0x000] */ 655 struct al_eth_mac_10g mac_10g; /* [0x400] */ 656 uint32_t rsrvd_0[64]; /* [0x800] */ 657 struct al_eth_mac_gen gen; /* [0x900] */ 658 struct al_eth_mac_kr kr; /* [0xa00] */ 659 struct al_eth_mac_sgmii sgmii; /* [0xb00] */ 660 struct al_eth_mac_stat stat; /* [0xc00] */ 661 struct al_eth_mac_stat_lane stat_lane[4]; /* [0xd00] */ 662 struct al_eth_mac_gen_v3 gen_v3; /* [0xe00] */ 663 }; 664 665 666 /* 667 * Registers Fields 668 */ 669 670 /**** 1G MAC registers ****/ 671 /* cmd_cfg */ 672 #define ETH_1G_MAC_CMD_CFG_TX_ENA (1 << 0) 673 #define ETH_1G_MAC_CMD_CFG_RX_ENA (1 << 1) 674 /* enable Half Duplex */ 675 #define ETH_1G_MAC_CMD_CFG_HD_EN (1 << 10) 676 /* enable 1G speed */ 677 #define ETH_1G_MAC_CMD_CFG_1G_SPD (1 << 3) 678 /* enable 10M speed */ 679 #define ETH_1G_MAC_CMD_CFG_10M_SPD (1 << 25) 680 681 /**** 10G MAC registers ****/ 682 /* cmd_cfg */ 683 #define ETH_10G_MAC_CMD_CFG_TX_ENA (1 << 0) 684 #define ETH_10G_MAC_CMD_CFG_RX_ENA (1 << 1) 685 #define ETH_10G_MAC_CMD_CFG_WAN_MODE (1 << 3) 686 #define ETH_10G_MAC_CMD_CFG_PROMIS_EN (1 << 4) 687 #define ETH_10G_MAC_CMD_CFG_PAD_EN (1 << 5) 688 #define ETH_10G_MAC_CMD_CFG_CRC_FWD (1 << 6) 689 #define ETH_10G_MAC_CMD_CFG_PAUSE_FWD (1 << 7) 690 #define ETH_10G_MAC_CMD_CFG_PAUSE_IGNORE (1 << 8) 691 #define ETH_10G_MAC_CMD_CFG_TX_ADDR_INS (1 << 9) 692 #define ETH_10G_MAC_CMD_CFG_LOOP_ENA (1 << 10) 693 #define ETH_10G_MAC_CMD_CFG_TX_PAD_EN (1 << 11) 694 #define ETH_10G_MAC_CMD_CFG_SW_RESET (1 << 12) 695 #define ETH_10G_MAC_CMD_CFG_CNTL_FRM_ENA (1 << 13) 696 #define ETH_10G_MAC_CMD_CFG_RX_ERR_DISC (1 << 14) 697 #define ETH_10G_MAC_CMD_CFG_PHY_TXENA (1 << 15) 698 #define ETH_10G_MAC_CMD_CFG_FORCE_SEND_IDLE (1 << 16) 699 #define ETH_10G_MAC_CMD_CFG_NO_LGTH_CHECK (1 << 17) 700 #define ETH_10G_MAC_CMD_CFG_COL_CNT_EXT (1 << 18) 701 #define ETH_10G_MAC_CMD_CFG_PFC_MODE (1 << 19) 702 #define ETH_10G_MAC_CMD_CFG_PAUSE_PFC_COMP (1 << 20) 703 #define ETH_10G_MAC_CMD_CFG_SFD_ANY (1 << 21) 704 #define ETH_10G_MAC_CMD_CFG_TX_FLUSH (1 << 22) 705 #define ETH_10G_MAC_CMD_CFG_TX_LOWP_ENA (1 << 23) 706 #define ETH_10G_MAC_CMD_CFG_REG_LOWP_RXEMPTY (1 << 24) 707 #define ETH_10G_MAC_CMD_CFG_SHORT_DISCARD (1 << 25) 708 709 /* mdio_cfg_status */ 710 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_MASK 0x0000001c 711 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_SHIFT 2 712 713 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_1_CLK 0 714 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_3_CLK 1 715 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_5_CLK 2 716 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_7_CLK 3 717 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_9_CLK 4 718 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_11_CLK 5 719 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_13_CLK 6 720 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_15_CLK 7 721 722 /* control */ 723 #define ETH_10G_MAC_CONTROL_AN_EN_MASK 0x00001000 724 #define ETH_10G_MAC_CONTROL_AN_EN_SHIFT 12 725 726 /* if_mode */ 727 #define ETH_10G_MAC_IF_MODE_SGMII_EN_MASK 0x00000001 728 #define ETH_10G_MAC_IF_MODE_SGMII_EN_SHIFT 0 729 #define ETH_10G_MAC_IF_MODE_SGMII_AN_MASK 0x00000002 730 #define ETH_10G_MAC_IF_MODE_SGMII_AN_SHIFT 1 731 #define ETH_10G_MAC_IF_MODE_SGMII_SPEED_MASK 0x0000000c 732 #define ETH_10G_MAC_IF_MODE_SGMII_SPEED_SHIFT 2 733 #define ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_MASK 0x00000010 734 #define ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_SHIFT 4 735 736 #define ETH_10G_MAC_IF_MODE_SGMII_SPEED_10M 0 737 #define ETH_10G_MAC_IF_MODE_SGMII_SPEED_100M 1 738 #define ETH_10G_MAC_IF_MODE_SGMII_SPEED_1G 2 739 740 #define ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_FULL 0 741 #define ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_HALF 1 742 743 /**** version register ****/ 744 /* Revision number (Minor) */ 745 #define ETH_MAC_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF 746 #define ETH_MAC_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0 747 /* Revision number (Major) */ 748 #define ETH_MAC_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00 749 #define ETH_MAC_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8 750 /* Date of release */ 751 #define ETH_MAC_GEN_VERSION_DATE_DAY_MASK 0x001F0000 752 #define ETH_MAC_GEN_VERSION_DATE_DAY_SHIFT 16 753 /* Month of release */ 754 #define ETH_MAC_GEN_VERSION_DATA_MONTH_MASK 0x01E00000 755 #define ETH_MAC_GEN_VERSION_DATA_MONTH_SHIFT 21 756 /* Year of release (starting from 2000) */ 757 #define ETH_MAC_GEN_VERSION_DATE_YEAR_MASK 0x3E000000 758 #define ETH_MAC_GEN_VERSION_DATE_YEAR_SHIFT 25 759 /* Reserved */ 760 #define ETH_MAC_GEN_VERSION_RESERVED_MASK 0xC0000000 761 #define ETH_MAC_GEN_VERSION_RESERVED_SHIFT 30 762 763 /**** cfg register ****/ 764 /* 765 * Selects between the 10/100/1000 MAC and the 1/2.5/10G MAC: 766 * 0 - 10/100/1000 767 * 1 - 1/2.5/10G 768 */ 769 #define ETH_MAC_GEN_CFG_MAC_1_10 (1 << 0) 770 /* 771 * Selects the operation mode of the 1/2.5/10G MAC: 772 * 00 - 1/2.5G SGMII 773 * 01 - 10G XAUI/RXAUI 774 * 10 – 10G KR 775 * 11 – Reserved 776 */ 777 #define ETH_MAC_GEN_CFG_XGMII_SGMII_MASK 0x00000006 778 #define ETH_MAC_GEN_CFG_XGMII_SGMII_SHIFT 1 779 /* 780 * Selects the operation mode of the PCS: 781 * 0 - XAUI 782 * 1 - RXAUI 783 */ 784 #define ETH_MAC_GEN_CFG_XAUI_RXAUI (1 << 3) 785 /* Swap bits of TBI (SGMII mode) interface */ 786 #define ETH_MAC_GEN_CFG_SWAP_TBI_RX (1 << 4) 787 /* 788 * Determines the offset of the TBI bus on the SerDes interface: 789 * 0 - LSB 790 * 1 - MSB 791 */ 792 #define ETH_MAC_GEN_CFG_TBI_MSB_RX (1 << 5) 793 /* 794 * Selects the SGMII PCS/MAC: 795 * 0 – 10G MAC with SGMII 796 * 1 – 1G MAC with SGMII 797 */ 798 #define ETH_MAC_GEN_CFG_SGMII_SEL (1 << 6) 799 /* 800 * Selects between RGMII and SGMII for the 1G MAC: 801 * 0 – RGMII 802 * 1 – SGMII 803 */ 804 #define ETH_MAC_GEN_CFG_RGMII_SGMII_SEL (1 << 7) 805 /* Swap bits of TBI (SGMII mode) interface */ 806 #define ETH_MAC_GEN_CFG_SWAP_TBI_TX (1 << 8) 807 /* 808 * Determines the offset of the TBI bus on the SerDes interface: 809 * 0 - LSB 810 * 1 - MSB 811 */ 812 #define ETH_MAC_GEN_CFG_TBI_MSB_TX (1 << 9) 813 /* 814 * Selection between the MDIO from 10/100/1000 MAC or the 1/2.5/10G MAC 815 * 0 - 10/100/1000 816 * 1 - 1/2.5/10G 817 */ 818 #define ETH_MAC_GEN_CFG_MDIO_1_10 (1 << 10) 819 /* 820 * Swap MDC output 821 * 0 – Normal 822 * 1 – Flipped 823 */ 824 #define ETH_MAC_GEN_CFG_MDIO_POL (1 << 11) 825 /* Swap bits on SerDes interface */ 826 #define ETH_MAC_GEN_CFG_SWAP_SERDES_RX_MASK 0x000F0000 827 #define ETH_MAC_GEN_CFG_SWAP_SERDES_RX_SHIFT 16 828 /* Swap bits on SerDes interface */ 829 #define ETH_MAC_GEN_CFG_SWAP_SERDES_TX_MASK 0x0F000000 830 #define ETH_MAC_GEN_CFG_SWAP_SERDES_TX_SHIFT 24 831 832 /**** mac_1g_cfg register ****/ 833 /* 834 * Selection of the input for the "set_1000" input of the Ethernet 10/100/1000 835 * MAC: 836 * 0 - From RGMII converter (automatic speed selection) 837 * 1 - From register set_1000_def 838 */ 839 #define ETH_MAC_GEN_MAC_1G_CFG_SET_1000_SEL (1 << 0) 840 /* Default value for the 10/100/1000 MAC "set_1000" input */ 841 #define ETH_MAC_GEN_MAC_1G_CFG_SET_1000_DEF (1 << 1) 842 /* 843 * Selection of the input for the "set_10" input of the Ethernet 10/100/1000 844 * MAC: 845 * 0 - From RGMII converter (automatic speed selection) 846 * 1 - From register set_10_def 847 */ 848 #define ETH_MAC_GEN_MAC_1G_CFG_SET_10_SEL (1 << 4) 849 /* Default value for the 10/100/1000 MAC "set_10" input */ 850 #define ETH_MAC_GEN_MAC_1G_CFG_SET_10_DEF (1 << 5) 851 /* Transmit low power enable */ 852 #define ETH_MAC_GEN_MAC_1G_CFG_LOWP_ENA (1 << 8) 853 /* 854 * Enable magic packet mode: 855 * 0 - Sleep mode 856 * 1 - Normal operation 857 */ 858 #define ETH_MAC_GEN_MAC_1G_CFG_SLEEPN (1 << 9) 859 /* Swap ff_tx_crc input */ 860 #define ETH_MAC_GEN_MAC_1G_CFG_SWAP_FF_TX_CRC (1 << 12) 861 862 /**** mac_1g_stat register ****/ 863 /* Status of the en_10 output form the 10/100/1000 MAC */ 864 #define ETH_MAC_GEN_MAC_1G_STAT_EN_10 (1 << 0) 865 /* Status of the eth_mode output from th 10/100/1000 MAC */ 866 #define ETH_MAC_GEN_MAC_1G_STAT_ETH_MODE (1 << 1) 867 /* Status of the lowp output from the 10/100/1000 MAC */ 868 #define ETH_MAC_GEN_MAC_1G_STAT_LOWP (1 << 4) 869 /* Status of the wakeup output from the 10/100/1000 MAC */ 870 #define ETH_MAC_GEN_MAC_1G_STAT_WAKEUP (1 << 5) 871 872 /**** rgmii_cfg register ****/ 873 /* 874 * Selection of the input for the "set_1000" input of the RGMII converter 875 * 0 - From MAC 876 * 1 - From register set_1000_def (automatic speed selection) 877 */ 878 #define ETH_MAC_GEN_RGMII_CFG_SET_1000_SEL (1 << 0) 879 /* Default value for the RGMII converter "set_1000" input */ 880 #define ETH_MAC_GEN_RGMII_CFG_SET_1000_DEF (1 << 1) 881 /* 882 * Selection of the input for the "set_10" input of the RGMII converter: 883 * 0 - From MAC 884 * 1 - From register set_10_def (automatic speed selection) 885 */ 886 #define ETH_MAC_GEN_RGMII_CFG_SET_10_SEL (1 << 4) 887 /* Default value for the 10/100/1000 MAC "set_10" input */ 888 #define ETH_MAC_GEN_RGMII_CFG_SET_10_DEF (1 << 5) 889 /* Enable automatic speed selection (based on PHY in-band status information) */ 890 #define ETH_MAC_GEN_RGMII_CFG_ENA_AUTO (1 << 8) 891 /* Force full duplex, only valid when ena_auto is '1'. */ 892 #define ETH_MAC_GEN_RGMII_CFG_SET_FD (1 << 9) 893 894 /**** rgmii_stat register ****/ 895 /* 896 * Status of the speed output form the RGMII converter 897 * 00 - 10 Mbps 898 * 01 - 100 Mbps 899 * 10 - 1000 Mbps 900 * 11 - Reserved 901 */ 902 #define ETH_MAC_GEN_RGMII_STAT_SPEED_MASK 0x00000003 903 #define ETH_MAC_GEN_RGMII_STAT_SPEED_SHIFT 0 904 /* 905 * Link indication from the RGMII converter (valid only if the external PHY 906 * supports in-band status signaling) 907 */ 908 #define ETH_MAC_GEN_RGMII_STAT_LINK (1 << 4) 909 /* 910 * Full duplex indication from the RGMII converter (valid only if the external 911 * PHY supports in-band status signaling) 912 */ 913 #define ETH_MAC_GEN_RGMII_STAT_DUP (1 << 5) 914 915 /**** mac_10g_cfg register ****/ 916 /* Instruct the XGMII to transmit local fault. */ 917 #define ETH_MAC_GEN_MAC_10G_CFG_TX_LOC_FAULT (1 << 0) 918 /* Instruct the XGMII to transmit remote fault. */ 919 #define ETH_MAC_GEN_MAC_10G_CFG_TX_REM_FAULT (1 << 1) 920 /* Instruct the XGMII to transmit link fault. */ 921 #define ETH_MAC_GEN_MAC_10G_CFG_TX_LI_FAULT (1 << 2) 922 /* 923 * Synchronous reset for the PCS layer. Can be used after SerDes lock assertion 924 * to reset the PCS state machine. 925 */ 926 #define ETH_MAC_GEN_MAC_10G_CFG_SG_SRESET (1 << 3) 927 /* 928 * PHY LOS indication selection 929 * 00 - Select register value from phy_los_def 930 * 01 - Select input from the SerDes 931 * 10 - Select input from GPIO 932 * 11 - Select inverted input from GPIO 933 */ 934 #define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_SEL_MASK 0x00000030 935 #define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_SEL_SHIFT 4 936 /* 937 * Default value for PHY LOS indication. Reflects the LOS indication from the 938 * SerDes. ('' if not used) 939 */ 940 #define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_DEF (1 << 6) 941 /* Reverse polarity of the LOS signal from the SerDes */ 942 #define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_POL (1 << 7) 943 /* Transmit low power enable */ 944 #define ETH_MAC_GEN_MAC_10G_CFG_LOWP_ENA (1 << 8) 945 /* Swap ff_tx_crc input */ 946 #define ETH_MAC_GEN_MAC_10G_CFG_SWAP_FF_TX_CRC (1 << 12) 947 948 /**** mac_10g_stat register ****/ 949 /* XGMII RS detects local fault */ 950 #define ETH_MAC_GEN_MAC_10G_STAT_LOC_FAULT (1 << 0) 951 /* XGMII RS detects remote fault */ 952 #define ETH_MAC_GEN_MAC_10G_STAT_REM_FAULT (1 << 1) 953 /* XGMII RS detects link fault */ 954 #define ETH_MAC_GEN_MAC_10G_STAT_LI_FAULT (1 << 2) 955 /* PFC mode */ 956 #define ETH_MAC_GEN_MAC_10G_STAT_PFC_MODE (1 << 3) 957 958 #define ETH_MAC_GEN_MAC_10G_STAT_SG_ENA (1 << 4) 959 960 #define ETH_MAC_GEN_MAC_10G_STAT_SG_ANDONE (1 << 5) 961 962 #define ETH_MAC_GEN_MAC_10G_STAT_SG_SYNC (1 << 6) 963 964 #define ETH_MAC_GEN_MAC_10G_STAT_SG_SPEED_MASK 0x00000180 965 #define ETH_MAC_GEN_MAC_10G_STAT_SG_SPEED_SHIFT 7 966 /* Status of the lowp output form the 1/2.5/10G MAC */ 967 #define ETH_MAC_GEN_MAC_10G_STAT_LOWP (1 << 9) 968 /* Status of the ts_avail output from th 1/2.5/10G MAC */ 969 #define ETH_MAC_GEN_MAC_10G_STAT_TS_AVAIL (1 << 10) 970 /* Transmit pause indication */ 971 #define ETH_MAC_GEN_MAC_10G_STAT_PAUSE_ON_MASK 0xFF000000 972 #define ETH_MAC_GEN_MAC_10G_STAT_PAUSE_ON_SHIFT 24 973 974 /**** xaui_cfg register ****/ 975 /* Increase rate matching FIFO threshold */ 976 #define ETH_MAC_GEN_XAUI_CFG_JUMBO_EN (1 << 0) 977 978 /**** xaui_stat register ****/ 979 /* Lane alignment status */ 980 #define ETH_MAC_GEN_XAUI_STAT_ALIGN_DONE (1 << 0) 981 /* Lane synchronization */ 982 #define ETH_MAC_GEN_XAUI_STAT_SYNC_MASK 0x000000F0 983 #define ETH_MAC_GEN_XAUI_STAT_SYNC_SHIFT 4 984 /* Code group alignment indication */ 985 #define ETH_MAC_GEN_XAUI_STAT_CG_ALIGN_MASK 0x00000F00 986 #define ETH_MAC_GEN_XAUI_STAT_CG_ALIGN_SHIFT 8 987 988 /**** rxaui_cfg register ****/ 989 /* Increase rate matching FIFO threshold */ 990 #define ETH_MAC_GEN_RXAUI_CFG_JUMBO_EN (1 << 0) 991 /* Scrambler enable */ 992 #define ETH_MAC_GEN_RXAUI_CFG_SRBL_EN (1 << 1) 993 /* Disparity calculation across lanes enabled */ 994 #define ETH_MAC_GEN_RXAUI_CFG_DISP_ACROSS_LANE (1 << 2) 995 996 /**** rxaui_stat register ****/ 997 /* Lane alignment status */ 998 #define ETH_MAC_GEN_RXAUI_STAT_ALIGN_DONE (1 << 0) 999 /* Lane synchronization */ 1000 #define ETH_MAC_GEN_RXAUI_STAT_SYNC_MASK 0x000000F0 1001 #define ETH_MAC_GEN_RXAUI_STAT_SYNC_SHIFT 4 1002 /* Code group alignment indication */ 1003 #define ETH_MAC_GEN_RXAUI_STAT_CG_ALIGN_MASK 0x00000F00 1004 #define ETH_MAC_GEN_RXAUI_STAT_CG_ALIGN_SHIFT 8 1005 1006 /**** sd_cfg register ****/ 1007 /* 1008 * Signal detect selection 1009 * 0 - from register 1010 * 1 - from SerDes 1011 */ 1012 #define ETH_MAC_GEN_SD_CFG_SEL_MASK 0x0000000F 1013 #define ETH_MAC_GEN_SD_CFG_SEL_SHIFT 0 1014 /* Signal detect value */ 1015 #define ETH_MAC_GEN_SD_CFG_VAL_MASK 0x000000F0 1016 #define ETH_MAC_GEN_SD_CFG_VAL_SHIFT 4 1017 /* Signal detect revers polarity (reverse polarity of signal from the SerDes */ 1018 #define ETH_MAC_GEN_SD_CFG_POL_MASK 0x00000F00 1019 #define ETH_MAC_GEN_SD_CFG_POL_SHIFT 8 1020 1021 /**** mdio_ctrl_1 register ****/ 1022 /* 1023 * Available indication 1024 * 0 - The port was available and it is captured by this Ethernet controller. 1025 * 1 - The port is used by another Ethernet controller. 1026 */ 1027 #define ETH_MAC_GEN_MDIO_CTRL_1_AVAIL (1 << 0) 1028 1029 /**** mdio_1 register ****/ 1030 /* Current Ethernet interface number that controls the MDIO port */ 1031 #define ETH_MAC_GEN_MDIO_1_INFO_MASK 0x000000FF 1032 #define ETH_MAC_GEN_MDIO_1_INFO_SHIFT 0 1033 1034 /**** mdio_ctrl_2 register ****/ 1035 /* 1036 * Available indication 1037 * 0 - The port was available and it is captured by this Ethernet controller. 1038 * 1 - The port is used by another Ethernet controller. 1039 */ 1040 #define ETH_MAC_GEN_MDIO_CTRL_2_AVAIL (1 << 0) 1041 1042 /**** mdio_2 register ****/ 1043 /* Current Ethernet interface number that controls the MDIO port */ 1044 #define ETH_MAC_GEN_MDIO_2_INFO_MASK 0x000000FF 1045 #define ETH_MAC_GEN_MDIO_2_INFO_SHIFT 0 1046 1047 /**** xgmii_dfifo_32_64 register ****/ 1048 /* FIFO enable */ 1049 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_ENABLE (1 << 0) 1050 /* Read Write command every 2 cycles */ 1051 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_RW_2_CYCLES (1 << 1) 1052 /* Swap LSB MSB when creating wider bus */ 1053 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_SWAP_LSB_MSB (1 << 2) 1054 /* Software reset */ 1055 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_SW_RESET (1 << 4) 1056 /* Read threshold */ 1057 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_READ_TH_MASK 0x0000FF00 1058 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_READ_TH_SHIFT 8 1059 /* FIFO used */ 1060 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_USED_MASK 0x00FF0000 1061 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_USED_SHIFT 16 1062 1063 /**** xgmii_dfifo_64_32 register ****/ 1064 /* FIFO enable */ 1065 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_ENABLE (1 << 0) 1066 /* Read Write command every 2 cycles */ 1067 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_RW_2_CYCLES (1 << 1) 1068 /* Swap LSB MSB when creating wider bus */ 1069 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_SWAP_LSB_MSB (1 << 2) 1070 /* Software reset */ 1071 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_SW_RESET (1 << 4) 1072 /* Read threshold */ 1073 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_READ_TH_MASK 0x0000FF00 1074 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_READ_TH_SHIFT 8 1075 /* FIFO used */ 1076 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_USED_MASK 0x00FF0000 1077 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_USED_SHIFT 16 1078 1079 /**** sd_fifo_ctrl register ****/ 1080 /* FIFO enable */ 1081 #define ETH_MAC_GEN_SD_FIFO_CTRL_ENABLE_MASK 0x0000000F 1082 #define ETH_MAC_GEN_SD_FIFO_CTRL_ENABLE_SHIFT 0 1083 /* Software reset */ 1084 #define ETH_MAC_GEN_SD_FIFO_CTRL_SW_RESET_MASK 0x000000F0 1085 #define ETH_MAC_GEN_SD_FIFO_CTRL_SW_RESET_SHIFT 4 1086 /* Read threshold */ 1087 #define ETH_MAC_GEN_SD_FIFO_CTRL_READ_TH_MASK 0x0000FF00 1088 #define ETH_MAC_GEN_SD_FIFO_CTRL_READ_TH_SHIFT 8 1089 1090 /**** sd_fifo_stat register ****/ 1091 /* FIFO 0 used */ 1092 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_0_MASK 0x000000FF 1093 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_0_SHIFT 0 1094 /* FIFO 1 used */ 1095 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_1_MASK 0x0000FF00 1096 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_1_SHIFT 8 1097 /* FIFO 2 used */ 1098 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_2_MASK 0x00FF0000 1099 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_2_SHIFT 16 1100 /* FIFO 3 used */ 1101 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_3_MASK 0xFF000000 1102 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_3_SHIFT 24 1103 1104 /**** mux_sel register ****/ 1105 /* 1106 * SGMII input selection selector 1107 * 00 – SerDes 0 1108 * 01 – SerDes 1 1109 * 10 – SerDes 2 1110 * 11 – SerDes 3 1111 */ 1112 #define ETH_MAC_GEN_MUX_SEL_SGMII_IN_MASK 0x00000003 1113 #define ETH_MAC_GEN_MUX_SEL_SGMII_IN_SHIFT 0 1114 /* 1115 * RXAUI Lane 0 Input 1116 * 00 – SerDes 0 1117 * 01 – SerDes 1 1118 * 10 – SerDes 2 1119 * 11 – SerDes 3 1120 */ 1121 #define ETH_MAC_GEN_MUX_SEL_RXAUI_0_IN_MASK 0x0000000C 1122 #define ETH_MAC_GEN_MUX_SEL_RXAUI_0_IN_SHIFT 2 1123 /* 1124 * RXAUI Lane 1 Input 1125 * 00 – SERDES 0 1126 * 01 – SERDES 1 1127 * 10 – SERDES 2 1128 * 11 – SERDES 3 1129 */ 1130 #define ETH_MAC_GEN_MUX_SEL_RXAUI_1_IN_MASK 0x00000030 1131 #define ETH_MAC_GEN_MUX_SEL_RXAUI_1_IN_SHIFT 4 1132 /* 1133 * XAUI Lane 0 Input 1134 * 00 – SERDES 0 1135 * 01 – SERDES 1 1136 * 10 – SERDES 2 1137 * 11 – SERDES 3 1138 */ 1139 #define ETH_MAC_GEN_MUX_SEL_XAUI_0_IN_MASK 0x000000C0 1140 #define ETH_MAC_GEN_MUX_SEL_XAUI_0_IN_SHIFT 6 1141 /* 1142 * XAUI Lane 1 Input 1143 * 00 – SERDES 0 1144 * 01 – SERDES 1 1145 * 10 – SERDES 2 1146 * 11 – SERDES 3 1147 */ 1148 #define ETH_MAC_GEN_MUX_SEL_XAUI_1_IN_MASK 0x00000300 1149 #define ETH_MAC_GEN_MUX_SEL_XAUI_1_IN_SHIFT 8 1150 /* 1151 * XAUI Lane 2 Input 1152 * 00 – SERDES 0 1153 * 01 – SERDES 1 1154 * 10 – SERDES 2 1155 * 11 – SERDES 3 1156 */ 1157 #define ETH_MAC_GEN_MUX_SEL_XAUI_2_IN_MASK 0x00000C00 1158 #define ETH_MAC_GEN_MUX_SEL_XAUI_2_IN_SHIFT 10 1159 /* 1160 * XAUI Lane 3 Input 1161 * 00 – SERDES 0 1162 * 01 – SERDES 1 1163 * 10 – SERDES 2 1164 * 11 – SERDES 3 1165 */ 1166 #define ETH_MAC_GEN_MUX_SEL_XAUI_3_IN_MASK 0x00003000 1167 #define ETH_MAC_GEN_MUX_SEL_XAUI_3_IN_SHIFT 12 1168 /* 1169 * KR PCS Input 1170 * 00 - SERDES 0 1171 * 01 - SERDES 1 1172 * 10 - SERDES 2 1173 * 11 - SERDES 3 1174 */ 1175 #define ETH_MAC_GEN_MUX_SEL_KR_IN_MASK 0x0000C000 1176 #define ETH_MAC_GEN_MUX_SEL_KR_IN_SHIFT 14 1177 /* 1178 * SerDes 0 input selection (TX) 1179 * 000 – XAUI lane 0 1180 * 001 – XAUI lane 1 1181 * 010 – XAUI lane 2 1182 * 011 – XAUI lane 3 1183 * 100 – RXAUI lane 0 1184 * 101 – RXAUI lane 1 1185 * 110 – SGMII 1186 * 111 – KR 1187 */ 1188 #define ETH_MAC_GEN_MUX_SEL_SERDES_0_TX_MASK 0x00070000 1189 #define ETH_MAC_GEN_MUX_SEL_SERDES_0_TX_SHIFT 16 1190 /* 1191 * SERDES 1 input selection (Tx) 1192 * 000 – XAUI lane 0 1193 * 001 – XAUI lane 1 1194 * 010 – XAUI lane 2 1195 * 011 – XAUI lane 3 1196 * 100 – RXAUI lane 0 1197 * 101 – RXAUI lane 1 1198 * 110 – SGMII 1199 * 111 – KR 1200 */ 1201 #define ETH_MAC_GEN_MUX_SEL_SERDES_1_TX_MASK 0x00380000 1202 #define ETH_MAC_GEN_MUX_SEL_SERDES_1_TX_SHIFT 19 1203 /* 1204 * SerDes 2 input selection (Tx) 1205 * 000 – XAUI lane 0 1206 * 001 – XAUI lane 1 1207 * 010 – XAUI lane 2 1208 * 011 – XAUI lane 3 1209 * 100 – RXAUI lane 0 1210 * 101 – RXAUI lane 1 1211 * 110 – SGMII 1212 * 111 – KR 1213 */ 1214 #define ETH_MAC_GEN_MUX_SEL_SERDES_2_TX_MASK 0x01C00000 1215 #define ETH_MAC_GEN_MUX_SEL_SERDES_2_TX_SHIFT 22 1216 /* 1217 * SerDes 3 input selection (Tx) 1218 * 000 – XAUI lane 0 1219 * 001 – XAUI lane 1 1220 * 010 – XAUI lane 2 1221 * 011 – XAUI lane 3 1222 * 100 – RXAUI lane 0 1223 * 101 – RXAUI lane 1 1224 * 110 – SGMII 1225 * 111 – KR 1226 */ 1227 #define ETH_MAC_GEN_MUX_SEL_SERDES_3_TX_MASK 0x0E000000 1228 #define ETH_MAC_GEN_MUX_SEL_SERDES_3_TX_SHIFT 25 1229 1230 /**** clk_cfg register ****/ 1231 /* 1232 * Rx/Tx lane 0 clock MUX select 1233 * must be aligned with data selector MUXs) 1234 * 0 – SerDes 0 clock 1235 * 0 – SerDes 1 clock 1236 * 2 – SerDes 2 clock 1237 * 3 – SerDes 3 clock 1238 */ 1239 #define ETH_MAC_GEN_CLK_CFG_LANE_0_CLK_SEL_MASK 0x00000003 1240 #define ETH_MAC_GEN_CLK_CFG_LANE_0_CLK_SEL_SHIFT 0 1241 /* 1242 * Rx/Tx lane 0 clock MUX select must be aligned with data selector MUXs) 1243 * 0 - SerDes 0 clock 1244 * 1 - SerDes 1 clock 1245 * 2 - SerDes 2 clock 1246 * 3 - SerDes 3 clock 1247 */ 1248 #define ETH_MAC_GEN_CLK_CFG_LANE_1_CLK_SEL_MASK 0x00000030 1249 #define ETH_MAC_GEN_CLK_CFG_LANE_1_CLK_SEL_SHIFT 4 1250 /* 1251 * RX/TX lane 0 clock MUX select (should be aligned with data selector MUXs) 1252 * 0 - SERDES 0 clock 1253 * 1 - SERDES 1 clock 1254 * 2 - SERDES 2 clock 1255 * 3 - SERDES 3 clock 1256 */ 1257 #define ETH_MAC_GEN_CLK_CFG_LANE_2_CLK_SEL_MASK 0x00000300 1258 #define ETH_MAC_GEN_CLK_CFG_LANE_2_CLK_SEL_SHIFT 8 1259 /* 1260 * Rx/Tx lane 0 clock MUX select must be aligned with data selector MUXs) 1261 * 0 - SerDes 0 clock 1262 * 1 - SerDes 1 clock 1263 * 2 - SerDes 2 clock 1264 * 3 - SerDes 3 clock 1265 */ 1266 #define ETH_MAC_GEN_CLK_CFG_LANE_3_CLK_SEL_MASK 0x00003000 1267 #define ETH_MAC_GEN_CLK_CFG_LANE_3_CLK_SEL_SHIFT 12 1268 /* 1269 * MAC GMII Rx clock MUX select must be aligned with data selector MUXs) 1270 * 0 – RGMII 1271 * 1 – SGMII 1272 */ 1273 #define ETH_MAC_GEN_CLK_CFG_GMII_RX_CLK_SEL (1 << 16) 1274 /* 1275 * MAC GMII Tx clock MUX select (should be aligned with data selector MUXs) 1276 * 0 - RGMII 1277 * 1 - SGMII 1278 */ 1279 #define ETH_MAC_GEN_CLK_CFG_GMII_TX_CLK_SEL (1 << 18) 1280 /* 1281 * Tx clock MUX select, 1282 * Selects the internal clock for the Tx data path 1283 * 0 – SerDes[0] TX DWORD CLK REF (for RXAUI and SGMII) 1284 * 1 – SerDes[0] TX WORD CLK REF (for XAUI and KR) 1285 */ 1286 #define ETH_MAC_GEN_CLK_CFG_TX_CLK_SEL (1 << 28) 1287 /* 1288 * Rxclock MUX select 1289 * Selects the internal clock for the Rx data path 1290 * 0 – XGMII TX CLK 32 LOCAL (for XAUI and RXAUI and KR) 1291 * 1 – SerDes[0] RX DWORD CLK GENERATED (125M) 1292 * (for SGMII) 1293 */ 1294 #define ETH_MAC_GEN_CLK_CFG_RX_CLK_SEL (1 << 30) 1295 1296 /**** los_sel register ****/ 1297 /* 1298 * Selected LOS/SD select 1299 * 00 – SerDes 0 1300 * 01 – SerDes 1 1301 * 10 – SerDes 2 1302 * 11 – SerDes 3 1303 */ 1304 #define ETH_MAC_GEN_LOS_SEL_LANE_0_SEL_MASK 0x00000003 1305 #define ETH_MAC_GEN_LOS_SEL_LANE_0_SEL_SHIFT 0 1306 /* 1307 * Selected LOS/SD select 1308 * 00 - SerDes 0 1309 * 01 - SerDes 1 1310 * 10 - SerDes 2 1311 * 11 - SerDes 3 1312 */ 1313 #define ETH_MAC_GEN_LOS_SEL_LANE_1_SEL_MASK 0x00000030 1314 #define ETH_MAC_GEN_LOS_SEL_LANE_1_SEL_SHIFT 4 1315 /* 1316 * Selected LOS/SD select 1317 * 00 - SerDes 0 1318 * 01 - SerDes 1 1319 * 10 - SerDes 2 1320 * 11 - SerDes 3 1321 */ 1322 #define ETH_MAC_GEN_LOS_SEL_LANE_2_SEL_MASK 0x00000300 1323 #define ETH_MAC_GEN_LOS_SEL_LANE_2_SEL_SHIFT 8 1324 /* 1325 * Selected LOS/SD select 1326 * 00 - SerDes 0 1327 * 01 - SerDes 1 1328 * 10 - SerDes 2 1329 * 11 - SerDes 3 1330 */ 1331 #define ETH_MAC_GEN_LOS_SEL_LANE_3_SEL_MASK 0x00003000 1332 #define ETH_MAC_GEN_LOS_SEL_LANE_3_SEL_SHIFT 12 1333 1334 /**** rgmii_sel register ****/ 1335 /* Swap [3:0] input with [7:4] */ 1336 #define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_3_0 (1 << 0) 1337 /* Swap [4] input with [9] */ 1338 #define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_4 (1 << 1) 1339 /* Swap [7:4] input with [3:0] */ 1340 #define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_7_3 (1 << 2) 1341 /* Swap [9] input with [4] */ 1342 #define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_9 (1 << 3) 1343 /* Swap [3:0] input with [7:4] */ 1344 #define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_3_0 (1 << 4) 1345 /* Swap [4] input with [9] */ 1346 #define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_4 (1 << 5) 1347 /* Swap [7:4] input with [3:0] */ 1348 #define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_7_3 (1 << 6) 1349 /* Swap [9] input with [4] */ 1350 #define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_9 (1 << 7) 1351 1352 /**** led_cfg register ****/ 1353 /* 1354 * LED source selection: 1355 * 0 – Default reg 1356 * 1 – Rx activity 1357 * 2 – Tx activity 1358 * 3 – Rx | Tx activity 1359 * 4-9 – SGMII LEDs 1360 */ 1361 #define ETH_MAC_GEN_LED_CFG_SEL_MASK 0x0000000F 1362 #define ETH_MAC_GEN_LED_CFG_SEL_SHIFT 0 1363 1364 /* turn the led on/off based on default value field (ETH_MAC_GEN_LED_CFG_DEF) */ 1365 #define ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG 0 1366 #define ETH_MAC_GEN_LED_CFG_SEL_RX_ACTIVITY_DEPRECIATED 1 1367 #define ETH_MAC_GEN_LED_CFG_SEL_TX_ACTIVITY_DEPRECIATED 2 1368 #define ETH_MAC_GEN_LED_CFG_SEL_RX_TX_ACTIVITY_DEPRECIATED 3 1369 #define ETH_MAC_GEN_LED_CFG_SEL_LINK_ACTIVITY 10 1370 1371 /* LED default value */ 1372 #define ETH_MAC_GEN_LED_CFG_DEF (1 << 4) 1373 /* LED signal polarity */ 1374 #define ETH_MAC_GEN_LED_CFG_POL (1 << 5) 1375 /* 1376 * activity timer (MSB) 1377 * 32 bit timer @SB clock 1378 */ 1379 #define ETH_MAC_GEN_LED_CFG_ACT_TIMER_MASK 0x00FF0000 1380 #define ETH_MAC_GEN_LED_CFG_ACT_TIMER_SHIFT 16 1381 /* 1382 * activity timer (MSB) 1383 * 32 bit timer @SB clock 1384 */ 1385 #define ETH_MAC_GEN_LED_CFG_BLINK_TIMER_MASK 0xFF000000 1386 #define ETH_MAC_GEN_LED_CFG_BLINK_TIMER_SHIFT 24 1387 1388 /**** pcs_addr register ****/ 1389 /* Address value */ 1390 #define ETH_MAC_KR_PCS_ADDR_VAL_MASK 0x0000FFFF 1391 #define ETH_MAC_KR_PCS_ADDR_VAL_SHIFT 0 1392 1393 /**** pcs_data register ****/ 1394 /* Data value */ 1395 #define ETH_MAC_KR_PCS_DATA_VAL_MASK 0x0000FFFF 1396 #define ETH_MAC_KR_PCS_DATA_VAL_SHIFT 0 1397 1398 /**** an_addr register ****/ 1399 /* Address value */ 1400 #define ETH_MAC_KR_AN_ADDR_VAL_MASK 0x0000FFFF 1401 #define ETH_MAC_KR_AN_ADDR_VAL_SHIFT 0 1402 1403 /**** an_data register ****/ 1404 /* Data value */ 1405 #define ETH_MAC_KR_AN_DATA_VAL_MASK 0x0000FFFF 1406 #define ETH_MAC_KR_AN_DATA_VAL_SHIFT 0 1407 1408 /**** pma_addr register ****/ 1409 /* Dddress value */ 1410 #define ETH_MAC_KR_PMA_ADDR_VAL_MASK 0x0000FFFF 1411 #define ETH_MAC_KR_PMA_ADDR_VAL_SHIFT 0 1412 1413 /**** pma_data register ****/ 1414 /* Data value */ 1415 #define ETH_MAC_KR_PMA_DATA_VAL_MASK 0x0000FFFF 1416 #define ETH_MAC_KR_PMA_DATA_VAL_SHIFT 0 1417 1418 /**** mtip_addr register ****/ 1419 /* Address value */ 1420 #define ETH_MAC_KR_MTIP_ADDR_VAL_MASK 0x0000FFFF 1421 #define ETH_MAC_KR_MTIP_ADDR_VAL_SHIFT 0 1422 1423 /**** mtip_data register ****/ 1424 /* Data value */ 1425 #define ETH_MAC_KR_MTIP_DATA_VAL_MASK 0x0000FFFF 1426 #define ETH_MAC_KR_MTIP_DATA_VAL_SHIFT 0 1427 1428 /**** pcs_cfg register ****/ 1429 /* Enable Auto-Negotiation after Reset */ 1430 #define ETH_MAC_KR_PCS_CFG_STRAP_AN_ENA (1 << 0) 1431 /* 1432 * Signal detect selector for the EEE 1433 * 0 – Register default value 1434 * 1 – SerDes value 1435 */ 1436 #define ETH_MAC_KR_PCS_CFG_EEE_SD_SEL (1 << 4) 1437 /* Signal detect default value for the EEE */ 1438 #define ETH_MAC_KR_PCS_CFG_EEE_DEF_VAL (1 << 5) 1439 /* Signal detect polarity reversal for the EEE */ 1440 #define ETH_MAC_KR_PCS_CFG_EEE_SD_POL (1 << 6) 1441 /* EEE timer value */ 1442 #define ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_MASK 0x0000FF00 1443 #define ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_SHIFT 8 1444 /* 1445 * Selects source for the enable SerDes DME signal 1446 * 0 – Register value 1447 * 1 – PCS output 1448 */ 1449 #define ETH_MAC_KR_PCS_CFG_DME_SEL (1 << 16) 1450 /* DME default value */ 1451 #define ETH_MAC_KR_PCS_CFG_DME_VAL (1 << 17) 1452 /* DME default polarity reversal when selecting PCS output */ 1453 #define ETH_MAC_KR_PCS_CFG_DME_POL (1 << 18) 1454 1455 /**** pcs_stat register ****/ 1456 /* Link enable by the Auto-Negotiation */ 1457 #define ETH_MAC_KR_PCS_STAT_AN_LINK_CONTROL_MASK 0x0000003F 1458 #define ETH_MAC_KR_PCS_STAT_AN_LINK_CONTROL_SHIFT 0 1459 /* Block lock */ 1460 #define ETH_MAC_KR_PCS_STAT_BLOCK_LOCK (1 << 8) 1461 /* hi BER */ 1462 #define ETH_MAC_KR_PCS_STAT_HI_BER (1 << 9) 1463 1464 #define ETH_MAC_KR_PCS_STAT_RX_WAKE_ERR (1 << 16) 1465 1466 #define ETH_MAC_KR_PCS_STAT_PMA_TXMODE_ALERT (1 << 17) 1467 1468 #define ETH_MAC_KR_PCS_STAT_PMA_TXMODE_QUIET (1 << 18) 1469 1470 #define ETH_MAC_KR_PCS_STAT_PMA_RXMODE_QUIET (1 << 19) 1471 1472 #define ETH_MAC_KR_PCS_STAT_RX_LPI_ACTIVE (1 << 20) 1473 1474 #define ETH_MAC_KR_PCS_STAT_TX_LPI_ACTIVE (1 << 21) 1475 1476 /**** reg_addr register ****/ 1477 /* Address value */ 1478 #define ETH_MAC_SGMII_REG_ADDR_VAL_MASK 0x0000001F 1479 #define ETH_MAC_SGMII_REG_ADDR_VAL_SHIFT 0 1480 1481 #define ETH_MAC_SGMII_REG_ADDR_CTRL_REG 0x0 1482 #define ETH_MAC_SGMII_REG_ADDR_IF_MODE_REG 0x14 1483 1484 /**** reg_data register ****/ 1485 /* Data value */ 1486 #define ETH_MAC_SGMII_REG_DATA_VAL_MASK 0x0000FFFF 1487 #define ETH_MAC_SGMII_REG_DATA_VAL_SHIFT 0 1488 1489 #define ETH_MAC_SGMII_REG_DATA_CTRL_AN_ENABLE (1 << 12) 1490 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_EN (1 << 0) 1491 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_AN (1 << 1) 1492 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_MASK 0xC 1493 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_SHIFT 2 1494 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_10 0x0 1495 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_100 0x1 1496 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_1000 0x2 1497 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_DUPLEX (1 << 4) 1498 1499 /**** clk_div register ****/ 1500 /* Value for 1000M selection */ 1501 #define ETH_MAC_SGMII_CLK_DIV_VAL_1000_MASK 0x000000FF 1502 #define ETH_MAC_SGMII_CLK_DIV_VAL_1000_SHIFT 0 1503 /* Value for 100M selection */ 1504 #define ETH_MAC_SGMII_CLK_DIV_VAL_100_MASK 0x0000FF00 1505 #define ETH_MAC_SGMII_CLK_DIV_VAL_100_SHIFT 8 1506 /* Value for 10M selection */ 1507 #define ETH_MAC_SGMII_CLK_DIV_VAL_10_MASK 0x00FF0000 1508 #define ETH_MAC_SGMII_CLK_DIV_VAL_10_SHIFT 16 1509 /* Bypass PCS selection */ 1510 #define ETH_MAC_SGMII_CLK_DIV_BYPASS (1 << 24) 1511 /* 1512 * Divider selection when bypass field is '1', one hot 1513 * 001 – 1000M 1514 * 010 – 100M 1515 * 100 – 10M 1516 */ 1517 #define ETH_MAC_SGMII_CLK_DIV_SEL_MASK 0x0E000000 1518 #define ETH_MAC_SGMII_CLK_DIV_SEL_SHIFT 25 1519 1520 /**** link_stat register ****/ 1521 1522 #define ETH_MAC_SGMII_LINK_STAT_SET_1000 (1 << 0) 1523 1524 #define ETH_MAC_SGMII_LINK_STAT_SET_100 (1 << 1) 1525 1526 #define ETH_MAC_SGMII_LINK_STAT_SET_10 (1 << 2) 1527 1528 #define ETH_MAC_SGMII_LINK_STAT_LED_AN (1 << 3) 1529 1530 #define ETH_MAC_SGMII_LINK_STAT_HD_ENA (1 << 4) 1531 1532 #define ETH_MAC_SGMII_LINK_STAT_LED_LINK (1 << 5) 1533 1534 /**** afifo_ctrl register ****/ 1535 /* enable tx input operation */ 1536 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_IN (1 << 0) 1537 /* enable tx output operation */ 1538 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_OUT (1 << 1) 1539 /* enable rx input operation */ 1540 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_IN (1 << 4) 1541 /* enable rx output operation */ 1542 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_OUT (1 << 5) 1543 /* enable tx FIFO input operation */ 1544 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_FIFO_IN (1 << 8) 1545 /* enable tx FIFO output operation */ 1546 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_FIFO_OUT (1 << 9) 1547 /* enable rx FIFO input operation */ 1548 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_FIFO_IN (1 << 12) 1549 /* enable rx FIFO output operation */ 1550 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_FIFO_OUT (1 << 13) 1551 1552 /**** tx_afifo_cfg_1 register ****/ 1553 /* minimum packet size configuration */ 1554 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_1_MIN_PKT_SIZE_MASK 0x0000FFFF 1555 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_1_MIN_PKT_SIZE_SHIFT 0 1556 1557 /**** tx_afifo_cfg_2 register ****/ 1558 /* maximum packet size configuration */ 1559 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_2_MAX_PKT_SIZE_MASK 0x0000FFFF 1560 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_2_MAX_PKT_SIZE_SHIFT 0 1561 1562 /**** tx_afifo_cfg_3 register ****/ 1563 /* input bus width */ 1564 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_MASK 0x0000FFFF 1565 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_SHIFT 0 1566 /* input bus width divide factor */ 1567 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_F_MASK 0xFFFF0000 1568 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_F_SHIFT 16 1569 1570 /**** tx_afifo_cfg_4 register ****/ 1571 /* output bus width */ 1572 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_MASK 0x0000FFFF 1573 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_SHIFT 0 1574 /* output bus width divide factor */ 1575 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_F_MASK 0xFFFF0000 1576 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_F_SHIFT 16 1577 1578 /**** tx_afifo_cfg_5 register ****/ 1579 /* 1580 * determines if the input bus is valid/read or “write enable”. 1581 * 0 – write enable 1582 * 1 – valid/ready 1583 */ 1584 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_INPUT_BUS_VALID_RDY (1 << 0) 1585 /* 1586 * determines if the output bus is valid/read or “write enable”. 1587 * 0 – write enable 1588 * 1 – valid/ready 1589 */ 1590 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_BUS_VALID_RDY (1 << 1) 1591 /* Swap input bus bytes */ 1592 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_INPUT_BUS_SWAP_BYTES (1 << 4) 1593 /* Swap output bus bytes */ 1594 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_BUS_SWAP_BYTES (1 << 5) 1595 /* 1596 * output clock select 1597 * 0 – mac_ll_tx_clk 1598 * 1 – clk_mac_sys_clk 1599 */ 1600 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_CLK_SEL (1 << 8) 1601 1602 /**** rx_afifo_cfg_1 register ****/ 1603 /* minimum packet size configuration */ 1604 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_1_MIN_PKT_SIZE_MASK 0x0000FFFF 1605 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_1_MIN_PKT_SIZE_SHIFT 0 1606 1607 /**** rx_afifo_cfg_2 register ****/ 1608 /* maximum packet size configuration */ 1609 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_2_MAX_PKT_SIZE_MASK 0x0000FFFF 1610 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_2_MAX_PKT_SIZE_SHIFT 0 1611 1612 /**** rx_afifo_cfg_3 register ****/ 1613 /* input bus width */ 1614 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_MASK 0x0000FFFF 1615 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_SHIFT 0 1616 /* input bus width divide factor */ 1617 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_F_MASK 0xFFFF0000 1618 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_F_SHIFT 16 1619 1620 /**** rx_afifo_cfg_4 register ****/ 1621 /* output bus width */ 1622 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_MASK 0x0000FFFF 1623 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_SHIFT 0 1624 /* output bus width divide factor */ 1625 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_F_MASK 0xFFFF0000 1626 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_F_SHIFT 16 1627 1628 /**** rx_afifo_cfg_5 register ****/ 1629 /* 1630 * determines if the input bus is valid/read or “write enable”. 1631 * 0 – write enable 1632 * 1 – valid/ready 1633 */ 1634 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_BUS_VALID_RDY (1 << 0) 1635 /* 1636 * determines if the output bus is valid/read or “write enable”. 1637 * 0 – write enable 1638 * 1 – valid/ready 1639 */ 1640 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_OUTPUT_BUS_VALID_RDY (1 << 1) 1641 /* Swap input bus bytes */ 1642 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_BUS_SWAP_BYTES (1 << 4) 1643 /* Swap output bus bytes */ 1644 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_OUTPUT_BUS_SWAP_BYTES (1 << 5) 1645 /* 1646 * input clock select 1647 * 0 – mac_ll_rx_clk 1648 * 1 – clk_serdes_int_0_tx_dword_ref 1649 * 2 – clk_mac_sys_clk 1650 * 3 – mac_ll_tx_clk 1651 */ 1652 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_CLK_SEL_MASK 0x00000300 1653 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_CLK_SEL_SHIFT 8 1654 1655 /**** mac_sel register ****/ 1656 /* 1657 * Select the MAC that is connected to the SGMII PCS. 1658 * 0 – 1G MAC 1659 * 1 – 10G MAC 1660 */ 1661 #define ETH_MAC_GEN_V3_MAC_SEL_MAC_10G_SGMII (1 << 0) 1662 /* 1663 * Select between the 10G and 40G MAC 1664 * 0 – 10G MAC 1665 * 1 – 40G MAC 1666 */ 1667 #define ETH_MAC_GEN_V3_MAC_SEL_MAC_10G_40G (1 << 4) 1668 1669 /**** mac_10g_ll_cfg register ****/ 1670 /* 1671 * select between 10G (KR PCS) and 1G (SGMII) mode. 1672 * 0 – 10G 1673 * 1 – 1G 1674 */ 1675 #define ETH_MAC_GEN_V3_MAC_10G_LL_CFG_MODE_1G (1 << 0) 1676 /* enable Magic packet detection in the MAC (all other packets are dropped) */ 1677 #define ETH_MAC_GEN_V3_MAC_10G_LL_CFG_MAGIC_ENA (1 << 5) 1678 1679 /**** mac_10g_ll_ctrl register ****/ 1680 /* Force the MAC to stop TX transmission after low power mode. */ 1681 #define ETH_MAC_GEN_V3_MAC_10G_LL_CTRL_LPI_TXHOLD (1 << 0) 1682 1683 /**** pcs_10g_ll_cfg register ****/ 1684 /* RX FEC Enable */ 1685 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_RX (1 << 0) 1686 /* TX FEC enable */ 1687 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_TX (1 << 1) 1688 /* 1689 * RX FEC error propagation enable, 1690 * (debug, always 0) 1691 */ 1692 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_ERR_ENA (1 << 2) 1693 /* 1694 * Gearbox configuration: 1695 * 00 -16 1696 * 01 – 20 1697 * 10 – 32 1698 * 11 – reserved 1699 */ 1700 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_TX_GB_CFG_MASK 0x00000030 1701 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_TX_GB_CFG_SHIFT 4 1702 /* 1703 * Gearbox configuration: 1704 * 00 -16 1705 * 01 – 20 1706 * 10 – 32 1707 * 11 – reserved 1708 */ 1709 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_RX_GB_CFG_MASK 0x000000C0 1710 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_RX_GB_CFG_SHIFT 6 1711 1712 /**** pcs_10g_ll_status register ****/ 1713 /* FEC locked indication */ 1714 #define ETH_MAC_GEN_V3_PCS_10G_LL_STATUS_FEC_LOCKED (1 << 0) 1715 1716 /**** pcs_40g_ll_cfg register ****/ 1717 /* RX FEC Enable */ 1718 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_RX_MASK 0x0000000F 1719 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_RX_SHIFT 0 1720 /* TX FEC enable */ 1721 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_TX_MASK 0x000000F0 1722 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_TX_SHIFT 4 1723 /* 1724 * RX FEC error propagation enable, 1725 * (debug, always 0) 1726 */ 1727 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_ERR_EN_MASK 0x00000F00 1728 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_ERR_EN_SHIFT 8 1729 /* 1730 * SERDES width, 16 bit enable 1731 * 1 – 16 1732 * 2 – 32 1733 */ 1734 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_SD_16B (1 << 12) 1735 /* FEC 91 enable */ 1736 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC91_ENA (1 << 13) 1737 /* 1738 * PHY LOS indication selection 1739 * 00 - Select register value from phy_los_def 1740 * 01 - Select input from the SerDes 1741 * 10 - Select input from GPIO 1742 * 11 - Select inverted input from GPIO 1743 */ 1744 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_SEL_MASK 0x00030000 1745 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_SEL_SHIFT 16 1746 /* PHY LOS default value */ 1747 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_DEF (1 << 18) 1748 /* PHY LOS polarity */ 1749 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_POL (1 << 19) 1750 /* 1751 * Energy detect indication selection 1752 * 00 - Select register value from phy_los_def 1753 * 01 - Select input from the SerDes 1754 * 10 - Select input from GPIO 1755 * 11 - Select inverted input from GPIO 1756 */ 1757 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_SEL_MASK 0x00300000 1758 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_SEL_SHIFT 20 1759 /* Energy detect default value */ 1760 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_DEF (1 << 22) 1761 /* Energy detect polarity */ 1762 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_POL (1 << 23) 1763 1764 /**** pcs_40g_ll_status register ****/ 1765 /* Block lock */ 1766 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_BLOCK_LOCK_MASK 0x0000000F 1767 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_BLOCK_LOCK_SHIFT 0 1768 /* align done */ 1769 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_ALIGN_DONE (1 << 4) 1770 /* high BER */ 1771 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_HIGH_BER (1 << 8) 1772 /* FEC locked indication */ 1773 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_FEC_LOCKED_MASK 0x0000F000 1774 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_FEC_LOCKED_SHIFT 12 1775 1776 /**** pcs_40g_ll_addr register ****/ 1777 /* Address value */ 1778 #define ETH_MAC_GEN_V3_PCS_40G_LL_ADDR_VAL_MASK 0x0001FFFF 1779 #define ETH_MAC_GEN_V3_PCS_40G_LL_ADDR_VAL_SHIFT 0 1780 1781 /**** pcs_40g_ll_data register ****/ 1782 /* Data value */ 1783 #define ETH_MAC_GEN_V3_PCS_40G_LL_DATA_VAL_MASK 0x0000FFFF 1784 #define ETH_MAC_GEN_V3_PCS_40G_LL_DATA_VAL_SHIFT 0 1785 1786 /**** mac_40g_ll_cfg register ****/ 1787 /* change TX CRC polarity */ 1788 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_SWAP_FF_TX_CRC (1 << 0) 1789 /* force TX remote fault */ 1790 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_REM_FAULT (1 << 4) 1791 /* force TX local fault */ 1792 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_LOC_FAULT (1 << 5) 1793 /* force TX Link fault */ 1794 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_LI_FAULT (1 << 6) 1795 /* 1796 * PHY LOS indication selection 1797 * 00 - Select register value from phy_los_def 1798 * 01 - Select input from the SerDes 1799 * 10 - Select input from GPIO 1800 * 11 - Select inverted input from GPIO 1801 */ 1802 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_SEL_MASK 0x00000300 1803 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_SEL_SHIFT 8 1804 /* PHY LOS default value */ 1805 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_DEF (1 << 10) 1806 /* PHY LOS polarity */ 1807 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_POL (1 << 11) 1808 1809 /**** mac_40g_ll_status register ****/ 1810 /* pause on indication */ 1811 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_PAUSE_ON_MASK 0x000000FF 1812 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_PAUSE_ON_SHIFT 0 1813 /* local fault indication received */ 1814 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_LOC_FAULT (1 << 8) 1815 /* remote fault indication received */ 1816 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_REM_FAULT (1 << 9) 1817 /* Link fault indication */ 1818 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_LI_FAULT (1 << 10) 1819 1820 /**** preamble_cfg_high register ****/ 1821 /* preamble value */ 1822 #define ETH_MAC_GEN_V3_PREAMBLE_CFG_HIGH_VAL_MASK 0x00FFFFFF 1823 #define ETH_MAC_GEN_V3_PREAMBLE_CFG_HIGH_VAL_SHIFT 0 1824 1825 /**** mac_40g_ll_addr register ****/ 1826 /* Address value */ 1827 #define ETH_MAC_GEN_V3_MAC_40G_LL_ADDR_VAL_MASK 0x000003FF 1828 #define ETH_MAC_GEN_V3_MAC_40G_LL_ADDR_VAL_SHIFT 0 1829 1830 /**** mac_40g_ll_ctrl register ****/ 1831 /* Force the MAC to stop TX transmission after low power mode. */ 1832 #define ETH_MAC_GEN_V3_MAC_40G_LL_CTRL_LPI_TXHOLD (1 << 0) 1833 1834 #define ETH_MAC_GEN_V3_MAC_40G_LL_CTRL_REG_LOWP_ENA (1 << 1) 1835 1836 /**** pcs_40g_fec_91_ll_addr register ****/ 1837 /* Address value */ 1838 #define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_ADDR_VAL_MASK 0x000001FF 1839 #define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_ADDR_VAL_SHIFT 0 1840 1841 /**** pcs_40g_fec_91_ll_data register ****/ 1842 /* Data value */ 1843 #define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_DATA_VAL_MASK 0x0000FFFF 1844 #define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_DATA_VAL_SHIFT 0 1845 1846 /**** pcs_40g_ll_eee_cfg register ****/ 1847 /* Low power timer configuration */ 1848 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_MASK 0x000000FF 1849 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_SHIFT 0 1850 /* Low power Fast wake */ 1851 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_LPI_FW (1 << 8) 1852 1853 /**** pcs_40g_ll_eee_status register ****/ 1854 /* TX LPI mode */ 1855 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_MODE_MASK 0x00000003 1856 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_MODE_SHIFT 0 1857 /* TX LPI state */ 1858 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_STATE_MASK 0x00000070 1859 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_STATE_SHIFT 4 1860 /* TX LPI mode */ 1861 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_MODE (1 << 8) 1862 /* TX LPI state */ 1863 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_STATE_MASK 0x00007000 1864 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_STATE_SHIFT 12 1865 /* TX LPI active */ 1866 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_ACTIVE (1 << 15) 1867 1868 /**** serdes_32_tx_shift register ****/ 1869 /* bit shift */ 1870 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_0_MASK 0x0000001F 1871 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_0_SHIFT 0 1872 /* bit shift */ 1873 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_1_MASK 0x000003E0 1874 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_1_SHIFT 5 1875 /* bit shift */ 1876 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_2_MASK 0x00007C00 1877 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_2_SHIFT 10 1878 /* bit shift */ 1879 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_3_MASK 0x000F8000 1880 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_3_SHIFT 15 1881 1882 /**** serdes_32_rx_shift register ****/ 1883 /* bit shift */ 1884 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_0_MASK 0x0000001F 1885 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_0_SHIFT 0 1886 /* bit shift */ 1887 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_1_MASK 0x000003E0 1888 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_1_SHIFT 5 1889 /* bit shift */ 1890 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_2_MASK 0x00007C00 1891 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_2_SHIFT 10 1892 /* bit shift */ 1893 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_3_MASK 0x000F8000 1894 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_3_SHIFT 15 1895 1896 /**** serdes_32_tx_sel register ****/ 1897 /* 1898 * 0 – directly from serdes 1899 * 1 – swapped 1900 * 2 – swapped with shift 1901 * 3 - legacy (based on gen cfg register) 1902 */ 1903 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_0_MASK 0x00000003 1904 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_0_SHIFT 0 1905 /* 1906 * 0 – directly from serdes 1907 * 1 – swapped 1908 * 2 – swapped with shift 1909 * 3 - legacy (based on gen cfg register) 1910 */ 1911 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_1_MASK 0x00000030 1912 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_1_SHIFT 4 1913 /* 1914 * 0 – directly from serdes 1915 * 1 – swapped 1916 * 2 – swapped with shift 1917 * 3 - legacy (based on gen cfg register) 1918 */ 1919 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_2_MASK 0x00000300 1920 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_2_SHIFT 8 1921 /* 1922 * 0 – directly from serdes 1923 * 1 – swapped 1924 * 2 – swapped with shift 1925 * 3 - legacy (based on gen cfg register) 1926 */ 1927 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_3_MASK 0x00003000 1928 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_3_SHIFT 12 1929 1930 /**** serdes_32_rx_sel register ****/ 1931 /* 1932 * 0 – directly from serdes 1933 * 1 – swapped 1934 * 2 – swapped with shift 1935 * 3 - legacy (based on gen cfg register) 1936 */ 1937 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_0_MASK 0x00000003 1938 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_0_SHIFT 0 1939 /* 1940 * 0 – directly from serdes 1941 * 1 – swapped 1942 * 2 – swapped with shift 1943 * 3 - legacy (based on gen cfg register) 1944 */ 1945 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_1_MASK 0x00000030 1946 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_1_SHIFT 4 1947 /* 1948 * 0 – directly from serdes 1949 * 1 – swapped 1950 * 2 – swapped with shift 1951 * 3 - legacy (based on gen cfg register) 1952 */ 1953 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_2_MASK 0x00000300 1954 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_2_SHIFT 8 1955 /* 1956 * 0 – directly from serdes 1957 * 1 – swapped 1958 * 2 – swapped with shift 1959 * 3 - legacy (based on gen cfg register) 1960 */ 1961 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_3_MASK 0x00003000 1962 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_3_SHIFT 12 1963 1964 /**** an_lt_ctrl register ****/ 1965 /* reset lane [3:0] */ 1966 #define ETH_MAC_GEN_V3_AN_LT_CTRL_SW_RESET_MASK 0x0000000F 1967 #define ETH_MAC_GEN_V3_AN_LT_CTRL_SW_RESET_SHIFT 0 1968 1969 /* PHY LOS indication input selection 1970 * 0 - from serdes 1971 * 1 - from an_lt 1972 */ 1973 #define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_0 (1 << 8) 1974 /* PHY LOS indication input selection 1975 * 0 - from serdes 1976 * 1 - from an_lt 1977 */ 1978 #define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_1 (1 << 9) 1979 /* PHY LOS indication input selection 1980 * 0 - from serdes 1981 * 1 - from an_lt 1982 */ 1983 #define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_2 (1 << 10) 1984 /* PHY LOS indication input selection 1985 * 0 - from serdes 1986 * 1 - from an_lt 1987 */ 1988 #define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_3 (1 << 11) 1989 1990 /**** an_lt_0_addr register ****/ 1991 /* Address value */ 1992 #define ETH_MAC_GEN_V3_AN_LT_0_ADDR_VAL_MASK 0x0000FFFF 1993 #define ETH_MAC_GEN_V3_AN_LT_0_ADDR_VAL_SHIFT 0 1994 1995 /**** an_lt_1_addr register ****/ 1996 /* Address value */ 1997 #define ETH_MAC_GEN_V3_AN_LT_1_ADDR_VAL_MASK 0x0000FFFF 1998 #define ETH_MAC_GEN_V3_AN_LT_1_ADDR_VAL_SHIFT 0 1999 2000 /**** an_lt_2_addr register ****/ 2001 /* Address value */ 2002 #define ETH_MAC_GEN_V3_AN_LT_2_ADDR_VAL_MASK 0x0000FFFF 2003 #define ETH_MAC_GEN_V3_AN_LT_2_ADDR_VAL_SHIFT 0 2004 2005 /**** an_lt_3_addr register ****/ 2006 /* Address value */ 2007 #define ETH_MAC_GEN_V3_AN_LT_3_ADDR_VAL_MASK 0x0000FFFF 2008 #define ETH_MAC_GEN_V3_AN_LT_3_ADDR_VAL_SHIFT 0 2009 2010 /**** ext_serdes_ctrl register ****/ 2011 /* 2012 * Lane 0, SERDES selection: 2013 * 0 – 10G SERDES, lane 0 2014 * 1 – 25G SERDES, lane 0 2015 */ 2016 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_SEL_25_10 (1 << 0) 2017 /* 2018 * Lane 1, SERDES selection: 2019 * 0 – 10G SERDES, lane 1 2020 * 1 – 25G SERDES, lane 1 2021 */ 2022 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_SEL_25_10 (1 << 1) 2023 /* 2024 * Lane 2, SERDES selection: 2025 * 0 – 10G SERDES, lane 2 2026 * 1 – 25G SERDES, lane 0 2027 */ 2028 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_2_SEL_25_10 (1 << 2) 2029 /* 2030 * Lane 3, SERDES selection: 2031 * 0 – 10G SERDES, lane 3 2032 * 1 – 25G SERDES, lane 1 2033 */ 2034 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_3_SEL_25_10 (1 << 3) 2035 2036 /* Lane 0 Rx, 25G 40bit-32bit gearshitf sw reset */ 2037 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_RX_25_GS_SW_RESET (1 << 4) 2038 /* Lane 0 Tx, 25G 40bit-32bit gearshitf sw reset */ 2039 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_TX_25_GS_SW_RESET (1 << 5) 2040 /* Lane 1 Rx, 25G 40bit-32bit gearshitf sw reset */ 2041 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_RX_25_GS_SW_RESET (1 << 6) 2042 /* Lane 1 Tx, 25G 40bit-32bit gearshitf sw reset */ 2043 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_TX_25_GS_SW_RESET (1 << 7) 2044 /* SerDes 25G gear shift Tx lane selector */ 2045 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_SRDS25_GS_TX_LANE_CLK_SEL (1 << 8) 2046 2047 /*** MAC Core registers addresses ***/ 2048 /* command config */ 2049 #define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR 0x00000008 2050 #define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_TX_ENA (1 << 0) 2051 #define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_RX_ENA (1 << 1) 2052 #define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_PFC_MODE (1 << 19) 2053 2054 /* frame length */ 2055 #define ETH_MAC_GEN_V3_MAC_40G_FRM_LENGTH_ADDR 0x00000014 2056 2057 #define ETH_MAC_GEN_V3_MAC_40G_CL01_PAUSE_QUANTA_ADDR 0x00000054 2058 #define ETH_MAC_GEN_V3_MAC_40G_CL23_PAUSE_QUANTA_ADDR 0x00000058 2059 #define ETH_MAC_GEN_V3_MAC_40G_CL45_PAUSE_QUANTA_ADDR 0x0000005C 2060 #define ETH_MAC_GEN_V3_MAC_40G_CL67_PAUSE_QUANTA_ADDR 0x00000060 2061 #define ETH_MAC_GEN_V3_MAC_40G_CL01_QUANTA_THRESH_ADDR 0x00000064 2062 #define ETH_MAC_GEN_V3_MAC_40G_CL23_QUANTA_THRESH_ADDR 0x00000068 2063 #define ETH_MAC_GEN_V3_MAC_40G_CL45_QUANTA_THRESH_ADDR 0x0000006C 2064 #define ETH_MAC_GEN_V3_MAC_40G_CL67_QUANTA_THRESH_ADDR 0x00000070 2065 2066 /* spare */ 2067 #define ETH_MAC_GEN_V3_SPARE_CHICKEN_DISABLE_TIMESTAMP_STRETCH (1 << 0) 2068 2069 /*** PCS Core registers addresses ***/ 2070 /* 40g control/status */ 2071 #define ETH_MAC_GEN_V3_PCS_40G_CONTROL_STATUS_ADDR 0x00000000 2072 /* 40g EEE control and capability */ 2073 #define ETH_MAC_GEN_V3_PCS_40G_EEE_CONTROL_ADDR 0x00000028 2074 /* 10g control_1 */ 2075 #define ETH_MAC_KR_PCS_CONTROL_1_ADDR 0x00000000 2076 2077 #define ETH_MAC_KR_PCS_BASE_R_STATUS2 0x00000021 2078 2079 #define ETH_MAC_KR_AN_MILLISECONDS_COUNTER_ADDR 0x00008000 2080 #define ETH_MAC_AN_LT_MILLISECONDS_COUNTER_ADDR 0x00000020 2081 2082 #ifdef __cplusplus 2083 } 2084 #endif 2085 2086 #endif /* __AL_HAL_ETH_MAC_REGS_H__ */ 2087 2088 /** @} end of Ethernet group */
Cache object: bbb2f4c9e1983645ea35e9ad0639ff63
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