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sys/contrib/dev/ath/ath_hal/ar9300/ar9300template_cus157.h
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1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 /* 18 * READ THIS NOTICE! 19 * 20 * Values defined in this file may only be changed under exceptional circumstances. 21 * 22 * Please ask Fiona Cain before making any changes. 23 */ 24 25 #ifndef __ar9300template_cus157_h__ 26 #define __ar9300template_cus157_h__ 27 28 /* Ensure that AH_BYTE_ORDER is defined */ 29 #ifndef AH_BYTE_ORDER 30 #error AH_BYTE_ORDER needs to be defined! 31 #endif 32 33 static ar9300_eeprom_t Ar9300Template_cus157= 34 { 35 36 2, // eepromVersion; 37 38 ar9300_eeprom_template_cus157, // templateVersion; 39 40 {0x00,0x03,0x7f,0x0,0x0,0x0}, //macAddr[6]; 41 42 //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= 43 44 {"cus157-030-f0000"}, 45 // {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 46 47 //static OSPREY_BASE_EEP_HEADER baseEepHeader= 48 49 { 50 {0,0x1f}, // regDmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 51 0x77, // txrxMask; //4 bits tx and 4 bits rx 52 {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // opCapFlags; 53 0, // rfSilent; 54 0, // blueToothOptions; 55 0, // deviceCap; 56 5, // deviceType; // takes lower byte in eeprom location 57 OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 58 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don 59 0x0d, //featureEnable; //bit0 - enable tx temp comp 60 //bit1 - enable tx volt comp 61 //bit2 - enable fastClock - default to 1 62 //bit3 - enable doubling - default to 1 63 //bit4 - enable internal regulator - default to 0 64 //bit5 - enable paprd -- default to 0 65 0, //miscConfiguration: bit0 - turn down drivestrength 66 6, // eepromWriteEnableGpio 67 0, // wlanDisableGpio 68 8, // wlanLedGpio 69 0xff, // rxBandSelectGpio 70 0x10, // txrxgain 71 0, // swreg 72 }, 73 74 75 //static OSPREY_MODAL_EEP_HEADER modalHeader2G= 76 { 77 78 0x110, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting) 79 0x44444, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 80 {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 81 {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 82 {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 83 25, // tempSlope; 84 0, // voltSlope; 85 {FREQ2FBIN(2464, 1),0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 86 {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 87 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 88 0, // quick drop 89 0, // xpaBiasLvl; // 1 90 0x0e, // txFrameToDataStart; // 1 91 0x0e, // txFrameToPaOn; // 1 92 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 93 0, // antennaGain; // 1 94 0x2c, // switchSettling; // 1 95 -30, // adcDesiredSize; // 1 96 0, // txEndToXpaOff; // 1 97 0x2, // txEndToRxOn; // 1 98 0xe, // txFrameToXpaOn; // 1 99 28, // thresh62; // 1 100 0x80C080, // paprdRateMaskHt20 // 4 101 0x80C080, // paprdRateMaskHt40 102 0, // ant_div_control 103 {0,0,0,0,0,0,0,0,0} //futureModal[9]; 104 }, 105 106 {{0,0,0,0,0,0,0,0,0,0,0,0,0,0}}, // base_ext1 107 108 //static A_UINT8 calFreqPier2G[OSPREY_NUM_2G_CAL_PIERS]= 109 { 110 FREQ2FBIN(2412, 1), 111 FREQ2FBIN(2437, 1), 112 FREQ2FBIN(2462, 1) 113 }, 114 115 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData2G[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= 116 117 { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 118 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 119 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 120 }, 121 122 //A_UINT8 calTarget_freqbin_Cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 123 124 { 125 FREQ2FBIN(2412, 1), 126 FREQ2FBIN(2472, 1) 127 }, 128 129 //static CAL_TARGET_POWER_LEG calTarget_freqbin_2G[OSPREY_NUM_2G_20_TARGET_POWERS] 130 { 131 FREQ2FBIN(2412, 1), 132 FREQ2FBIN(2437, 1), 133 FREQ2FBIN(2472, 1) 134 }, 135 136 //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS] 137 { 138 FREQ2FBIN(2412, 1), 139 FREQ2FBIN(2437, 1), 140 FREQ2FBIN(2472, 1) 141 }, 142 143 //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS] 144 { 145 FREQ2FBIN(2412, 1), 146 FREQ2FBIN(2437, 1), 147 FREQ2FBIN(2472, 1) 148 }, 149 150 //static CAL_TARGET_POWER_LEG calTargetPowerCck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= 151 { 152 //1L-5L,5S,11L,11S 153 {{34,34,34,34}}, 154 {{34,34,34,34}} 155 }, 156 157 //static CAL_TARGET_POWER_LEG calTargetPower2G[OSPREY_NUM_2G_20_TARGET_POWERS]= 158 { 159 //6-24,36,48,54 160 {{34,34,34,30}}, 161 {{34,34,34,30}}, 162 {{34,34,34,30}}, 163 }, 164 165 //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]= 166 { 167 //0_8_16,1-3_9-11_17-19, 168 // 4,5,6,7,12,13,14,15,20,21,22,23 169 {{32,32,32,32,30,30,32,32,30,30,32,32,30,30}}, 170 {{32,32,32,32,30,30,32,32,30,30,32,32,30,30}}, 171 {{32,32,32,32,30,30,32,32,30,30,32,32,30,30}}, 172 }, 173 174 //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]= 175 { 176 //0_8_16,1-3_9-11_17-19, 177 // 4,5,6,7,12,13,14,15,20,21,22,23 178 {{30,30,30,30,30,28,30,30,28,28,30,30,28,26}}, 179 {{30,30,30,30,30,28,30,30,28,28,30,30,28,26}}, 180 {{30,30,30,30,30,28,30,30,28,28,30,30,28,26}}, 181 }, 182 183 //static A_UINT8 ctlIndex_2G[OSPREY_NUM_CTLS_2G]= 184 185 { 186 187 0x11, 188 0x12, 189 0x15, 190 0x17, 191 0x41, 192 0x42, 193 0x45, 194 0x47, 195 0x31, 196 0x32, 197 0x35, 198 0x37 199 200 }, 201 202 //A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 203 204 { 205 {FREQ2FBIN(2412, 1), 206 FREQ2FBIN(2417, 1), 207 FREQ2FBIN(2457, 1), 208 FREQ2FBIN(2462, 1)}, 209 210 {FREQ2FBIN(2412, 1), 211 FREQ2FBIN(2417, 1), 212 FREQ2FBIN(2462, 1), 213 0xFF}, 214 215 {FREQ2FBIN(2412, 1), 216 FREQ2FBIN(2417, 1), 217 FREQ2FBIN(2462, 1), 218 0xFF}, 219 220 {FREQ2FBIN(2422, 1), 221 FREQ2FBIN(2427, 1), 222 FREQ2FBIN(2447, 1), 223 FREQ2FBIN(2452, 1)}, 224 225 {/*Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 226 /*Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 227 /*Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 228 /*Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(2484, 1)}, 229 230 {/*Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 231 /*Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 232 /*Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 233 0}, 234 235 {/*Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 236 /*Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 237 FREQ2FBIN(2472, 1), 238 0}, 239 240 {/*Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1), 241 /*Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1), 242 /*Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1), 243 /*Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)}, 244 245 {/*Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 246 /*Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 247 /*Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 248 0}, 249 250 {/*Data[9].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 251 /*Data[9].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 252 /*Data[9].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 253 0}, 254 255 {/*Data[10].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1), 256 /*Data[10].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1), 257 /*Data[10].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1), 258 0}, 259 260 {/*Data[11].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1), 261 /*Data[11].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1), 262 /*Data[11].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1), 263 /*Data[11].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)} 264 }, 265 266 267 //OSP_CAL_CTL_DATA_2G ctlPowerData_2G[OSPREY_NUM_CTLS_2G]; 268 269 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 270 { 271 272 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 273 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 274 {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, 275 276 {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, 277 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 278 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 279 280 {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, 281 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 282 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 283 284 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 285 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 286 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 287 288 }, 289 #else 290 { 291 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 292 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 293 {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, 294 295 {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, 296 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 297 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 298 299 {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, 300 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 301 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 302 303 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 304 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 305 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 306 }, 307 #endif 308 309 //static OSPREY_MODAL_EEP_HEADER modalHeader5G= 310 311 { 312 313 0x220, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting) 314 0x44444, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 315 {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 316 {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 317 {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 318 45, // tempSlope; 319 0, // voltSlope; 320 {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 321 {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 322 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 323 0, // quick drop 324 0, // xpaBiasLvl; // 1 325 0x0e, // txFrameToDataStart; // 1 326 0x0e, // txFrameToPaOn; // 1 327 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 328 0, // antennaGain; // 1 329 0x2d, // switchSettling; // 1 330 -30, // adcDesiredSize; // 1 331 0, // txEndToXpaOff; // 1 332 0x2, // txEndToRxOn; // 1 333 0xe, // txFrameToXpaOn; // 1 334 28, // thresh62; // 1 335 0xf0e0e0, // paprdRateMaskHt20 // 4 336 0xf0e0e0, // paprdRateMaskHt40 // 4 337 {0,0,0,0,0,0,0,0,0,0} //futureModal[10]; 338 }, 339 340 { // base_ext2 341 40, // tempSlopeLow 342 50, // tempSlopeHigh 343 {0,0,0}, 344 {0,0,0}, 345 {0,0,0}, 346 {0,0,0} 347 }, 348 349 //static A_UINT8 calFreqPier5G[OSPREY_NUM_5G_CAL_PIERS]= 350 { 351 //pPiers[0] = 352 FREQ2FBIN(5180, 0), 353 //pPiers[1] = 354 FREQ2FBIN(5220, 0), 355 //pPiers[2] = 356 FREQ2FBIN(5320, 0), 357 //pPiers[3] = 358 FREQ2FBIN(5400, 0), 359 //pPiers[4] = 360 FREQ2FBIN(5500, 0), 361 //pPiers[5] = 362 FREQ2FBIN(5600, 0), 363 //pPiers[6] = 364 FREQ2FBIN(5700, 0), 365 //pPiers[7] = 366 FREQ2FBIN(5785, 0), 367 }, 368 369 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData5G[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= 370 371 { 372 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 373 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 374 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 375 376 }, 377 378 //static CAL_TARGET_POWER_LEG calTarget_freqbin_5G[OSPREY_NUM_5G_20_TARGET_POWERS]= 379 380 { 381 FREQ2FBIN(5180, 0), 382 FREQ2FBIN(5240, 0), 383 FREQ2FBIN(5320, 0), 384 FREQ2FBIN(5400, 0), 385 FREQ2FBIN(5500, 0), 386 FREQ2FBIN(5600, 0), 387 FREQ2FBIN(5700, 0), 388 FREQ2FBIN(5825, 0) 389 }, 390 391 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]= 392 393 { 394 FREQ2FBIN(5180, 0), 395 FREQ2FBIN(5240, 0), 396 FREQ2FBIN(5320, 0), 397 FREQ2FBIN(5400, 0), 398 FREQ2FBIN(5500, 0), 399 FREQ2FBIN(5700, 0), 400 FREQ2FBIN(5745, 0), 401 FREQ2FBIN(5825, 0) 402 }, 403 404 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]= 405 406 { 407 FREQ2FBIN(5180, 0), 408 FREQ2FBIN(5240, 0), 409 FREQ2FBIN(5320, 0), 410 FREQ2FBIN(5400, 0), 411 FREQ2FBIN(5500, 0), 412 FREQ2FBIN(5700, 0), 413 FREQ2FBIN(5745, 0), 414 FREQ2FBIN(5825, 0) 415 }, 416 417 418 //static CAL_TARGET_POWER_LEG calTargetPower5G[OSPREY_NUM_5G_20_TARGET_POWERS]= 419 420 421 { 422 //6-24,36,48,54 423 {{30,30,26,22}}, 424 {{30,30,26,22}}, 425 {{30,30,30,24}}, 426 {{30,30,30,24}}, 427 {{30,30,26,22}}, 428 {{30,24,20,18}}, 429 {{30,24,20,18}}, 430 {{30,24,20,18}}, 431 }, 432 433 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]= 434 435 { 436 //0_8_16,1-3_9-11_17-19, 437 // 4,5,6,7,12,13,14,15,20,21,22,23 438 {{30,30,30,28,24,20,30,28,24,18,30,26,22,16}}, 439 {{30,30,30,28,24,20,30,28,24,18,30,26,22,16}}, 440 {{30,30,30,26,22,18,30,26,22,16,30,24,20,14}}, 441 {{30,30,30,26,22,18,30,26,22,16,30,24,20,14}}, 442 {{30,30,30,24,20,16,30,24,20,14,30,22,18,12}}, 443 {{30,30,30,24,20,16,30,24,20,14,30,22,18,12}}, 444 {{28,28,28,22,18,14,28,22,18,12,28,20,16,10}}, 445 {{28,28,28,22,18,14,28,22,18,12,28,20,16,10}}, 446 }, 447 448 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]= 449 { 450 //0_8_16,1-3_9-11_17-19, 451 // 4,5,6,7,12,13,14,15,20,21,22,23 452 {{28,28,28,26,22,18,28,24,20,16,20,16,16,16}}, 453 {{28,28,28,26,22,18,28,24,20,16,20,16,16,16}}, 454 {{28,28,28,28,24,20,28,28,24,20,22,20,20,20}}, 455 {{28,28,28,28,24,20,28,28,24,20,22,20,20,20}}, 456 {{28,28,28,24,20,16,28,24,20,16,18,16,16,16}}, 457 {{28,28,28,22,18,14,22,20,16,12,14,12,12,10}}, 458 {{28,28,28,22,18,14,22,20,16,12,14,12,12,10}}, 459 {{28,28,28,22,18,14,22,20,16,12,14,12,12,10}}, 460 }, 461 462 //static A_UINT8 ctlIndex_5G[OSPREY_NUM_CTLS_5G]= 463 464 { 465 //pCtlIndex[0] = 466 0x10, 467 //pCtlIndex[1] = 468 0x16, 469 //pCtlIndex[2] = 470 0x18, 471 //pCtlIndex[3] = 472 0x40, 473 //pCtlIndex[4] = 474 0x46, 475 //pCtlIndex[5] = 476 0x48, 477 //pCtlIndex[6] = 478 0x30, 479 //pCtlIndex[7] = 480 0x36, 481 //pCtlIndex[8] = 482 0x38 483 }, 484 485 // A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 486 487 { 488 {/* Data[0].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 489 /* Data[0].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), 490 /* Data[0].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0), 491 /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), 492 /* Data[0].ctlEdges[4].bChannel*/FREQ2FBIN(5600, 0), 493 /* Data[0].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), 494 /* Data[0].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), 495 /* Data[0].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, 496 497 {/* Data[1].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 498 /* Data[1].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), 499 /* Data[1].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0), 500 /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), 501 /* Data[1].ctlEdges[4].bChannel*/FREQ2FBIN(5520, 0), 502 /* Data[1].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), 503 /* Data[1].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), 504 /* Data[1].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, 505 506 {/* Data[2].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), 507 /* Data[2].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0), 508 /* Data[2].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0), 509 /* Data[2].ctlEdges[3].bChannel*/FREQ2FBIN(5310, 0), 510 /* Data[2].ctlEdges[4].bChannel*/FREQ2FBIN(5510, 0), 511 /* Data[2].ctlEdges[5].bChannel*/FREQ2FBIN(5550, 0), 512 /* Data[2].ctlEdges[6].bChannel*/FREQ2FBIN(5670, 0), 513 /* Data[2].ctlEdges[7].bChannel*/FREQ2FBIN(5755, 0)}, 514 515 {/* Data[3].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 516 /* Data[3].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0), 517 /* Data[3].ctlEdges[2].bChannel*/FREQ2FBIN(5260, 0), 518 /* Data[3].ctlEdges[3].bChannel*/FREQ2FBIN(5320, 0), 519 /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0), 520 /* Data[3].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), 521 /* Data[3].ctlEdges[6].bChannel*/0xFF, 522 /* Data[3].ctlEdges[7].bChannel*/0xFF}, 523 524 {/* Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 525 /* Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), 526 /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0), 527 /* Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(5700, 0), 528 /* Data[4].ctlEdges[4].bChannel*/0xFF, 529 /* Data[4].ctlEdges[5].bChannel*/0xFF, 530 /* Data[4].ctlEdges[6].bChannel*/0xFF, 531 /* Data[4].ctlEdges[7].bChannel*/0xFF}, 532 533 {/* Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), 534 /* Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(5270, 0), 535 /* Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(5310, 0), 536 /* Data[5].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0), 537 /* Data[5].ctlEdges[4].bChannel*/FREQ2FBIN(5590, 0), 538 /* Data[5].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0), 539 /* Data[5].ctlEdges[6].bChannel*/0xFF, 540 /* Data[5].ctlEdges[7].bChannel*/0xFF}, 541 542 {/* Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 543 /* Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0), 544 /* Data[6].ctlEdges[2].bChannel*/FREQ2FBIN(5220, 0), 545 /* Data[6].ctlEdges[3].bChannel*/FREQ2FBIN(5260, 0), 546 /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0), 547 /* Data[6].ctlEdges[5].bChannel*/FREQ2FBIN(5600, 0), 548 /* Data[6].ctlEdges[6].bChannel*/FREQ2FBIN(5700, 0), 549 /* Data[6].ctlEdges[7].bChannel*/FREQ2FBIN(5745, 0)}, 550 551 {/* Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0), 552 /* Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0), 553 /* Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(5320, 0), 554 /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0), 555 /* Data[7].ctlEdges[4].bChannel*/FREQ2FBIN(5560, 0), 556 /* Data[7].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0), 557 /* Data[7].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0), 558 /* Data[7].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)}, 559 560 {/* Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0), 561 /* Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0), 562 /* Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0), 563 /* Data[8].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0), 564 /* Data[8].ctlEdges[4].bChannel*/FREQ2FBIN(5550, 0), 565 /* Data[8].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0), 566 /* Data[8].ctlEdges[6].bChannel*/FREQ2FBIN(5755, 0), 567 /* Data[8].ctlEdges[7].bChannel*/FREQ2FBIN(5795, 0)} 568 }, 569 570 //static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= 571 572 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 573 { 574 {{{1, 60}, 575 {1, 60}, 576 {1, 60}, 577 {1, 60}, 578 {1, 60}, 579 {1, 60}, 580 {1, 60}, 581 {0, 60}}}, 582 583 {{{1, 60}, 584 {1, 60}, 585 {1, 60}, 586 {1, 60}, 587 {1, 60}, 588 {1, 60}, 589 {1, 60}, 590 {0, 60}}}, 591 592 {{{0, 60}, 593 {1, 60}, 594 {0, 60}, 595 {1, 60}, 596 {1, 60}, 597 {1, 60}, 598 {1, 60}, 599 {1, 60}}}, 600 601 {{{0, 60}, 602 {1, 60}, 603 {1, 60}, 604 {0, 60}, 605 {1, 60}, 606 {0, 60}, 607 {0, 60}, 608 {0, 60}}}, 609 610 {{{1, 60}, 611 {1, 60}, 612 {1, 60}, 613 {0, 60}, 614 {0, 60}, 615 {0, 60}, 616 {0, 60}, 617 {0, 60}}}, 618 619 {{{1, 60}, 620 {1, 60}, 621 {1, 60}, 622 {1, 60}, 623 {1, 60}, 624 {0, 60}, 625 {0, 60}, 626 {0, 60}}}, 627 628 {{{1, 60}, 629 {1, 60}, 630 {1, 60}, 631 {1, 60}, 632 {1, 60}, 633 {1, 60}, 634 {1, 60}, 635 {1, 60}}}, 636 637 {{{1, 60}, 638 {1, 60}, 639 {0, 60}, 640 {1, 60}, 641 {1, 60}, 642 {1, 60}, 643 {1, 60}, 644 {0, 60}}}, 645 646 {{{1, 60}, 647 {0, 60}, 648 {1, 60}, 649 {1, 60}, 650 {1, 60}, 651 {1, 60}, 652 {0, 60}, 653 {1, 60}}}, 654 } 655 #else 656 { 657 {{{60, 1}, 658 {60, 1}, 659 {60, 1}, 660 {60, 1}, 661 {60, 1}, 662 {60, 1}, 663 {60, 1}, 664 {60, 0}}}, 665 666 {{{60, 1}, 667 {60, 1}, 668 {60, 1}, 669 {60, 1}, 670 {60, 1}, 671 {60, 1}, 672 {60, 1}, 673 {60, 0}}}, 674 675 {{{60, 0}, 676 {60, 1}, 677 {60, 0}, 678 {60, 1}, 679 {60, 1}, 680 {60, 1}, 681 {60, 1}, 682 {60, 1}}}, 683 684 {{{60, 0}, 685 {60, 1}, 686 {60, 1}, 687 {60, 0}, 688 {60, 1}, 689 {60, 0}, 690 {60, 0}, 691 {60, 0}}}, 692 693 {{{60, 1}, 694 {60, 1}, 695 {60, 1}, 696 {60, 0}, 697 {60, 0}, 698 {60, 0}, 699 {60, 0}, 700 {60, 0}}}, 701 702 {{{60, 1}, 703 {60, 1}, 704 {60, 1}, 705 {60, 1}, 706 {60, 1}, 707 {60, 0}, 708 {60, 0}, 709 {60, 0}}}, 710 711 {{{60, 1}, 712 {60, 1}, 713 {60, 1}, 714 {60, 1}, 715 {60, 1}, 716 {60, 1}, 717 {60, 1}, 718 {60, 1}}}, 719 720 {{{60, 1}, 721 {60, 1}, 722 {60, 0}, 723 {60, 1}, 724 {60, 1}, 725 {60, 1}, 726 {60, 1}, 727 {60, 0}}}, 728 729 {{{60, 1}, 730 {60, 0}, 731 {60, 1}, 732 {60, 1}, 733 {60, 1}, 734 {60, 1}, 735 {60, 0}, 736 {60, 1}}}, 737 } 738 #endif 739 }; 740 741 #endif 742
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