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sys/contrib/dev/ath/ath_hal/ar9300/ar9300template_hb116.h
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1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 /* 18 * READ THIS NOTICE! 19 * 20 * Values defined in this file may only be changed under exceptional circumstances. 21 * 22 * Please ask Fiona Cain before making any changes. 23 */ 24 25 26 #ifndef __ar9300templateHB116_h__ 27 #define __ar9300templateHB116_h__ 28 29 /* Ensure that AH_BYTE_ORDER is defined */ 30 #ifndef AH_BYTE_ORDER 31 #error AH_BYTE_ORDER needs to be defined! 32 #endif 33 34 static ar9300_eeprom_t ar9300_template_hb116= 35 { 36 37 2, // eeprom_version; 38 39 ar9300_eeprom_template_hb116, // template_version; 40 41 {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6]; 42 43 //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]= 44 45 {"hb116-041-f0000"}, 46 // {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 47 48 //static OSPREY_BASE_EEP_HEADER base_eep_header= 49 50 { 51 {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 52 0x33, // txrx_mask; //4 bits tx and 4 bits rx 53 {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // op_cap_flags; 54 0, // rf_silent; 55 0, // blue_tooth_options; 56 0, // device_cap; 57 5, // device_type; // takes lower byte in eeprom location 58 OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 59 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don 60 0x0d, //feature_enable; //bit0 - enable tx temp comp 61 //bit1 - enable tx volt comp 62 //bit2 - enable fastClock - default to 1 63 //bit3 - enable doubling - default to 1 64 //bit4 - enable internal regulator - default to 0 65 //bit5 - enable paprd -- default to 0 66 0, //misc_configuration: bit0 - turn down drivestrength 67 6, // eeprom_write_enable_gpio 68 0, // wlan_disable_gpio 69 8, // wlan_led_gpio 70 0xff, // rx_band_select_gpio 71 0x10, // txrxgain 72 0, // swreg 73 }, 74 75 76 //static OSPREY_MODAL_EEP_HEADER modal_header_2g= 77 { 78 79 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 80 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 81 {0x10,0x10,0x10}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 82 {0x1f,0x1f,0x1f}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 83 {0x12,0x12,0x12}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 84 25, // temp_slope; 85 0, // voltSlope; 86 {FREQ2FBIN(2464, 1),0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 87 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 88 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 89 0, // quick drop 90 0, // xpa_bias_lvl; // 1 91 0x0e, // tx_frame_to_data_start; // 1 92 0x0e, // tx_frame_to_pa_on; // 1 93 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 94 0, // antenna_gain; // 1 95 0x2c, // switchSettling; // 1 96 -30, // adcDesiredSize; // 1 97 0, // txEndToXpaOff; // 1 98 0x2, // txEndToRxOn; // 1 99 0xe, // tx_frame_to_xpa_on; // 1 100 28, // thresh62; // 1 101 0x0c80C080, // paprd_rate_mask_ht20 // 4 102 0x0080C080, // paprd_rate_mask_ht40 103 0, // switchcomspdt; // 2 104 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 105 0, // rf_gain_cap 106 0, // tx_gain_cap 107 {0,0,0,0,0} //futureModal[5]; 108 }, 109 110 { 111 0, // ant_div_control 112 {0,0}, // base_ext1 113 0, // misc_enable 114 {0,0,0,0,0,0,0,0}, // temp slop extension 115 0, // quick drop low 116 0, // quick drop high 117 }, 118 119 //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]= 120 { 121 FREQ2FBIN(2412, 1), 122 FREQ2FBIN(2437, 1), 123 FREQ2FBIN(2462, 1) 124 }, 125 126 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]= 127 128 { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 129 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 130 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 131 }, 132 133 //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 134 135 { 136 FREQ2FBIN(2412, 1), 137 FREQ2FBIN(2472, 1) 138 }, 139 140 //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS] 141 { 142 FREQ2FBIN(2412, 1), 143 FREQ2FBIN(2437, 1), 144 FREQ2FBIN(2472, 1) 145 }, 146 147 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS] 148 { 149 FREQ2FBIN(2412, 1), 150 FREQ2FBIN(2437, 1), 151 FREQ2FBIN(2472, 1) 152 }, 153 154 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS] 155 { 156 FREQ2FBIN(2412, 1), 157 FREQ2FBIN(2437, 1), 158 FREQ2FBIN(2472, 1) 159 }, 160 161 //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]= 162 { 163 //1L-5L,5S,11L,11S 164 {{34,34,34,34}}, 165 {{34,34,34,34}} 166 }, 167 168 //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]= 169 { 170 //6-24,36,48,54 171 {{34,34,32,32}}, 172 {{34,34,32,32}}, 173 {{34,34,32,32}}, 174 }, 175 176 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]= 177 { 178 //0_8_16,1-3_9-11_17-19, 179 // 4,5,6,7,12,13,14,15,20,21,22,23 180 {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}}, 181 {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}}, 182 {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}}, 183 }, 184 185 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]= 186 { 187 //0_8_16,1-3_9-11_17-19, 188 // 4,5,6,7,12,13,14,15,20,21,22,23 189 {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, 190 {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, 191 {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}}, 192 }, 193 194 //static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]= 195 196 { 197 198 0x11, 199 0x12, 200 0x15, 201 0x17, 202 0x41, 203 0x42, 204 0x45, 205 0x47, 206 0x31, 207 0x32, 208 0x35, 209 0x37 210 211 }, 212 213 //A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 214 215 { 216 {FREQ2FBIN(2412, 1), 217 FREQ2FBIN(2417, 1), 218 FREQ2FBIN(2457, 1), 219 FREQ2FBIN(2462, 1)}, 220 221 {FREQ2FBIN(2412, 1), 222 FREQ2FBIN(2417, 1), 223 FREQ2FBIN(2462, 1), 224 0xFF}, 225 226 {FREQ2FBIN(2412, 1), 227 FREQ2FBIN(2417, 1), 228 FREQ2FBIN(2462, 1), 229 0xFF}, 230 231 {FREQ2FBIN(2422, 1), 232 FREQ2FBIN(2427, 1), 233 FREQ2FBIN(2447, 1), 234 FREQ2FBIN(2452, 1)}, 235 236 {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 237 /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 238 /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 239 /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)}, 240 241 {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 242 /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 243 /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 244 0}, 245 246 {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 247 /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 248 FREQ2FBIN(2472, 1), 249 0}, 250 251 {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 252 /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 253 /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 254 /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}, 255 256 {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 257 /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 258 /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 259 0}, 260 261 {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 262 /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 263 /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 264 0}, 265 266 {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1), 267 /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1), 268 /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1), 269 0}, 270 271 {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1), 272 /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1), 273 /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1), 274 /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)} 275 }, 276 277 278 //OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; 279 280 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 281 { 282 283 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 284 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 285 {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}}, 286 287 {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}}, 288 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 289 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 290 291 {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}}, 292 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 293 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 294 295 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}}, 296 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 297 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}}, 298 299 }, 300 #else 301 { 302 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 303 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 304 {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}}, 305 306 {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}}, 307 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 308 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 309 310 {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}}, 311 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 312 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 313 314 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}}, 315 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 316 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}}, 317 }, 318 #endif 319 320 //static OSPREY_MODAL_EEP_HEADER modal_header_5g= 321 322 { 323 324 0x220, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 325 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 326 {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 327 {0x19,0x19,0x19}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 328 {0x14,0x14,0x14}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 329 70, // temp_slope; 330 0, // voltSlope; 331 {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 332 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain 333 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved 334 0, // quick drop 335 0, // xpa_bias_lvl; // 1 336 0x0e, // tx_frame_to_data_start; // 1 337 0x0e, // tx_frame_to_pa_on; // 1 338 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 339 0, // antenna_gain; // 1 340 0x2d, // switchSettling; // 1 341 -30, // adcDesiredSize; // 1 342 0, // txEndToXpaOff; // 1 343 0x2, // txEndToRxOn; // 1 344 0xe, // tx_frame_to_xpa_on; // 1 345 28, // thresh62; // 1 346 0x0cf0e0e0, // paprd_rate_mask_ht20 // 4 347 0x6cf0e0e0, // paprd_rate_mask_ht40 // 4 348 0, // switchcomspdt; // 2 349 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 350 0, // rf_gain_cap 351 0, // tx_gain_cap 352 {0,0,0,0,0} //futureModal[5]; 353 }, 354 355 { // base_ext2 356 35, // temp_slope_low 357 50, // temp_slope_high 358 {0,0,0}, 359 {0,0,0}, 360 {0,0,0}, 361 {0,0,0} 362 }, 363 364 //static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]= 365 { 366 //pPiers[0] = 367 FREQ2FBIN(5160, 0), 368 //pPiers[1] = 369 FREQ2FBIN(5220, 0), 370 //pPiers[2] = 371 FREQ2FBIN(5320, 0), 372 //pPiers[3] = 373 FREQ2FBIN(5400, 0), 374 //pPiers[4] = 375 FREQ2FBIN(5500, 0), 376 //pPiers[5] = 377 FREQ2FBIN(5600, 0), 378 //pPiers[6] = 379 FREQ2FBIN(5700, 0), 380 //pPiers[7] = 381 FREQ2FBIN(5785, 0), 382 }, 383 384 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]= 385 386 { 387 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 388 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 389 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}}, 390 391 }, 392 393 //static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 394 395 { 396 FREQ2FBIN(5180, 0), 397 FREQ2FBIN(5240, 0), 398 FREQ2FBIN(5320, 0), 399 FREQ2FBIN(5400, 0), 400 FREQ2FBIN(5500, 0), 401 FREQ2FBIN(5600, 0), 402 FREQ2FBIN(5700, 0), 403 FREQ2FBIN(5825, 0) 404 }, 405 406 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 407 408 { 409 FREQ2FBIN(5180, 0), 410 FREQ2FBIN(5240, 0), 411 FREQ2FBIN(5320, 0), 412 FREQ2FBIN(5400, 0), 413 FREQ2FBIN(5500, 0), 414 FREQ2FBIN(5700, 0), 415 FREQ2FBIN(5745, 0), 416 FREQ2FBIN(5825, 0) 417 }, 418 419 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 420 421 { 422 FREQ2FBIN(5180, 0), 423 FREQ2FBIN(5240, 0), 424 FREQ2FBIN(5320, 0), 425 FREQ2FBIN(5400, 0), 426 FREQ2FBIN(5500, 0), 427 FREQ2FBIN(5700, 0), 428 FREQ2FBIN(5745, 0), 429 FREQ2FBIN(5825, 0) 430 }, 431 432 433 //static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]= 434 435 436 { 437 //6-24,36,48,54 438 {{30,30,28,24}}, 439 {{30,30,28,24}}, 440 {{30,30,28,24}}, 441 {{30,30,28,24}}, 442 {{30,30,28,24}}, 443 {{30,30,28,24}}, 444 {{30,30,28,24}}, 445 {{30,30,28,24}}, 446 }, 447 448 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]= 449 450 { 451 //0_8_16,1-3_9-11_17-19, 452 // 4,5,6,7,12,13,14,15,20,21,22,23 453 {{30,30,30,28,24,20,30,28,24,20,0,0,0,0}}, 454 {{30,30,30,28,24,20,30,28,24,20,0,0,0,0}}, 455 {{30,30,30,26,22,18,30,26,22,18,0,0,0,0}}, 456 {{30,30,30,26,22,18,30,26,22,18,0,0,0,0}}, 457 {{30,30,30,24,20,16,30,24,20,16,0,0,0,0}}, 458 {{30,30,30,24,20,16,30,24,20,16,0,0,0,0}}, 459 {{30,30,30,22,18,14,30,22,18,14,0,0,0,0}}, 460 {{30,30,30,22,18,14,30,22,18,14,0,0,0,0}}, 461 }, 462 463 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]= 464 { 465 //0_8_16,1-3_9-11_17-19, 466 // 4,5,6,7,12,13,14,15,20,21,22,23 467 {{28,28,28,26,22,18,28,26,22,18,0,0,0,0}}, 468 {{28,28,28,26,22,18,28,26,22,18,0,0,0,0}}, 469 {{28,28,28,24,20,16,28,24,20,16,0,0,0,0}}, 470 {{28,28,28,24,20,16,28,24,20,16,0,0,0,0}}, 471 {{28,28,28,22,18,14,28,22,18,14,0,0,0,0}}, 472 {{28,28,28,22,18,14,28,22,18,14,0,0,0,0}}, 473 {{28,28,28,20,16,12,28,20,16,12,0,0,0,0}}, 474 {{28,28,28,20,16,12,28,20,16,12,0,0,0,0}}, 475 }, 476 477 //static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]= 478 479 { 480 //pCtlIndex[0] = 481 0x10, 482 //pCtlIndex[1] = 483 0x16, 484 //pCtlIndex[2] = 485 0x18, 486 //pCtlIndex[3] = 487 0x40, 488 //pCtlIndex[4] = 489 0x46, 490 //pCtlIndex[5] = 491 0x48, 492 //pCtlIndex[6] = 493 0x30, 494 //pCtlIndex[7] = 495 0x36, 496 //pCtlIndex[8] = 497 0x38 498 }, 499 500 // A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 501 502 { 503 {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 504 /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 505 /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 506 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 507 /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0), 508 /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 509 /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 510 /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 511 512 {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 513 /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 514 /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0), 515 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 516 /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0), 517 /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 518 /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 519 /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 520 521 {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 522 /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 523 /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 524 /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0), 525 /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0), 526 /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0), 527 /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0), 528 /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)}, 529 530 {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 531 /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 532 /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0), 533 /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0), 534 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 535 /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 536 /* Data[3].ctl_edges[6].bChannel*/0xFF, 537 /* Data[3].ctl_edges[7].bChannel*/0xFF}, 538 539 {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 540 /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 541 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0), 542 /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0), 543 /* Data[4].ctl_edges[4].bChannel*/0xFF, 544 /* Data[4].ctl_edges[5].bChannel*/0xFF, 545 /* Data[4].ctl_edges[6].bChannel*/0xFF, 546 /* Data[4].ctl_edges[7].bChannel*/0xFF}, 547 548 {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 549 /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0), 550 /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0), 551 /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 552 /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0), 553 /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 554 /* Data[5].ctl_edges[6].bChannel*/0xFF, 555 /* Data[5].ctl_edges[7].bChannel*/0xFF}, 556 557 {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 558 /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0), 559 /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0), 560 /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0), 561 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0), 562 /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0), 563 /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0), 564 /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)}, 565 566 {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0), 567 /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0), 568 /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0), 569 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0), 570 /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0), 571 /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0), 572 /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0), 573 /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)}, 574 575 {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0), 576 /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0), 577 /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0), 578 /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0), 579 /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0), 580 /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0), 581 /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0), 582 /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)} 583 }, 584 585 //static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]= 586 587 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 588 { 589 {{{1, 60}, 590 {1, 60}, 591 {1, 60}, 592 {1, 60}, 593 {1, 60}, 594 {1, 60}, 595 {1, 60}, 596 {0, 60}}}, 597 598 {{{1, 60}, 599 {1, 60}, 600 {1, 60}, 601 {1, 60}, 602 {1, 60}, 603 {1, 60}, 604 {1, 60}, 605 {0, 60}}}, 606 607 {{{0, 60}, 608 {1, 60}, 609 {0, 60}, 610 {1, 60}, 611 {1, 60}, 612 {1, 60}, 613 {1, 60}, 614 {1, 60}}}, 615 616 {{{0, 60}, 617 {1, 60}, 618 {1, 60}, 619 {0, 60}, 620 {1, 60}, 621 {0, 60}, 622 {0, 60}, 623 {0, 60}}}, 624 625 {{{1, 60}, 626 {1, 60}, 627 {1, 60}, 628 {0, 60}, 629 {0, 60}, 630 {0, 60}, 631 {0, 60}, 632 {0, 60}}}, 633 634 {{{1, 60}, 635 {1, 60}, 636 {1, 60}, 637 {1, 60}, 638 {1, 60}, 639 {0, 60}, 640 {0, 60}, 641 {0, 60}}}, 642 643 {{{1, 60}, 644 {1, 60}, 645 {1, 60}, 646 {1, 60}, 647 {1, 60}, 648 {1, 60}, 649 {1, 60}, 650 {1, 60}}}, 651 652 {{{1, 60}, 653 {1, 60}, 654 {0, 60}, 655 {1, 60}, 656 {1, 60}, 657 {1, 60}, 658 {1, 60}, 659 {0, 60}}}, 660 661 {{{1, 60}, 662 {0, 60}, 663 {1, 60}, 664 {1, 60}, 665 {1, 60}, 666 {1, 60}, 667 {0, 60}, 668 {1, 60}}}, 669 } 670 #else 671 { 672 {{{60, 1}, 673 {60, 1}, 674 {60, 1}, 675 {60, 1}, 676 {60, 1}, 677 {60, 1}, 678 {60, 1}, 679 {60, 0}}}, 680 681 {{{60, 1}, 682 {60, 1}, 683 {60, 1}, 684 {60, 1}, 685 {60, 1}, 686 {60, 1}, 687 {60, 1}, 688 {60, 0}}}, 689 690 {{{60, 0}, 691 {60, 1}, 692 {60, 0}, 693 {60, 1}, 694 {60, 1}, 695 {60, 1}, 696 {60, 1}, 697 {60, 1}}}, 698 699 {{{60, 0}, 700 {60, 1}, 701 {60, 1}, 702 {60, 0}, 703 {60, 1}, 704 {60, 0}, 705 {60, 0}, 706 {60, 0}}}, 707 708 {{{60, 1}, 709 {60, 1}, 710 {60, 1}, 711 {60, 0}, 712 {60, 0}, 713 {60, 0}, 714 {60, 0}, 715 {60, 0}}}, 716 717 {{{60, 1}, 718 {60, 1}, 719 {60, 1}, 720 {60, 1}, 721 {60, 1}, 722 {60, 0}, 723 {60, 0}, 724 {60, 0}}}, 725 726 {{{60, 1}, 727 {60, 1}, 728 {60, 1}, 729 {60, 1}, 730 {60, 1}, 731 {60, 1}, 732 {60, 1}, 733 {60, 1}}}, 734 735 {{{60, 1}, 736 {60, 1}, 737 {60, 0}, 738 {60, 1}, 739 {60, 1}, 740 {60, 1}, 741 {60, 1}, 742 {60, 0}}}, 743 744 {{{60, 1}, 745 {60, 0}, 746 {60, 1}, 747 {60, 1}, 748 {60, 1}, 749 {60, 1}, 750 {60, 0}, 751 {60, 1}}}, 752 } 753 #endif 754 }; 755 756 #endif
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