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sys/contrib/dev/iwlwifi/cfg/22000.c
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1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2015-2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2022 Intel Corporation 5 */ 6 #include <linux/module.h> 7 #include <linux/stringify.h> 8 #include "iwl-config.h" 9 #include "iwl-prph.h" 10 #include "fw/api/txq.h" 11 12 /* Highest firmware API version supported */ 13 #define IWL_22000_UCODE_API_MAX 73 14 15 /* Lowest firmware API version supported */ 16 #define IWL_22000_UCODE_API_MIN 39 17 18 /* NVM versions */ 19 #define IWL_22000_NVM_VERSION 0x0a1d 20 21 /* Memory offsets and lengths */ 22 #define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */ 23 #define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */ 24 #define IWL_22000_DCCM2_OFFSET 0x880000 25 #define IWL_22000_DCCM2_LEN 0x8000 26 #define IWL_22000_SMEM_OFFSET 0x400000 27 #define IWL_22000_SMEM_LEN 0xD0000 28 29 #define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-" 30 #define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-" 31 #define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-" 32 #define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-" 33 #define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-" 34 #define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-" 35 #define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-" 36 #define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-" 37 #define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-" 38 #define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-" 39 #define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-" 40 #define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-" 41 #define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-" 42 #define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-" 43 #define IWL_SO_A_MR_A_FW_PRE "iwlwifi-so-a0-mr-a0-" 44 #define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-" 45 #define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-" 46 #define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-" 47 #define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-" 48 #define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0-" 49 #define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-" 50 #define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0-" 51 #define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-" 52 #define IWL_MA_A_FM_A_FW_PRE "iwlwifi-ma-a0-fm-a0-" 53 #define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-" 54 #define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0-" 55 #define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0-" 56 #define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0-" 57 #define IWL_BZ_A_MR_A_FW_PRE "iwlwifi-bz-a0-mr-a0-" 58 #define IWL_BZ_A_FM_A_FW_PRE "iwlwifi-bz-a0-fm-a0-" 59 #define IWL_GL_A_FM_A_FW_PRE "iwlwifi-gl-a0-fm-a0-" 60 #define IWL_BZ_Z_GF_A_FW_PRE "iwlwifi-bz-z0-gf-a0-" 61 #define IWL_BNJ_A_FM_A_FW_PRE "iwlwifi-BzBnj-a0-fm-a0-" 62 #define IWL_BNJ_A_FM4_A_FW_PRE "iwlwifi-BzBnj-a0-fm4-a0-" 63 #define IWL_BNJ_A_GF_A_FW_PRE "iwlwifi-BzBnj-a0-gf-a0-" 64 #define IWL_BNJ_A_GF4_A_FW_PRE "iwlwifi-BzBnj-a0-gf4-a0-" 65 #define IWL_BNJ_A_HR_B_FW_PRE "iwlwifi-BzBnj-a0-hr-b0-" 66 67 68 #define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \ 69 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode" 70 #define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \ 71 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode" 72 #define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \ 73 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 74 #define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \ 75 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode" 76 #define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \ 77 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode" 78 #define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \ 79 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode" 80 #define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \ 81 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode" 82 #define IWL_CC_A_MODULE_FIRMWARE(api) \ 83 IWL_CC_A_FW_PRE __stringify(api) ".ucode" 84 #define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \ 85 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode" 86 #define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \ 87 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode" 88 #define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \ 89 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode" 90 #define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \ 91 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode" 92 #define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 93 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 94 #define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \ 95 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 96 #define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \ 97 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 98 #define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \ 99 IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode" 100 #define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \ 101 IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode" 102 #define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \ 103 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode" 104 #define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \ 105 IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode" 106 #define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \ 107 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode" 108 #define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api) \ 109 IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode" 110 #define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \ 111 IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode" 112 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \ 113 IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode" 114 #define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \ 115 IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode" 116 #define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \ 117 IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 118 #define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \ 119 IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode" 120 #define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \ 121 IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode" 122 #define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \ 123 IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode" 124 #define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \ 125 IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode" 126 #define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \ 127 IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode" 128 #define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \ 129 IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode" 130 #define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \ 131 IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode" 132 #define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \ 133 IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode" 134 135 static const struct iwl_base_params iwl_22000_base_params = { 136 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 137 .num_of_queues = 512, 138 .max_tfd_queue_size = 256, 139 .shadow_ram_support = true, 140 .led_compensation = 57, 141 .wd_timeout = IWL_LONG_WD_TIMEOUT, 142 .max_event_log_size = 512, 143 .shadow_reg_enable = true, 144 .pcie_l1_allowed = true, 145 }; 146 147 static const struct iwl_base_params iwl_ax210_base_params = { 148 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 149 .num_of_queues = 512, 150 .max_tfd_queue_size = 65536, 151 .shadow_ram_support = true, 152 .led_compensation = 57, 153 .wd_timeout = IWL_LONG_WD_TIMEOUT, 154 .max_event_log_size = 512, 155 .shadow_reg_enable = true, 156 .pcie_l1_allowed = true, 157 }; 158 159 static const struct iwl_ht_params iwl_22000_ht_params = { 160 .stbc = true, 161 .ldpc = true, 162 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) | 163 BIT(NL80211_BAND_6GHZ), 164 }; 165 166 #define IWL_DEVICE_22000_COMMON \ 167 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 168 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 169 .led_mode = IWL_LED_RF_STATE, \ 170 .nvm_hw_section_num = 10, \ 171 .non_shared_ant = ANT_B, \ 172 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 173 .dccm_len = IWL_22000_DCCM_LEN, \ 174 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 175 .dccm2_len = IWL_22000_DCCM2_LEN, \ 176 .smem_offset = IWL_22000_SMEM_OFFSET, \ 177 .smem_len = IWL_22000_SMEM_LEN, \ 178 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 179 .apmg_not_supported = true, \ 180 .trans.mq_rx_supported = true, \ 181 .vht_mu_mimo_supported = true, \ 182 .mac_addr_from_csr = 0x380, \ 183 .ht_params = &iwl_22000_ht_params, \ 184 .nvm_ver = IWL_22000_NVM_VERSION, \ 185 .trans.use_tfh = true, \ 186 .trans.rf_id = true, \ 187 .trans.gen2 = true, \ 188 .nvm_type = IWL_NVM_EXT, \ 189 .dbgc_supported = true, \ 190 .min_umac_error_event_table = 0x400000, \ 191 .d3_debug_data_base_addr = 0x401000, \ 192 .d3_debug_data_length = 60 * 1024, \ 193 .mon_smem_regs = { \ 194 .write_ptr = { \ 195 .addr = LDBG_M2S_BUF_WPTR, \ 196 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 197 }, \ 198 .cycle_cnt = { \ 199 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 200 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 201 }, \ 202 } 203 204 #define IWL_DEVICE_22500 \ 205 IWL_DEVICE_22000_COMMON, \ 206 .trans.device_family = IWL_DEVICE_FAMILY_22000, \ 207 .trans.base_params = &iwl_22000_base_params, \ 208 .gp2_reg_addr = 0xa02c68, \ 209 .mon_dram_regs = { \ 210 .write_ptr = { \ 211 .addr = MON_BUFF_WRPTR_VER2, \ 212 .mask = 0xffffffff, \ 213 }, \ 214 .cycle_cnt = { \ 215 .addr = MON_BUFF_CYCLE_CNT_VER2, \ 216 .mask = 0xffffffff, \ 217 }, \ 218 } 219 220 #define IWL_DEVICE_AX210 \ 221 IWL_DEVICE_22000_COMMON, \ 222 .trans.umac_prph_offset = 0x300000, \ 223 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \ 224 .trans.base_params = &iwl_ax210_base_params, \ 225 .min_txq_size = 128, \ 226 .gp2_reg_addr = 0xd02c68, \ 227 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, \ 228 .mon_dram_regs = { \ 229 .write_ptr = { \ 230 .addr = DBGC_CUR_DBGBUF_STATUS, \ 231 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 232 }, \ 233 .cycle_cnt = { \ 234 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 235 .mask = 0xffffffff, \ 236 }, \ 237 .cur_frag = { \ 238 .addr = DBGC_CUR_DBGBUF_STATUS, \ 239 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 240 }, \ 241 } 242 243 #define IWL_DEVICE_BZ_COMMON \ 244 .ucode_api_max = IWL_22000_UCODE_API_MAX, \ 245 .ucode_api_min = IWL_22000_UCODE_API_MIN, \ 246 .led_mode = IWL_LED_RF_STATE, \ 247 .nvm_hw_section_num = 10, \ 248 .non_shared_ant = ANT_B, \ 249 .dccm_offset = IWL_22000_DCCM_OFFSET, \ 250 .dccm_len = IWL_22000_DCCM_LEN, \ 251 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \ 252 .dccm2_len = IWL_22000_DCCM2_LEN, \ 253 .smem_offset = IWL_22000_SMEM_OFFSET, \ 254 .smem_len = IWL_22000_SMEM_LEN, \ 255 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM, \ 256 .apmg_not_supported = true, \ 257 .trans.mq_rx_supported = true, \ 258 .vht_mu_mimo_supported = true, \ 259 .mac_addr_from_csr = 0x30, \ 260 .ht_params = &iwl_22000_ht_params, \ 261 .nvm_ver = IWL_22000_NVM_VERSION, \ 262 .trans.use_tfh = true, \ 263 .trans.rf_id = true, \ 264 .trans.gen2 = true, \ 265 .nvm_type = IWL_NVM_EXT, \ 266 .dbgc_supported = true, \ 267 .min_umac_error_event_table = 0x400000, \ 268 .d3_debug_data_base_addr = 0x401000, \ 269 .d3_debug_data_length = 60 * 1024, \ 270 .mon_smem_regs = { \ 271 .write_ptr = { \ 272 .addr = LDBG_M2S_BUF_WPTR, \ 273 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 274 }, \ 275 .cycle_cnt = { \ 276 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 277 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 278 }, \ 279 } 280 281 #define IWL_DEVICE_BZ \ 282 IWL_DEVICE_BZ_COMMON, \ 283 .trans.umac_prph_offset = 0x300000, \ 284 .trans.device_family = IWL_DEVICE_FAMILY_BZ, \ 285 .trans.base_params = &iwl_ax210_base_params, \ 286 .min_txq_size = 128, \ 287 .gp2_reg_addr = 0xd02c68, \ 288 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \ 289 .mon_dram_regs = { \ 290 .write_ptr = { \ 291 .addr = DBGC_CUR_DBGBUF_STATUS, \ 292 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 293 }, \ 294 .cycle_cnt = { \ 295 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 296 .mask = 0xffffffff, \ 297 }, \ 298 .cur_frag = { \ 299 .addr = DBGC_CUR_DBGBUF_STATUS, \ 300 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 301 }, \ 302 }, \ 303 .mon_dbgi_regs = { \ 304 .write_ptr = { \ 305 .addr = DBGI_SRAM_FIFO_POINTERS, \ 306 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \ 307 }, \ 308 } 309 310 const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = { 311 .mq_rx_supported = true, 312 .use_tfh = true, 313 .rf_id = true, 314 .gen2 = true, 315 .device_family = IWL_DEVICE_FAMILY_22000, 316 .base_params = &iwl_22000_base_params, 317 }; 318 319 const struct iwl_cfg_trans_params iwl_qu_trans_cfg = { 320 .mq_rx_supported = true, 321 .use_tfh = true, 322 .rf_id = true, 323 .gen2 = true, 324 .device_family = IWL_DEVICE_FAMILY_22000, 325 .base_params = &iwl_22000_base_params, 326 .integrated = true, 327 .xtal_latency = 500, 328 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 329 }; 330 331 const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = { 332 .mq_rx_supported = true, 333 .use_tfh = true, 334 .rf_id = true, 335 .gen2 = true, 336 .device_family = IWL_DEVICE_FAMILY_22000, 337 .base_params = &iwl_22000_base_params, 338 .integrated = true, 339 .xtal_latency = 1820, 340 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US, 341 }; 342 343 const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = { 344 .mq_rx_supported = true, 345 .use_tfh = true, 346 .rf_id = true, 347 .gen2 = true, 348 .device_family = IWL_DEVICE_FAMILY_22000, 349 .base_params = &iwl_22000_base_params, 350 .integrated = true, 351 .xtal_latency = 12000, 352 .low_latency_xtal = true, 353 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 354 }; 355 356 const struct iwl_cfg_trans_params iwl_snj_trans_cfg = { 357 .mq_rx_supported = true, 358 .use_tfh = true, 359 .rf_id = true, 360 .gen2 = true, 361 .device_family = IWL_DEVICE_FAMILY_AX210, 362 .base_params = &iwl_ax210_base_params, 363 .umac_prph_offset = 0x300000, 364 }; 365 366 const struct iwl_cfg_trans_params iwl_so_trans_cfg = { 367 .mq_rx_supported = true, 368 .use_tfh = true, 369 .rf_id = true, 370 .gen2 = true, 371 .device_family = IWL_DEVICE_FAMILY_AX210, 372 .base_params = &iwl_ax210_base_params, 373 .umac_prph_offset = 0x300000, 374 .integrated = true, 375 /* TODO: the following values need to be checked */ 376 .xtal_latency = 500, 377 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US, 378 }; 379 380 const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = { 381 .mq_rx_supported = true, 382 .use_tfh = true, 383 .rf_id = true, 384 .gen2 = true, 385 .device_family = IWL_DEVICE_FAMILY_AX210, 386 .base_params = &iwl_ax210_base_params, 387 .umac_prph_offset = 0x300000, 388 .integrated = true, 389 .low_latency_xtal = true, 390 .xtal_latency = 12000, 391 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 392 }; 393 394 const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = { 395 .mq_rx_supported = true, 396 .use_tfh = true, 397 .rf_id = true, 398 .gen2 = true, 399 .device_family = IWL_DEVICE_FAMILY_AX210, 400 .base_params = &iwl_ax210_base_params, 401 .umac_prph_offset = 0x300000, 402 .integrated = true, 403 .low_latency_xtal = true, 404 .xtal_latency = 12000, 405 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 406 .imr_enabled = true, 407 }; 408 409 /* 410 * If the device doesn't support HE, no need to have that many buffers. 411 * 22000 devices can split multiple frames into a single RB, so fewer are 412 * needed; AX210 cannot (but use smaller RBs by default) - these sizes 413 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with 414 * additional overhead to account for processing time. 415 */ 416 #define IWL_NUM_RBDS_NON_HE 512 417 #define IWL_NUM_RBDS_22000_HE 2048 418 #define IWL_NUM_RBDS_AX210_HE 4096 419 420 /* 421 * All JF radio modules are part of the 9000 series, but the MAC part 422 * looks more like 22000. That's why this device is here, but called 423 * 9560 nevertheless. 424 */ 425 const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = { 426 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE, 427 IWL_DEVICE_22500, 428 .num_rbds = IWL_NUM_RBDS_NON_HE, 429 }; 430 431 const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = { 432 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE, 433 IWL_DEVICE_22500, 434 .num_rbds = IWL_NUM_RBDS_NON_HE, 435 }; 436 437 const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = { 438 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE, 439 IWL_DEVICE_22500, 440 /* 441 * This device doesn't support receiving BlockAck with a large bitmap 442 * so we need to restrict the size of transmitted aggregation to the 443 * HT size; mac80211 would otherwise pick the HE max (256) by default. 444 */ 445 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 446 .num_rbds = IWL_NUM_RBDS_NON_HE, 447 }; 448 449 const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = { 450 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE, 451 IWL_DEVICE_22500, 452 /* 453 * This device doesn't support receiving BlockAck with a large bitmap 454 * so we need to restrict the size of transmitted aggregation to the 455 * HT size; mac80211 would otherwise pick the HE max (256) by default. 456 */ 457 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 458 .num_rbds = IWL_NUM_RBDS_NON_HE, 459 }; 460 461 const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = { 462 .device_family = IWL_DEVICE_FAMILY_22000, 463 .base_params = &iwl_22000_base_params, 464 .mq_rx_supported = true, 465 .use_tfh = true, 466 .rf_id = true, 467 .gen2 = true, 468 .bisr_workaround = 1, 469 }; 470 471 const struct iwl_cfg_trans_params iwl_ma_trans_cfg = { 472 .device_family = IWL_DEVICE_FAMILY_AX210, 473 .base_params = &iwl_ax210_base_params, 474 .mq_rx_supported = true, 475 .use_tfh = true, 476 .rf_id = true, 477 .gen2 = true, 478 .integrated = true, 479 .umac_prph_offset = 0x300000 480 }; 481 482 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = { 483 .device_family = IWL_DEVICE_FAMILY_BZ, 484 .base_params = &iwl_ax210_base_params, 485 .mq_rx_supported = true, 486 .use_tfh = true, 487 .rf_id = true, 488 .gen2 = true, 489 .integrated = true, 490 .umac_prph_offset = 0x300000, 491 .xtal_latency = 12000, 492 .low_latency_xtal = true, 493 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 494 }; 495 496 const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101"; 497 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz"; 498 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz"; 499 const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203"; 500 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz"; 501 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz"; 502 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz"; 503 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz"; 504 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz"; 505 const char iwl_bz_name[] = "Intel(R) TBD Bz device"; 506 507 const char iwl_ax200_killer_1650w_name[] = 508 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)"; 509 const char iwl_ax200_killer_1650x_name[] = 510 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)"; 511 const char iwl_ax201_killer_1650s_name[] = 512 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)"; 513 const char iwl_ax201_killer_1650i_name[] = 514 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)"; 515 const char iwl_ax210_killer_1675w_name[] = 516 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)"; 517 const char iwl_ax210_killer_1675x_name[] = 518 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)"; 519 const char iwl_ax211_killer_1675s_name[] = 520 "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)"; 521 const char iwl_ax211_killer_1675i_name[] = 522 "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)"; 523 const char iwl_ax411_killer_1690s_name[] = 524 "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)"; 525 const char iwl_ax411_killer_1690i_name[] = 526 "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)"; 527 528 const struct iwl_cfg iwl_qu_b0_hr1_b0 = { 529 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 530 IWL_DEVICE_22500, 531 /* 532 * This device doesn't support receiving BlockAck with a large bitmap 533 * so we need to restrict the size of transmitted aggregation to the 534 * HT size; mac80211 would otherwise pick the HE max (256) by default. 535 */ 536 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 537 .tx_with_siso_diversity = true, 538 .num_rbds = IWL_NUM_RBDS_22000_HE, 539 }; 540 541 const struct iwl_cfg iwl_qu_b0_hr_b0 = { 542 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 543 IWL_DEVICE_22500, 544 /* 545 * This device doesn't support receiving BlockAck with a large bitmap 546 * so we need to restrict the size of transmitted aggregation to the 547 * HT size; mac80211 would otherwise pick the HE max (256) by default. 548 */ 549 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 550 .num_rbds = IWL_NUM_RBDS_22000_HE, 551 }; 552 553 const struct iwl_cfg iwl_ax201_cfg_qu_hr = { 554 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 555 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 556 IWL_DEVICE_22500, 557 /* 558 * This device doesn't support receiving BlockAck with a large bitmap 559 * so we need to restrict the size of transmitted aggregation to the 560 * HT size; mac80211 would otherwise pick the HE max (256) by default. 561 */ 562 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 563 .num_rbds = IWL_NUM_RBDS_22000_HE, 564 }; 565 566 const struct iwl_cfg iwl_qu_c0_hr1_b0 = { 567 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 568 IWL_DEVICE_22500, 569 /* 570 * This device doesn't support receiving BlockAck with a large bitmap 571 * so we need to restrict the size of transmitted aggregation to the 572 * HT size; mac80211 would otherwise pick the HE max (256) by default. 573 */ 574 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 575 .tx_with_siso_diversity = true, 576 .num_rbds = IWL_NUM_RBDS_22000_HE, 577 }; 578 579 const struct iwl_cfg iwl_qu_c0_hr_b0 = { 580 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 581 IWL_DEVICE_22500, 582 /* 583 * This device doesn't support receiving BlockAck with a large bitmap 584 * so we need to restrict the size of transmitted aggregation to the 585 * HT size; mac80211 would otherwise pick the HE max (256) by default. 586 */ 587 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 588 .num_rbds = IWL_NUM_RBDS_22000_HE, 589 }; 590 591 const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = { 592 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 593 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 594 IWL_DEVICE_22500, 595 /* 596 * This device doesn't support receiving BlockAck with a large bitmap 597 * so we need to restrict the size of transmitted aggregation to the 598 * HT size; mac80211 would otherwise pick the HE max (256) by default. 599 */ 600 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 601 .num_rbds = IWL_NUM_RBDS_22000_HE, 602 }; 603 604 const struct iwl_cfg iwl_quz_a0_hr1_b0 = { 605 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 606 IWL_DEVICE_22500, 607 /* 608 * This device doesn't support receiving BlockAck with a large bitmap 609 * so we need to restrict the size of transmitted aggregation to the 610 * HT size; mac80211 would otherwise pick the HE max (256) by default. 611 */ 612 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 613 .tx_with_siso_diversity = true, 614 .num_rbds = IWL_NUM_RBDS_22000_HE, 615 }; 616 617 const struct iwl_cfg iwl_ax201_cfg_quz_hr = { 618 .name = "Intel(R) Wi-Fi 6 AX201 160MHz", 619 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 620 IWL_DEVICE_22500, 621 /* 622 * This device doesn't support receiving BlockAck with a large bitmap 623 * so we need to restrict the size of transmitted aggregation to the 624 * HT size; mac80211 would otherwise pick the HE max (256) by default. 625 */ 626 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 627 .num_rbds = IWL_NUM_RBDS_22000_HE, 628 }; 629 630 const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = { 631 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)", 632 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 633 IWL_DEVICE_22500, 634 /* 635 * This device doesn't support receiving BlockAck with a large bitmap 636 * so we need to restrict the size of transmitted aggregation to the 637 * HT size; mac80211 would otherwise pick the HE max (256) by default. 638 */ 639 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 640 .num_rbds = IWL_NUM_RBDS_22000_HE, 641 }; 642 643 const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = { 644 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)", 645 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 646 IWL_DEVICE_22500, 647 /* 648 * This device doesn't support receiving BlockAck with a large bitmap 649 * so we need to restrict the size of transmitted aggregation to the 650 * HT size; mac80211 would otherwise pick the HE max (256) by default. 651 */ 652 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 653 .num_rbds = IWL_NUM_RBDS_22000_HE, 654 }; 655 656 const struct iwl_cfg iwl_ax200_cfg_cc = { 657 .fw_name_pre = IWL_CC_A_FW_PRE, 658 IWL_DEVICE_22500, 659 /* 660 * This device doesn't support receiving BlockAck with a large bitmap 661 * so we need to restrict the size of transmitted aggregation to the 662 * HT size; mac80211 would otherwise pick the HE max (256) by default. 663 */ 664 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 665 .num_rbds = IWL_NUM_RBDS_22000_HE, 666 }; 667 668 const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = { 669 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 670 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 671 IWL_DEVICE_22500, 672 /* 673 * This device doesn't support receiving BlockAck with a large bitmap 674 * so we need to restrict the size of transmitted aggregation to the 675 * HT size; mac80211 would otherwise pick the HE max (256) by default. 676 */ 677 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 678 .num_rbds = IWL_NUM_RBDS_22000_HE, 679 }; 680 681 const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = { 682 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 683 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE, 684 IWL_DEVICE_22500, 685 /* 686 * This device doesn't support receiving BlockAck with a large bitmap 687 * so we need to restrict the size of transmitted aggregation to the 688 * HT size; mac80211 would otherwise pick the HE max (256) by default. 689 */ 690 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 691 .num_rbds = IWL_NUM_RBDS_22000_HE, 692 }; 693 694 const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = { 695 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)", 696 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 697 IWL_DEVICE_22500, 698 /* 699 * This device doesn't support receiving BlockAck with a large bitmap 700 * so we need to restrict the size of transmitted aggregation to the 701 * HT size; mac80211 would otherwise pick the HE max (256) by default. 702 */ 703 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 704 .num_rbds = IWL_NUM_RBDS_22000_HE, 705 }; 706 707 const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = { 708 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)", 709 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE, 710 IWL_DEVICE_22500, 711 /* 712 * This device doesn't support receiving BlockAck with a large bitmap 713 * so we need to restrict the size of transmitted aggregation to the 714 * HT size; mac80211 would otherwise pick the HE max (256) by default. 715 */ 716 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 717 .num_rbds = IWL_NUM_RBDS_22000_HE, 718 }; 719 720 const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = { 721 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE, 722 IWL_DEVICE_22500, 723 /* 724 * This device doesn't support receiving BlockAck with a large bitmap 725 * so we need to restrict the size of transmitted aggregation to the 726 * HT size; mac80211 would otherwise pick the HE max (256) by default. 727 */ 728 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 729 .num_rbds = IWL_NUM_RBDS_22000_HE, 730 }; 731 732 const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = { 733 .name = "Intel(R) Wireless-AC 9560 160MHz", 734 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE, 735 IWL_DEVICE_AX210, 736 .num_rbds = IWL_NUM_RBDS_NON_HE, 737 }; 738 739 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = { 740 .name = iwl_ax211_name, 741 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 742 .uhb_supported = true, 743 IWL_DEVICE_AX210, 744 .num_rbds = IWL_NUM_RBDS_AX210_HE, 745 }; 746 747 const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = { 748 .name = iwl_ax211_name, 749 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE, 750 .uhb_supported = true, 751 IWL_DEVICE_AX210, 752 .num_rbds = IWL_NUM_RBDS_AX210_HE, 753 .trans.xtal_latency = 12000, 754 .trans.low_latency_xtal = true, 755 }; 756 757 const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = { 758 .name = "Intel(R) Wi-Fi 6 AX210 160MHz", 759 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE, 760 .uhb_supported = true, 761 IWL_DEVICE_AX210, 762 .num_rbds = IWL_NUM_RBDS_AX210_HE, 763 }; 764 765 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = { 766 .name = iwl_ax411_name, 767 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 768 .uhb_supported = true, 769 IWL_DEVICE_AX210, 770 .num_rbds = IWL_NUM_RBDS_AX210_HE, 771 }; 772 773 const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = { 774 .name = iwl_ax411_name, 775 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE, 776 .uhb_supported = true, 777 IWL_DEVICE_AX210, 778 .num_rbds = IWL_NUM_RBDS_AX210_HE, 779 .trans.xtal_latency = 12000, 780 .trans.low_latency_xtal = true, 781 }; 782 783 const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = { 784 .name = iwl_ax411_name, 785 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE, 786 .uhb_supported = true, 787 IWL_DEVICE_AX210, 788 .num_rbds = IWL_NUM_RBDS_AX210_HE, 789 }; 790 791 const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = { 792 .name = iwl_ax211_name, 793 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE, 794 .uhb_supported = true, 795 IWL_DEVICE_AX210, 796 .num_rbds = IWL_NUM_RBDS_AX210_HE, 797 }; 798 799 const struct iwl_cfg iwl_cfg_snj_hr_b0 = { 800 .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE, 801 .uhb_supported = true, 802 IWL_DEVICE_AX210, 803 .num_rbds = IWL_NUM_RBDS_AX210_HE, 804 }; 805 806 const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = { 807 .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE, 808 .uhb_supported = true, 809 IWL_DEVICE_AX210, 810 .num_rbds = IWL_NUM_RBDS_AX210_HE, 811 }; 812 813 const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = { 814 .fw_name_pre = IWL_MA_A_HR_B_FW_PRE, 815 .uhb_supported = true, 816 IWL_DEVICE_AX210, 817 .num_rbds = IWL_NUM_RBDS_AX210_HE, 818 }; 819 820 const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = { 821 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE, 822 .uhb_supported = true, 823 IWL_DEVICE_AX210, 824 .num_rbds = IWL_NUM_RBDS_AX210_HE, 825 }; 826 827 const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = { 828 .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE, 829 .uhb_supported = true, 830 IWL_DEVICE_AX210, 831 .num_rbds = IWL_NUM_RBDS_AX210_HE, 832 }; 833 834 const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = { 835 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 836 .uhb_supported = true, 837 IWL_DEVICE_AX210, 838 .num_rbds = IWL_NUM_RBDS_AX210_HE, 839 }; 840 841 const struct iwl_cfg iwl_cfg_ma_a0_ms_a0 = { 842 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE, 843 .uhb_supported = false, 844 IWL_DEVICE_AX210, 845 .num_rbds = IWL_NUM_RBDS_AX210_HE, 846 }; 847 848 const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = { 849 .fw_name_pre = IWL_SO_A_MR_A_FW_PRE, 850 .uhb_supported = false, 851 IWL_DEVICE_AX210, 852 .num_rbds = IWL_NUM_RBDS_AX210_HE, 853 }; 854 855 const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = { 856 .fw_name_pre = IWL_MA_A_FM_A_FW_PRE, 857 .uhb_supported = true, 858 IWL_DEVICE_AX210, 859 .num_rbds = IWL_NUM_RBDS_AX210_HE, 860 }; 861 862 const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = { 863 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 864 .uhb_supported = true, 865 IWL_DEVICE_AX210, 866 .num_rbds = IWL_NUM_RBDS_AX210_HE, 867 }; 868 869 const struct iwl_cfg iwl_cfg_snj_a0_ms_a0 = { 870 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE, 871 .uhb_supported = false, 872 IWL_DEVICE_AX210, 873 .num_rbds = IWL_NUM_RBDS_AX210_HE, 874 }; 875 876 const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = { 877 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE, 878 IWL_DEVICE_AX210, 879 .num_rbds = IWL_NUM_RBDS_AX210_HE, 880 }; 881 882 const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = { 883 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE, 884 IWL_DEVICE_22500, 885 /* 886 * This device doesn't support receiving BlockAck with a large bitmap 887 * so we need to restrict the size of transmitted aggregation to the 888 * HT size; mac80211 would otherwise pick the HE max (256) by default. 889 */ 890 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT, 891 .num_rbds = IWL_NUM_RBDS_22000_HE, 892 }; 893 894 const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = { 895 .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE, 896 .uhb_supported = true, 897 IWL_DEVICE_BZ, 898 .num_rbds = IWL_NUM_RBDS_AX210_HE, 899 }; 900 901 const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = { 902 .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE, 903 .uhb_supported = true, 904 IWL_DEVICE_BZ, 905 .num_rbds = IWL_NUM_RBDS_AX210_HE, 906 }; 907 908 const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = { 909 .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE, 910 .uhb_supported = true, 911 IWL_DEVICE_BZ, 912 .num_rbds = IWL_NUM_RBDS_AX210_HE, 913 }; 914 915 const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = { 916 .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE, 917 .uhb_supported = true, 918 IWL_DEVICE_BZ, 919 .num_rbds = IWL_NUM_RBDS_AX210_HE, 920 }; 921 922 const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = { 923 .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE, 924 .uhb_supported = true, 925 IWL_DEVICE_BZ, 926 .num_rbds = IWL_NUM_RBDS_AX210_HE, 927 }; 928 929 const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = { 930 .fw_name_pre = IWL_GL_A_FM_A_FW_PRE, 931 .uhb_supported = true, 932 IWL_DEVICE_BZ, 933 .num_rbds = IWL_NUM_RBDS_AX210_HE, 934 }; 935 936 const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = { 937 .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE, 938 .uhb_supported = true, 939 IWL_DEVICE_BZ, 940 .num_rbds = IWL_NUM_RBDS_AX210_HE, 941 }; 942 943 const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = { 944 .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE, 945 .uhb_supported = true, 946 IWL_DEVICE_BZ, 947 .num_rbds = IWL_NUM_RBDS_AX210_HE, 948 }; 949 950 const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = { 951 .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE, 952 .uhb_supported = true, 953 IWL_DEVICE_BZ, 954 .num_rbds = IWL_NUM_RBDS_AX210_HE, 955 }; 956 957 const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = { 958 .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE, 959 .uhb_supported = true, 960 IWL_DEVICE_BZ, 961 .num_rbds = IWL_NUM_RBDS_AX210_HE, 962 }; 963 964 const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = { 965 .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE, 966 .uhb_supported = true, 967 IWL_DEVICE_BZ, 968 .num_rbds = IWL_NUM_RBDS_AX210_HE, 969 }; 970 971 const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = { 972 .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE, 973 .uhb_supported = true, 974 IWL_DEVICE_BZ, 975 .num_rbds = IWL_NUM_RBDS_AX210_HE, 976 }; 977 MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 978 MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 979 MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 980 MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 981 MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 982 MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 983 MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 984 MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 985 MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 986 MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 987 MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 988 MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 989 MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 990 MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 991 MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 992 MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 993 MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 994 MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 995 MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 996 MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 997 MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 998 MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 999 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1000 MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1001 MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1002 MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1003 MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1004 MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1005 MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1006 MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1007 MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1008 MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX)); 1009 MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
Cache object: 9e7f182ca938e1be185b2fe1eac5317a
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