1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /*
3 * Copyright (C) 2012-2014, 2018, 2020-2021 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7 #ifndef __iwl_fw_api_phy_ctxt_h__
8 #define __iwl_fw_api_phy_ctxt_h__
9
10 /* Supported bands */
11 #define PHY_BAND_5 (0)
12 #define PHY_BAND_24 (1)
13 #define PHY_BAND_6 (2)
14
15 /* Supported channel width, vary if there is VHT support */
16 #define PHY_VHT_CHANNEL_MODE20 (0x0)
17 #define PHY_VHT_CHANNEL_MODE40 (0x1)
18 #define PHY_VHT_CHANNEL_MODE80 (0x2)
19 #define PHY_VHT_CHANNEL_MODE160 (0x3)
20
21 /*
22 * Control channel position:
23 * For legacy set bit means upper channel, otherwise lower.
24 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
25 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
26 * center_freq
27 * |
28 * 40Mhz |_______|_______|
29 * 80Mhz |_______|_______|_______|_______|
30 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
31 * code 011 010 001 000 | 100 101 110 111
32 */
33 #define PHY_VHT_CTRL_POS_1_BELOW (0x0)
34 #define PHY_VHT_CTRL_POS_2_BELOW (0x1)
35 #define PHY_VHT_CTRL_POS_3_BELOW (0x2)
36 #define PHY_VHT_CTRL_POS_4_BELOW (0x3)
37 #define PHY_VHT_CTRL_POS_1_ABOVE (0x4)
38 #define PHY_VHT_CTRL_POS_2_ABOVE (0x5)
39 #define PHY_VHT_CTRL_POS_3_ABOVE (0x6)
40 #define PHY_VHT_CTRL_POS_4_ABOVE (0x7)
41
42 /*
43 * struct iwl_fw_channel_info_v1 - channel information
44 *
45 * @band: PHY_BAND_*
46 * @channel: channel number
47 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
48 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
49 */
50 struct iwl_fw_channel_info_v1 {
51 u8 band;
52 u8 channel;
53 u8 width;
54 u8 ctrl_pos;
55 } __packed; /* CHANNEL_CONFIG_API_S_VER_1 */
56
57 /*
58 * struct iwl_fw_channel_info - channel information
59 *
60 * @channel: channel number
61 * @band: PHY_BAND_*
62 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
63 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
64 * @reserved: for future use and alignment
65 */
66 struct iwl_fw_channel_info {
67 __le32 channel;
68 u8 band;
69 u8 width;
70 u8 ctrl_pos;
71 u8 reserved;
72 } __packed; /*CHANNEL_CONFIG_API_S_VER_2 */
73
74 #define PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
75 #define PHY_RX_CHAIN_DRIVER_FORCE_MSK \
76 (0x1 << PHY_RX_CHAIN_DRIVER_FORCE_POS)
77 #define PHY_RX_CHAIN_VALID_POS (1)
78 #define PHY_RX_CHAIN_VALID_MSK \
79 (0x7 << PHY_RX_CHAIN_VALID_POS)
80 #define PHY_RX_CHAIN_FORCE_SEL_POS (4)
81 #define PHY_RX_CHAIN_FORCE_SEL_MSK \
82 (0x7 << PHY_RX_CHAIN_FORCE_SEL_POS)
83 #define PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
84 #define PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
85 (0x7 << PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
86 #define PHY_RX_CHAIN_CNT_POS (10)
87 #define PHY_RX_CHAIN_CNT_MSK \
88 (0x3 << PHY_RX_CHAIN_CNT_POS)
89 #define PHY_RX_CHAIN_MIMO_CNT_POS (12)
90 #define PHY_RX_CHAIN_MIMO_CNT_MSK \
91 (0x3 << PHY_RX_CHAIN_MIMO_CNT_POS)
92 #define PHY_RX_CHAIN_MIMO_FORCE_POS (14)
93 #define PHY_RX_CHAIN_MIMO_FORCE_MSK \
94 (0x1 << PHY_RX_CHAIN_MIMO_FORCE_POS)
95
96 /* TODO: fix the value, make it depend on firmware at runtime? */
97 #define NUM_PHY_CTX 3
98
99 /* TODO: complete missing documentation */
100 /**
101 * struct iwl_phy_context_cmd_tail - tail of iwl_phy_ctx_cmd for alignment with
102 * various channel structures.
103 *
104 * @txchain_info: ???
105 * @rxchain_info: ???
106 * @acquisition_data: ???
107 * @dsp_cfg_flags: set to 0
108 */
109 struct iwl_phy_context_cmd_tail {
110 __le32 txchain_info;
111 __le32 rxchain_info;
112 __le32 acquisition_data;
113 __le32 dsp_cfg_flags;
114 } __packed;
115
116 /**
117 * struct iwl_phy_context_cmd - config of the PHY context
118 * ( PHY_CONTEXT_CMD = 0x8 )
119 * @id_and_color: ID and color of the relevant Binding
120 * @action: action to perform, one of FW_CTXT_ACTION_*
121 * @apply_time: 0 means immediate apply and context switch.
122 * other value means apply new params after X usecs
123 * @tx_param_color: ???
124 * @ci: channel info
125 * @tail: command tail
126 */
127 struct iwl_phy_context_cmd_v1 {
128 /* COMMON_INDEX_HDR_API_S_VER_1 */
129 __le32 id_and_color;
130 __le32 action;
131 /* PHY_CONTEXT_DATA_API_S_VER_3 */
132 __le32 apply_time;
133 __le32 tx_param_color;
134 struct iwl_fw_channel_info ci;
135 struct iwl_phy_context_cmd_tail tail;
136 } __packed; /* PHY_CONTEXT_CMD_API_VER_1 */
137
138 /**
139 * struct iwl_phy_context_cmd - config of the PHY context
140 * ( PHY_CONTEXT_CMD = 0x8 )
141 * @id_and_color: ID and color of the relevant Binding
142 * @action: action to perform, one of FW_CTXT_ACTION_*
143 * @lmac_id: the lmac id the phy context belongs to
144 * @ci: channel info
145 * @rxchain_info: ???
146 * @dsp_cfg_flags: set to 0
147 * @reserved: reserved to align to 64 bit
148 */
149 struct iwl_phy_context_cmd {
150 /* COMMON_INDEX_HDR_API_S_VER_1 */
151 __le32 id_and_color;
152 __le32 action;
153 /* PHY_CONTEXT_DATA_API_S_VER_3, PHY_CONTEXT_DATA_API_S_VER_4 */
154 struct iwl_fw_channel_info ci;
155 __le32 lmac_id;
156 __le32 rxchain_info; /* reserved in _VER_4 */
157 __le32 dsp_cfg_flags;
158 __le32 reserved;
159 } __packed; /* PHY_CONTEXT_CMD_API_VER_3, PHY_CONTEXT_CMD_API_VER_4 */
160
161 #endif /* __iwl_fw_api_phy_ctxt_h__ */
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