Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/dev/iwlwifi/pcie/ctxt-info-gen3.c
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1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018-2022 Intel Corporation 4 */ 5 #include "iwl-trans.h" 6 #include "iwl-fh.h" 7 #include "iwl-context-info-gen3.h" 8 #include "internal.h" 9 #include "iwl-prph.h" 10 11 static void 12 iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans, 13 struct iwl_prph_scratch_hwm_cfg *dbg_cfg, 14 u32 *control_flags) 15 { 16 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 17 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 18 u32 dbg_flags = 0; 19 20 if (!iwl_trans_dbg_ini_valid(trans)) { 21 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 22 23 iwl_pcie_alloc_fw_monitor(trans, 0); 24 25 if (fw_mon->size) { 26 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 27 28 IWL_DEBUG_FW(trans, 29 "WRT: Applying DRAM buffer destination\n"); 30 31 dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); 32 dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); 33 } 34 35 goto out; 36 } 37 38 fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id]; 39 40 switch (le32_to_cpu(fw_mon_cfg->buf_location)) { 41 case IWL_FW_INI_LOCATION_SRAM_PATH: 42 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL; 43 IWL_DEBUG_FW(trans, 44 "WRT: Applying SMEM buffer destination\n"); 45 break; 46 47 case IWL_FW_INI_LOCATION_NPK_PATH: 48 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF; 49 IWL_DEBUG_FW(trans, 50 "WRT: Applying NPK buffer destination\n"); 51 break; 52 53 case IWL_FW_INI_LOCATION_DRAM_PATH: 54 if (trans->dbg.fw_mon_ini[alloc_id].num_frags) { 55 struct iwl_dram_data *frag = 56 &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 57 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; 58 dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical); 59 dbg_cfg->hwm_size = cpu_to_le32(frag->size); 60 dbg_cfg->debug_token_config = cpu_to_le32(trans->dbg.ucode_preset); 61 IWL_DEBUG_FW(trans, 62 "WRT: Applying DRAM destination (debug_token_config=%u)\n", 63 dbg_cfg->debug_token_config); 64 IWL_DEBUG_FW(trans, 65 "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n", 66 alloc_id, 67 trans->dbg.fw_mon_ini[alloc_id].num_frags); 68 } 69 break; 70 default: 71 IWL_ERR(trans, "WRT: Invalid buffer destination\n"); 72 } 73 out: 74 if (dbg_flags) 75 *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags; 76 } 77 78 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, 79 const struct fw_img *fw) 80 { 81 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 82 struct iwl_context_info_gen3 *ctxt_info_gen3; 83 struct iwl_prph_scratch *prph_scratch; 84 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl; 85 struct iwl_prph_info *prph_info; 86 u32 control_flags = 0; 87 int ret; 88 int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 89 trans->cfg->min_txq_size); 90 91 switch (trans_pcie->rx_buf_size) { 92 case IWL_AMSDU_DEF: 93 return -EINVAL; 94 case IWL_AMSDU_2K: 95 break; 96 case IWL_AMSDU_4K: 97 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 98 break; 99 case IWL_AMSDU_8K: 100 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 101 /* if firmware supports the ext size, tell it */ 102 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K; 103 break; 104 case IWL_AMSDU_12K: 105 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; 106 /* if firmware supports the ext size, tell it */ 107 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K; 108 break; 109 } 110 111 /* Allocate prph scratch */ 112 prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), 113 &trans_pcie->prph_scratch_dma_addr, 114 GFP_KERNEL); 115 if (!prph_scratch) 116 return -ENOMEM; 117 118 prph_sc_ctrl = &prph_scratch->ctrl_cfg; 119 120 prph_sc_ctrl->version.version = 0; 121 prph_sc_ctrl->version.mac_id = 122 cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV)); 123 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); 124 125 control_flags |= IWL_PRPH_SCRATCH_MTR_MODE; 126 control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT; 127 128 if (trans->trans_cfg->imr_enabled) 129 control_flags |= IWL_PRPH_SCRATCH_IMR_DEBUG_EN; 130 131 /* initialize RX default queue */ 132 prph_sc_ctrl->rbd_cfg.free_rbd_addr = 133 cpu_to_le64(trans_pcie->rxq->bd_dma); 134 135 iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, 136 &control_flags); 137 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); 138 139 /* allocate ucode sections in dram and set addresses */ 140 ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); 141 if (ret) 142 goto err_free_prph_scratch; 143 144 145 /* Allocate prph information 146 * currently we don't assign to the prph info anything, but it would get 147 * assigned later 148 * 149 * We also use the second half of this page to give the device some 150 * dummy TR/CR tail pointers - which shouldn't be necessary as we don't 151 * use this, but the hardware still reads/writes there and we can't let 152 * it go do that with a NULL pointer. 153 */ 154 BUILD_BUG_ON(sizeof(*prph_info) > PAGE_SIZE / 2); 155 prph_info = dma_alloc_coherent(trans->dev, PAGE_SIZE, 156 &trans_pcie->prph_info_dma_addr, 157 GFP_KERNEL); 158 if (!prph_info) { 159 ret = -ENOMEM; 160 goto err_free_prph_scratch; 161 } 162 163 /* Allocate context info */ 164 ctxt_info_gen3 = dma_alloc_coherent(trans->dev, 165 sizeof(*ctxt_info_gen3), 166 &trans_pcie->ctxt_info_dma_addr, 167 GFP_KERNEL); 168 if (!ctxt_info_gen3) { 169 ret = -ENOMEM; 170 goto err_free_prph_info; 171 } 172 173 ctxt_info_gen3->prph_info_base_addr = 174 cpu_to_le64(trans_pcie->prph_info_dma_addr); 175 ctxt_info_gen3->prph_scratch_base_addr = 176 cpu_to_le64(trans_pcie->prph_scratch_dma_addr); 177 ctxt_info_gen3->prph_scratch_size = 178 cpu_to_le32(sizeof(*prph_scratch)); 179 ctxt_info_gen3->cr_head_idx_arr_base_addr = 180 cpu_to_le64(trans_pcie->rxq->rb_stts_dma); 181 ctxt_info_gen3->tr_tail_idx_arr_base_addr = 182 cpu_to_le64(trans_pcie->prph_info_dma_addr + PAGE_SIZE / 2); 183 ctxt_info_gen3->cr_tail_idx_arr_base_addr = 184 cpu_to_le64(trans_pcie->prph_info_dma_addr + 3 * PAGE_SIZE / 4); 185 ctxt_info_gen3->mtr_base_addr = 186 cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr); 187 ctxt_info_gen3->mcr_base_addr = 188 cpu_to_le64(trans_pcie->rxq->used_bd_dma); 189 ctxt_info_gen3->mtr_size = 190 cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size)); 191 ctxt_info_gen3->mcr_size = 192 cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds)); 193 194 trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; 195 trans_pcie->prph_info = prph_info; 196 trans_pcie->prph_scratch = prph_scratch; 197 198 /* Allocate IML */ 199 trans_pcie->iml = dma_alloc_coherent(trans->dev, trans->iml_len, 200 &trans_pcie->iml_dma_addr, 201 GFP_KERNEL); 202 if (!trans_pcie->iml) { 203 ret = -ENOMEM; 204 goto err_free_ctxt_info; 205 } 206 207 memcpy(trans_pcie->iml, trans->iml, trans->iml_len); 208 209 iwl_enable_fw_load_int_ctx_info(trans); 210 211 /* kick FW self load */ 212 iwl_write64(trans, CSR_CTXT_INFO_ADDR, 213 trans_pcie->ctxt_info_dma_addr); 214 iwl_write64(trans, CSR_IML_DATA_ADDR, 215 trans_pcie->iml_dma_addr); 216 iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); 217 218 iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, 219 CSR_AUTO_FUNC_BOOT_ENA); 220 221 return 0; 222 223 err_free_ctxt_info: 224 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 225 trans_pcie->ctxt_info_gen3, 226 trans_pcie->ctxt_info_dma_addr); 227 trans_pcie->ctxt_info_gen3 = NULL; 228 err_free_prph_info: 229 dma_free_coherent(trans->dev, PAGE_SIZE, prph_info, 230 trans_pcie->prph_info_dma_addr); 231 232 err_free_prph_scratch: 233 dma_free_coherent(trans->dev, 234 sizeof(*prph_scratch), 235 prph_scratch, 236 trans_pcie->prph_scratch_dma_addr); 237 return ret; 238 239 } 240 241 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive) 242 { 243 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 244 245 if (trans_pcie->iml) { 246 dma_free_coherent(trans->dev, trans->iml_len, trans_pcie->iml, 247 trans_pcie->iml_dma_addr); 248 trans_pcie->iml_dma_addr = 0; 249 trans_pcie->iml = NULL; 250 } 251 252 iwl_pcie_ctxt_info_free_fw_img(trans); 253 254 if (alive) 255 return; 256 257 if (!trans_pcie->ctxt_info_gen3) 258 return; 259 260 /* ctxt_info_gen3 and prph_scratch are still needed for PNVM load */ 261 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3), 262 trans_pcie->ctxt_info_gen3, 263 trans_pcie->ctxt_info_dma_addr); 264 trans_pcie->ctxt_info_dma_addr = 0; 265 trans_pcie->ctxt_info_gen3 = NULL; 266 267 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), 268 trans_pcie->prph_scratch, 269 trans_pcie->prph_scratch_dma_addr); 270 trans_pcie->prph_scratch_dma_addr = 0; 271 trans_pcie->prph_scratch = NULL; 272 273 /* this is needed for the entire lifetime */ 274 dma_free_coherent(trans->dev, PAGE_SIZE, trans_pcie->prph_info, 275 trans_pcie->prph_info_dma_addr); 276 trans_pcie->prph_info_dma_addr = 0; 277 trans_pcie->prph_info = NULL; 278 } 279 280 int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, 281 const void *data, u32 len) 282 { 283 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 284 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 285 &trans_pcie->prph_scratch->ctrl_cfg; 286 int ret; 287 288 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 289 return 0; 290 291 /* only allocate the DRAM if not allocated yet */ 292 if (!trans->pnvm_loaded) { 293 if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size)) 294 return -EBUSY; 295 296 ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len, 297 &trans_pcie->pnvm_dram); 298 if (ret < 0) { 299 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n", 300 ret); 301 return ret; 302 } 303 } 304 305 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = 306 cpu_to_le64(trans_pcie->pnvm_dram.physical); 307 prph_sc_ctrl->pnvm_cfg.pnvm_size = 308 cpu_to_le32(trans_pcie->pnvm_dram.size); 309 310 return 0; 311 } 312 313 int iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans, 314 const void *data, u32 len) 315 { 316 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 317 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = 318 &trans_pcie->prph_scratch->ctrl_cfg; 319 int ret; 320 321 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 322 return 0; 323 324 /* only allocate the DRAM if not allocated yet */ 325 if (!trans->reduce_power_loaded) { 326 if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size)) 327 return -EBUSY; 328 329 ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len, 330 &trans_pcie->reduce_power_dram); 331 if (ret < 0) { 332 IWL_DEBUG_FW(trans, 333 "Failed to allocate reduce power DMA %d.\n", 334 ret); 335 return ret; 336 } 337 } 338 339 prph_sc_ctrl->reduce_power_cfg.base_addr = 340 cpu_to_le64(trans_pcie->reduce_power_dram.physical); 341 prph_sc_ctrl->reduce_power_cfg.size = 342 cpu_to_le32(trans_pcie->reduce_power_dram.size); 343 344 return 0; 345 }
Cache object: 08017e845445396f223d1f7b1ada4492
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