Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/dev/iwlwifi/pcie/trans.c
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1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2007-2015, 2018-2022 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/debugfs.h> 10 #include <linux/sched.h> 11 #include <linux/bitops.h> 12 #include <linux/gfp.h> 13 #include <linux/vmalloc.h> 14 #include <linux/module.h> 15 #include <linux/wait.h> 16 #include <linux/seq_file.h> 17 #if defined(__FreeBSD__) 18 #include <linux/delay.h> 19 #endif 20 21 #include "iwl-drv.h" 22 #include "iwl-trans.h" 23 #include "iwl-csr.h" 24 #include "iwl-prph.h" 25 #include "iwl-scd.h" 26 #include "iwl-agn-hw.h" 27 #include "fw/error-dump.h" 28 #include "fw/dbg.h" 29 #include "fw/api/tx.h" 30 #include "mei/iwl-mei.h" 31 #include "internal.h" 32 #include "iwl-fh.h" 33 #include "iwl-context-info-gen3.h" 34 35 /* extended range in FW SRAM */ 36 #define IWL_FW_MEM_EXTENDED_START 0x40000 37 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 38 39 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 40 { 41 #define PCI_DUMP_SIZE 352 42 #define PCI_MEM_DUMP_SIZE 64 43 #define PCI_PARENT_DUMP_SIZE 524 44 #define PREFIX_LEN 32 45 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 46 struct pci_dev *pdev = trans_pcie->pci_dev; 47 u32 i, pos, alloc_size, *ptr, *buf; 48 char *prefix; 49 50 if (trans_pcie->pcie_dbg_dumped_once) 51 return; 52 53 /* Should be a multiple of 4 */ 54 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 55 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 56 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 57 58 /* Alloc a max size buffer */ 59 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 60 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 61 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 62 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 63 64 buf = kmalloc(alloc_size, GFP_ATOMIC); 65 if (!buf) 66 return; 67 prefix = (char *)buf + alloc_size - PREFIX_LEN; 68 69 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 70 71 /* Print wifi device registers */ 72 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 73 IWL_ERR(trans, "iwlwifi device config registers:\n"); 74 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 75 if (pci_read_config_dword(pdev, i, ptr)) 76 goto err_read; 77 #if defined(__linux__) 78 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 79 #elif defined(__FreeBSD__) 80 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 81 #endif 82 83 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 84 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 85 *ptr = iwl_read32(trans, i); 86 #if defined(__linux__) 87 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 88 #elif defined(__FreeBSD__) 89 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 90 #endif 91 92 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 93 if (pos) { 94 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 95 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 96 if (pci_read_config_dword(pdev, pos + i, ptr)) 97 goto err_read; 98 #if defined(__linux__) 99 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 100 32, 4, buf, i, 0); 101 #elif defined(__FreeBSD__) 102 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 103 #endif 104 } 105 106 /* Print parent device registers next */ 107 if (!pdev->bus->self) 108 goto out; 109 110 pdev = pdev->bus->self; 111 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 112 113 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 114 pci_name(pdev)); 115 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 116 if (pci_read_config_dword(pdev, i, ptr)) 117 goto err_read; 118 #if defined(__linux__) 119 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 120 #elif defined(__FreeBSD__) 121 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 122 #endif 123 124 /* Print root port AER registers */ 125 pos = 0; 126 pdev = pcie_find_root_port(pdev); 127 if (pdev) 128 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 129 if (pos) { 130 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 131 pci_name(pdev)); 132 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 133 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 134 if (pci_read_config_dword(pdev, pos + i, ptr)) 135 goto err_read; 136 #if defined(__linux__) 137 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 138 4, buf, i, 0); 139 #elif defined(__FreeBSD__) 140 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 141 #endif 142 } 143 goto out; 144 145 err_read: 146 #if defined(__linux__) 147 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 148 #elif defined(__FreeBSD__) 149 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 150 #endif 151 IWL_ERR(trans, "Read failed at 0x%X\n", i); 152 out: 153 trans_pcie->pcie_dbg_dumped_once = 1; 154 kfree(buf); 155 } 156 157 static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, 158 bool retake_ownership) 159 { 160 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 161 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 162 iwl_set_bit(trans, CSR_GP_CNTRL, 163 CSR_GP_CNTRL_REG_FLAG_SW_RESET); 164 else 165 iwl_set_bit(trans, CSR_RESET, 166 CSR_RESET_REG_FLAG_SW_RESET); 167 usleep_range(5000, 6000); 168 169 if (retake_ownership) 170 return iwl_pcie_prepare_card_hw(trans); 171 172 return 0; 173 } 174 175 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 176 { 177 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 178 179 if (!fw_mon->size) 180 return; 181 182 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 183 fw_mon->physical); 184 185 fw_mon->block = NULL; 186 fw_mon->physical = 0; 187 fw_mon->size = 0; 188 } 189 190 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 191 u8 max_power, u8 min_power) 192 { 193 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 194 void *block = NULL; 195 dma_addr_t physical = 0; 196 u32 size = 0; 197 u8 power; 198 199 if (fw_mon->size) 200 return; 201 202 for (power = max_power; power >= min_power; power--) { 203 size = BIT(power); 204 block = dma_alloc_coherent(trans->dev, size, &physical, 205 GFP_KERNEL | __GFP_NOWARN); 206 if (!block) 207 continue; 208 209 IWL_INFO(trans, 210 "Allocated 0x%08x bytes for firmware monitor.\n", 211 size); 212 break; 213 } 214 215 if (WARN_ON_ONCE(!block)) 216 return; 217 218 if (power != max_power) 219 IWL_ERR(trans, 220 "Sorry - debug buffer is only %luK while you requested %luK\n", 221 (unsigned long)BIT(power - 10), 222 (unsigned long)BIT(max_power - 10)); 223 224 fw_mon->block = block; 225 fw_mon->physical = physical; 226 fw_mon->size = size; 227 } 228 229 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 230 { 231 if (!max_power) { 232 /* default max_power is maximum */ 233 max_power = 26; 234 } else { 235 max_power += 11; 236 } 237 238 if (WARN(max_power > 26, 239 "External buffer size for monitor is too big %d, check the FW TLV\n", 240 max_power)) 241 return; 242 243 if (trans->dbg.fw_mon.size) 244 return; 245 246 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 247 } 248 249 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 250 { 251 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 252 ((reg & 0x0000ffff) | (2 << 28))); 253 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 254 } 255 256 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 257 { 258 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 259 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 260 ((reg & 0x0000ffff) | (3 << 28))); 261 } 262 263 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 264 { 265 if (trans->cfg->apmg_not_supported) 266 return; 267 268 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 269 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 270 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 271 ~APMG_PS_CTRL_MSK_PWR_SRC); 272 else 273 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 274 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 275 ~APMG_PS_CTRL_MSK_PWR_SRC); 276 } 277 278 /* PCI registers */ 279 #define PCI_CFG_RETRY_TIMEOUT 0x041 280 281 void iwl_pcie_apm_config(struct iwl_trans *trans) 282 { 283 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 284 u16 lctl; 285 u16 cap; 286 287 /* 288 * L0S states have been found to be unstable with our devices 289 * and in newer hardware they are not officially supported at 290 * all, so we must always set the L0S_DISABLED bit. 291 */ 292 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 293 294 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 295 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 296 297 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 298 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 299 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 300 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 301 trans->ltr_enabled ? "En" : "Dis"); 302 } 303 304 /* 305 * Start up NIC's basic functionality after it has been reset 306 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 307 * NOTE: This does not load uCode nor start the embedded processor 308 */ 309 static int iwl_pcie_apm_init(struct iwl_trans *trans) 310 { 311 int ret; 312 313 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 314 315 /* 316 * Use "set_bit" below rather than "write", to preserve any hardware 317 * bits already set by default after reset. 318 */ 319 320 /* Disable L0S exit timer (platform NMI Work/Around) */ 321 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 322 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 323 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 324 325 /* 326 * Disable L0s without affecting L1; 327 * don't wait for ICH L0s (ICH bug W/A) 328 */ 329 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 330 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 331 332 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 333 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 334 335 /* 336 * Enable HAP INTA (interrupt from management bus) to 337 * wake device's PCI Express link L1a -> L0s 338 */ 339 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 340 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 341 342 iwl_pcie_apm_config(trans); 343 344 /* Configure analog phase-lock-loop before activating to D0A */ 345 if (trans->trans_cfg->base_params->pll_cfg) 346 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 347 348 ret = iwl_finish_nic_init(trans); 349 if (ret) 350 return ret; 351 352 if (trans->cfg->host_interrupt_operation_mode) { 353 /* 354 * This is a bit of an abuse - This is needed for 7260 / 3160 355 * only check host_interrupt_operation_mode even if this is 356 * not related to host_interrupt_operation_mode. 357 * 358 * Enable the oscillator to count wake up time for L1 exit. This 359 * consumes slightly more power (100uA) - but allows to be sure 360 * that we wake up from L1 on time. 361 * 362 * This looks weird: read twice the same register, discard the 363 * value, set a bit, and yet again, read that same register 364 * just to discard the value. But that's the way the hardware 365 * seems to like it. 366 */ 367 iwl_read_prph(trans, OSC_CLK); 368 iwl_read_prph(trans, OSC_CLK); 369 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 370 iwl_read_prph(trans, OSC_CLK); 371 iwl_read_prph(trans, OSC_CLK); 372 } 373 374 /* 375 * Enable DMA clock and wait for it to stabilize. 376 * 377 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "" 378 * bits do not disable clocks. This preserves any hardware 379 * bits already set by default in "CLK_CTRL_REG" after reset. 380 */ 381 if (!trans->cfg->apmg_not_supported) { 382 iwl_write_prph(trans, APMG_CLK_EN_REG, 383 APMG_CLK_VAL_DMA_CLK_RQT); 384 udelay(20); 385 386 /* Disable L1-Active */ 387 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 388 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 389 390 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 391 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 392 APMG_RTC_INT_STT_RFKILL); 393 } 394 395 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 396 397 return 0; 398 } 399 400 /* 401 * Enable LP XTAL to avoid HW bug where device may consume much power if 402 * FW is not loaded after device reset. LP XTAL is disabled by default 403 * after device HW reset. Do it only if XTAL is fed by internal source. 404 * Configure device's "persistence" mode to avoid resetting XTAL again when 405 * SHRD_HW_RST occurs in S3. 406 */ 407 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 408 { 409 int ret; 410 u32 apmg_gp1_reg; 411 u32 apmg_xtal_cfg_reg; 412 u32 dl_cfg_reg; 413 414 /* Force XTAL ON */ 415 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 416 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 417 418 ret = iwl_trans_pcie_sw_reset(trans, true); 419 420 if (!ret) 421 ret = iwl_finish_nic_init(trans); 422 423 if (WARN_ON(ret)) { 424 /* Release XTAL ON request */ 425 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 426 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 427 return; 428 } 429 430 /* 431 * Clear "disable persistence" to avoid LP XTAL resetting when 432 * SHRD_HW_RST is applied in S3. 433 */ 434 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 435 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 436 437 /* 438 * Force APMG XTAL to be active to prevent its disabling by HW 439 * caused by APMG idle state. 440 */ 441 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 442 SHR_APMG_XTAL_CFG_REG); 443 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 444 apmg_xtal_cfg_reg | 445 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 446 447 ret = iwl_trans_pcie_sw_reset(trans, true); 448 if (ret) 449 IWL_ERR(trans, 450 "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n"); 451 452 /* Enable LP XTAL by indirect access through CSR */ 453 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 454 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 455 SHR_APMG_GP1_WF_XTAL_LP_EN | 456 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 457 458 /* Clear delay line clock power up */ 459 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 460 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 461 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 462 463 /* 464 * Enable persistence mode to avoid LP XTAL resetting when 465 * SHRD_HW_RST is applied in S3. 466 */ 467 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 468 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 469 470 /* 471 * Clear "initialization complete" bit to move adapter from 472 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 473 */ 474 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 475 476 /* Activates XTAL resources monitor */ 477 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 478 CSR_MONITOR_XTAL_RESOURCES); 479 480 /* Release XTAL ON request */ 481 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 482 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 483 udelay(10); 484 485 /* Release APMG XTAL */ 486 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 487 apmg_xtal_cfg_reg & 488 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 489 } 490 491 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 492 { 493 int ret; 494 495 /* stop device's busmaster DMA activity */ 496 497 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 498 iwl_set_bit(trans, CSR_GP_CNTRL, 499 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 500 501 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 502 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 503 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 504 100); 505 msleep(100); 506 } else { 507 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 508 509 ret = iwl_poll_bit(trans, CSR_RESET, 510 CSR_RESET_REG_FLAG_MASTER_DISABLED, 511 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 512 } 513 514 if (ret < 0) 515 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 516 517 IWL_DEBUG_INFO(trans, "stop master\n"); 518 } 519 520 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 521 { 522 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 523 524 if (op_mode_leave) { 525 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 526 iwl_pcie_apm_init(trans); 527 528 /* inform ME that we are leaving */ 529 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 530 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 531 APMG_PCIDEV_STT_VAL_WAKE_ME); 532 else if (trans->trans_cfg->device_family >= 533 IWL_DEVICE_FAMILY_8000) { 534 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 535 CSR_RESET_LINK_PWR_MGMT_DISABLED); 536 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 537 CSR_HW_IF_CONFIG_REG_PREPARE | 538 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 539 mdelay(1); 540 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 541 CSR_RESET_LINK_PWR_MGMT_DISABLED); 542 } 543 mdelay(5); 544 } 545 546 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 547 548 /* Stop device's DMA activity */ 549 iwl_pcie_apm_stop_master(trans); 550 551 if (trans->cfg->lp_xtal_workaround) { 552 iwl_pcie_apm_lp_xtal_enable(trans); 553 return; 554 } 555 556 iwl_trans_pcie_sw_reset(trans, false); 557 558 /* 559 * Clear "initialization complete" bit to move adapter from 560 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 561 */ 562 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 563 } 564 565 static int iwl_pcie_nic_init(struct iwl_trans *trans) 566 { 567 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 568 int ret; 569 570 /* nic_init */ 571 spin_lock_bh(&trans_pcie->irq_lock); 572 ret = iwl_pcie_apm_init(trans); 573 spin_unlock_bh(&trans_pcie->irq_lock); 574 575 if (ret) 576 return ret; 577 578 iwl_pcie_set_pwr(trans, false); 579 580 iwl_op_mode_nic_config(trans->op_mode); 581 582 /* Allocate the RX queue, or reset if it is already allocated */ 583 ret = iwl_pcie_rx_init(trans); 584 if (ret) 585 return ret; 586 587 /* Allocate or reset and init all Tx and Command queues */ 588 if (iwl_pcie_tx_init(trans)) { 589 iwl_pcie_rx_free(trans); 590 return -ENOMEM; 591 } 592 593 if (trans->trans_cfg->base_params->shadow_reg_enable) { 594 /* enable shadow regs in HW */ 595 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 596 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 597 } 598 599 return 0; 600 } 601 602 #define HW_READY_TIMEOUT (50) 603 604 /* Note: returns poll_bit return value, which is >= 0 if success */ 605 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 606 { 607 int ret; 608 609 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 610 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 611 612 /* See if we got it */ 613 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 614 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 615 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 616 HW_READY_TIMEOUT); 617 618 if (ret >= 0) 619 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 620 621 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 622 return ret; 623 } 624 625 /* Note: returns standard 0/-ERROR code */ 626 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 627 { 628 int ret; 629 int t = 0; 630 int iter; 631 632 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 633 634 ret = iwl_pcie_set_hw_ready(trans); 635 /* If the card is ready, exit 0 */ 636 if (ret >= 0) { 637 trans->csme_own = false; 638 return 0; 639 } 640 641 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 642 CSR_RESET_LINK_PWR_MGMT_DISABLED); 643 usleep_range(1000, 2000); 644 645 for (iter = 0; iter < 10; iter++) { 646 /* If HW is not ready, prepare the conditions to check again */ 647 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 648 CSR_HW_IF_CONFIG_REG_PREPARE); 649 650 do { 651 ret = iwl_pcie_set_hw_ready(trans); 652 if (ret >= 0) { 653 trans->csme_own = false; 654 return 0; 655 } 656 657 if (iwl_mei_is_connected()) { 658 IWL_DEBUG_INFO(trans, 659 "Couldn't prepare the card but SAP is connected\n"); 660 trans->csme_own = true; 661 if (trans->trans_cfg->device_family != 662 IWL_DEVICE_FAMILY_9000) 663 IWL_ERR(trans, 664 "SAP not supported for this NIC family\n"); 665 666 return -EBUSY; 667 } 668 669 usleep_range(200, 1000); 670 t += 200; 671 } while (t < 150000); 672 msleep(25); 673 } 674 675 IWL_ERR(trans, "Couldn't prepare the card\n"); 676 677 return ret; 678 } 679 680 /* 681 * ucode 682 */ 683 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 684 u32 dst_addr, dma_addr_t phy_addr, 685 u32 byte_cnt) 686 { 687 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 688 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 689 690 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 691 dst_addr); 692 693 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 694 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 695 696 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 697 (iwl_get_dma_hi_addr(phy_addr) 698 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 699 700 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 701 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 702 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 703 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 704 705 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 706 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 707 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 708 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 709 } 710 711 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 712 u32 dst_addr, dma_addr_t phy_addr, 713 u32 byte_cnt) 714 { 715 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 716 int ret; 717 718 trans_pcie->ucode_write_complete = false; 719 720 if (!iwl_trans_grab_nic_access(trans)) 721 return -EIO; 722 723 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 724 byte_cnt); 725 iwl_trans_release_nic_access(trans); 726 727 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 728 trans_pcie->ucode_write_complete, 5 * HZ); 729 if (!ret) { 730 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 731 iwl_trans_pcie_dump_regs(trans); 732 return -ETIMEDOUT; 733 } 734 735 return 0; 736 } 737 738 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 739 const struct fw_desc *section) 740 { 741 u8 *v_addr; 742 dma_addr_t p_addr; 743 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 744 int ret = 0; 745 746 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 747 section_num); 748 749 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 750 GFP_KERNEL | __GFP_NOWARN); 751 if (!v_addr) { 752 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 753 chunk_sz = PAGE_SIZE; 754 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 755 &p_addr, GFP_KERNEL); 756 if (!v_addr) 757 return -ENOMEM; 758 } 759 760 for (offset = 0; offset < section->len; offset += chunk_sz) { 761 u32 copy_size, dst_addr; 762 bool extended_addr = false; 763 764 copy_size = min_t(u32, chunk_sz, section->len - offset); 765 dst_addr = section->offset + offset; 766 767 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 768 dst_addr <= IWL_FW_MEM_EXTENDED_END) 769 extended_addr = true; 770 771 if (extended_addr) 772 iwl_set_bits_prph(trans, LMPM_CHICK, 773 LMPM_CHICK_EXTENDED_ADDR_SPACE); 774 775 memcpy(v_addr, (const u8 *)section->data + offset, copy_size); 776 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 777 copy_size); 778 779 if (extended_addr) 780 iwl_clear_bits_prph(trans, LMPM_CHICK, 781 LMPM_CHICK_EXTENDED_ADDR_SPACE); 782 783 if (ret) { 784 IWL_ERR(trans, 785 "Could not load the [%d] uCode section\n", 786 section_num); 787 break; 788 } 789 } 790 791 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 792 return ret; 793 } 794 795 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 796 const struct fw_img *image, 797 int cpu, 798 int *first_ucode_section) 799 { 800 int shift_param; 801 int i, ret = 0, sec_num = 0x1; 802 u32 val, last_read_idx = 0; 803 804 if (cpu == 1) { 805 shift_param = 0; 806 *first_ucode_section = 0; 807 } else { 808 shift_param = 16; 809 (*first_ucode_section)++; 810 } 811 812 for (i = *first_ucode_section; i < image->num_sec; i++) { 813 last_read_idx = i; 814 815 /* 816 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 817 * CPU1 to CPU2. 818 * PAGING_SEPARATOR_SECTION delimiter - separate between 819 * CPU2 non paged to CPU2 paging sec. 820 */ 821 if (!image->sec[i].data || 822 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 823 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 824 IWL_DEBUG_FW(trans, 825 "Break since Data not valid or Empty section, sec = %d\n", 826 i); 827 break; 828 } 829 830 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 831 if (ret) 832 return ret; 833 834 /* Notify ucode of loaded section number and status */ 835 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 836 val = val | (sec_num << shift_param); 837 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 838 839 sec_num = (sec_num << 1) | 0x1; 840 } 841 842 *first_ucode_section = last_read_idx; 843 844 iwl_enable_interrupts(trans); 845 846 if (trans->trans_cfg->use_tfh) { 847 if (cpu == 1) 848 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 849 0xFFFF); 850 else 851 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 852 0xFFFFFFFF); 853 } else { 854 if (cpu == 1) 855 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 856 0xFFFF); 857 else 858 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 859 0xFFFFFFFF); 860 } 861 862 return 0; 863 } 864 865 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 866 const struct fw_img *image, 867 int cpu, 868 int *first_ucode_section) 869 { 870 int i, ret = 0; 871 u32 last_read_idx = 0; 872 873 if (cpu == 1) 874 *first_ucode_section = 0; 875 else 876 (*first_ucode_section)++; 877 878 for (i = *first_ucode_section; i < image->num_sec; i++) { 879 last_read_idx = i; 880 881 /* 882 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 883 * CPU1 to CPU2. 884 * PAGING_SEPARATOR_SECTION delimiter - separate between 885 * CPU2 non paged to CPU2 paging sec. 886 */ 887 if (!image->sec[i].data || 888 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 889 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 890 IWL_DEBUG_FW(trans, 891 "Break since Data not valid or Empty section, sec = %d\n", 892 i); 893 break; 894 } 895 896 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 897 if (ret) 898 return ret; 899 } 900 901 *first_ucode_section = last_read_idx; 902 903 return 0; 904 } 905 906 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 907 { 908 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 909 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 910 &trans->dbg.fw_mon_cfg[alloc_id]; 911 struct iwl_dram_data *frag; 912 913 if (!iwl_trans_dbg_ini_valid(trans)) 914 return; 915 916 if (le32_to_cpu(fw_mon_cfg->buf_location) == 917 IWL_FW_INI_LOCATION_SRAM_PATH) { 918 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 919 /* set sram monitor by enabling bit 7 */ 920 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 921 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 922 923 return; 924 } 925 926 if (le32_to_cpu(fw_mon_cfg->buf_location) != 927 IWL_FW_INI_LOCATION_DRAM_PATH || 928 !trans->dbg.fw_mon_ini[alloc_id].num_frags) 929 return; 930 931 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 932 933 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 934 alloc_id); 935 936 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 937 frag->physical >> MON_BUFF_SHIFT_VER2); 938 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 939 (frag->physical + frag->size - 256) >> 940 MON_BUFF_SHIFT_VER2); 941 } 942 943 void iwl_pcie_apply_destination(struct iwl_trans *trans) 944 { 945 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 946 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 947 int i; 948 949 if (iwl_trans_dbg_ini_valid(trans)) { 950 iwl_pcie_apply_destination_ini(trans); 951 return; 952 } 953 954 IWL_INFO(trans, "Applying debug destination %s\n", 955 get_fw_dbg_mode_string(dest->monitor_mode)); 956 957 if (dest->monitor_mode == EXTERNAL_MODE) 958 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 959 else 960 IWL_WARN(trans, "PCI should have external buffer debug\n"); 961 962 for (i = 0; i < trans->dbg.n_dest_reg; i++) { 963 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 964 u32 val = le32_to_cpu(dest->reg_ops[i].val); 965 966 switch (dest->reg_ops[i].op) { 967 case CSR_ASSIGN: 968 iwl_write32(trans, addr, val); 969 break; 970 case CSR_SETBIT: 971 iwl_set_bit(trans, addr, BIT(val)); 972 break; 973 case CSR_CLEARBIT: 974 iwl_clear_bit(trans, addr, BIT(val)); 975 break; 976 case PRPH_ASSIGN: 977 iwl_write_prph(trans, addr, val); 978 break; 979 case PRPH_SETBIT: 980 iwl_set_bits_prph(trans, addr, BIT(val)); 981 break; 982 case PRPH_CLEARBIT: 983 iwl_clear_bits_prph(trans, addr, BIT(val)); 984 break; 985 case PRPH_BLOCKBIT: 986 if (iwl_read_prph(trans, addr) & BIT(val)) { 987 IWL_ERR(trans, 988 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 989 val, addr); 990 goto monitor; 991 } 992 break; 993 default: 994 IWL_ERR(trans, "FW debug - unknown OP %d\n", 995 dest->reg_ops[i].op); 996 break; 997 } 998 } 999 1000 monitor: 1001 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 1002 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 1003 fw_mon->physical >> dest->base_shift); 1004 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1005 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 1006 (fw_mon->physical + fw_mon->size - 1007 256) >> dest->end_shift); 1008 else 1009 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 1010 (fw_mon->physical + fw_mon->size) >> 1011 dest->end_shift); 1012 } 1013 } 1014 1015 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 1016 const struct fw_img *image) 1017 { 1018 int ret = 0; 1019 int first_ucode_section; 1020 1021 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1022 image->is_dual_cpus ? "Dual" : "Single"); 1023 1024 /* load to FW the binary non secured sections of CPU1 */ 1025 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1026 if (ret) 1027 return ret; 1028 1029 if (image->is_dual_cpus) { 1030 /* set CPU2 header address */ 1031 iwl_write_prph(trans, 1032 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1033 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1034 1035 /* load to FW the binary sections of CPU2 */ 1036 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1037 &first_ucode_section); 1038 if (ret) 1039 return ret; 1040 } 1041 1042 if (iwl_pcie_dbg_on(trans)) 1043 iwl_pcie_apply_destination(trans); 1044 1045 iwl_enable_interrupts(trans); 1046 1047 /* release CPU reset */ 1048 iwl_write32(trans, CSR_RESET, 0); 1049 1050 return 0; 1051 } 1052 1053 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1054 const struct fw_img *image) 1055 { 1056 int ret = 0; 1057 int first_ucode_section; 1058 1059 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1060 image->is_dual_cpus ? "Dual" : "Single"); 1061 1062 if (iwl_pcie_dbg_on(trans)) 1063 iwl_pcie_apply_destination(trans); 1064 1065 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1066 iwl_read_prph(trans, WFPM_GP2)); 1067 1068 /* 1069 * Set default value. On resume reading the values that were 1070 * zeored can provide debug data on the resume flow. 1071 * This is for debugging only and has no functional impact. 1072 */ 1073 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1074 1075 /* configure the ucode to be ready to get the secured image */ 1076 /* release CPU reset */ 1077 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1078 1079 /* load to FW the binary Secured sections of CPU1 */ 1080 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1081 &first_ucode_section); 1082 if (ret) 1083 return ret; 1084 1085 /* load to FW the binary sections of CPU2 */ 1086 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1087 &first_ucode_section); 1088 } 1089 1090 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1091 { 1092 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1093 bool hw_rfkill = iwl_is_rfkill_set(trans); 1094 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1095 bool report; 1096 1097 if (hw_rfkill) { 1098 set_bit(STATUS_RFKILL_HW, &trans->status); 1099 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1100 } else { 1101 clear_bit(STATUS_RFKILL_HW, &trans->status); 1102 if (trans_pcie->opmode_down) 1103 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1104 } 1105 1106 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1107 1108 if (prev != report) 1109 iwl_trans_pcie_rf_kill(trans, report); 1110 1111 return hw_rfkill; 1112 } 1113 1114 struct iwl_causes_list { 1115 u32 cause_num; 1116 u32 mask_reg; 1117 u8 addr; 1118 }; 1119 1120 static const struct iwl_causes_list causes_list_common[] = { 1121 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1122 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1123 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1124 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1125 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1126 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1127 {MSIX_HW_INT_CAUSES_REG_RESET_DONE, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 1128 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1129 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1130 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1131 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1132 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1133 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1134 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1135 }; 1136 1137 static const struct iwl_causes_list causes_list_pre_bz[] = { 1138 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1139 }; 1140 1141 static const struct iwl_causes_list causes_list_bz[] = { 1142 {MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ, CSR_MSIX_HW_INT_MASK_AD, 0x15}, 1143 }; 1144 1145 static void iwl_pcie_map_list(struct iwl_trans *trans, 1146 const struct iwl_causes_list *causes, 1147 int arr_size, int val) 1148 { 1149 int i; 1150 1151 for (i = 0; i < arr_size; i++) { 1152 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 1153 iwl_clear_bit(trans, causes[i].mask_reg, 1154 causes[i].cause_num); 1155 } 1156 } 1157 1158 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1159 { 1160 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1161 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1162 /* 1163 * Access all non RX causes and map them to the default irq. 1164 * In case we are missing at least one interrupt vector, 1165 * the first interrupt vector will serve non-RX and FBQ causes. 1166 */ 1167 iwl_pcie_map_list(trans, causes_list_common, 1168 ARRAY_SIZE(causes_list_common), val); 1169 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1170 iwl_pcie_map_list(trans, causes_list_bz, 1171 ARRAY_SIZE(causes_list_bz), val); 1172 else 1173 iwl_pcie_map_list(trans, causes_list_pre_bz, 1174 ARRAY_SIZE(causes_list_pre_bz), val); 1175 } 1176 1177 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1178 { 1179 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1180 u32 offset = 1181 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1182 u32 val, idx; 1183 1184 /* 1185 * The first RX queue - fallback queue, which is designated for 1186 * management frame, command responses etc, is always mapped to the 1187 * first interrupt vector. The other RX queues are mapped to 1188 * the other (N - 2) interrupt vectors. 1189 */ 1190 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1191 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1192 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1193 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1194 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1195 } 1196 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1197 1198 val = MSIX_FH_INT_CAUSES_Q(0); 1199 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1200 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1201 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1202 1203 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1204 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1205 } 1206 1207 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1208 { 1209 struct iwl_trans *trans = trans_pcie->trans; 1210 1211 if (!trans_pcie->msix_enabled) { 1212 if (trans->trans_cfg->mq_rx_supported && 1213 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1214 iwl_write_umac_prph(trans, UREG_CHICK, 1215 UREG_CHICK_MSI_ENABLE); 1216 return; 1217 } 1218 /* 1219 * The IVAR table needs to be configured again after reset, 1220 * but if the device is disabled, we can't write to 1221 * prph. 1222 */ 1223 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1224 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1225 1226 /* 1227 * Each cause from the causes list above and the RX causes is 1228 * represented as a byte in the IVAR table. The first nibble 1229 * represents the bound interrupt vector of the cause, the second 1230 * represents no auto clear for this cause. This will be set if its 1231 * interrupt vector is bound to serve other causes. 1232 */ 1233 iwl_pcie_map_rx_causes(trans); 1234 1235 iwl_pcie_map_non_rx_causes(trans); 1236 } 1237 1238 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1239 { 1240 struct iwl_trans *trans = trans_pcie->trans; 1241 1242 iwl_pcie_conf_msix_hw(trans_pcie); 1243 1244 if (!trans_pcie->msix_enabled) 1245 return; 1246 1247 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1248 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1249 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1250 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1251 } 1252 1253 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1254 { 1255 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1256 1257 lockdep_assert_held(&trans_pcie->mutex); 1258 1259 if (trans_pcie->is_down) 1260 return; 1261 1262 trans_pcie->is_down = true; 1263 1264 /* tell the device to stop sending interrupts */ 1265 iwl_disable_interrupts(trans); 1266 1267 /* device going down, Stop using ICT table */ 1268 iwl_pcie_disable_ict(trans); 1269 1270 /* 1271 * If a HW restart happens during firmware loading, 1272 * then the firmware loading might call this function 1273 * and later it might be called again due to the 1274 * restart. So don't process again if the device is 1275 * already dead. 1276 */ 1277 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1278 IWL_DEBUG_INFO(trans, 1279 "DEVICE_ENABLED bit was set and is now cleared\n"); 1280 iwl_pcie_tx_stop(trans); 1281 iwl_pcie_rx_stop(trans); 1282 1283 /* Power-down device's busmaster DMA clocks */ 1284 if (!trans->cfg->apmg_not_supported) { 1285 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1286 APMG_CLK_VAL_DMA_CLK_RQT); 1287 udelay(5); 1288 } 1289 } 1290 1291 /* Make sure (redundant) we've released our request to stay awake */ 1292 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1293 iwl_clear_bit(trans, CSR_GP_CNTRL, 1294 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1295 else 1296 iwl_clear_bit(trans, CSR_GP_CNTRL, 1297 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1298 1299 /* Stop the device, and put it in low power state */ 1300 iwl_pcie_apm_stop(trans, false); 1301 1302 /* re-take ownership to prevent other users from stealing the device */ 1303 iwl_trans_pcie_sw_reset(trans, true); 1304 1305 /* 1306 * Upon stop, the IVAR table gets erased, so msi-x won't 1307 * work. This causes a bug in RF-KILL flows, since the interrupt 1308 * that enables radio won't fire on the correct irq, and the 1309 * driver won't be able to handle the interrupt. 1310 * Configure the IVAR table again after reset. 1311 */ 1312 iwl_pcie_conf_msix_hw(trans_pcie); 1313 1314 /* 1315 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1316 * This is a bug in certain verions of the hardware. 1317 * Certain devices also keep sending HW RF kill interrupt all 1318 * the time, unless the interrupt is ACKed even if the interrupt 1319 * should be masked. Re-ACK all the interrupts here. 1320 */ 1321 iwl_disable_interrupts(trans); 1322 1323 /* clear all status bits */ 1324 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1325 clear_bit(STATUS_INT_ENABLED, &trans->status); 1326 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1327 1328 /* 1329 * Even if we stop the HW, we still want the RF kill 1330 * interrupt 1331 */ 1332 iwl_enable_rfkill_int(trans); 1333 } 1334 1335 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1336 { 1337 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1338 1339 if (trans_pcie->msix_enabled) { 1340 int i; 1341 1342 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1343 synchronize_irq(trans_pcie->msix_entries[i].vector); 1344 } else { 1345 synchronize_irq(trans_pcie->pci_dev->irq); 1346 } 1347 } 1348 1349 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1350 const struct fw_img *fw, bool run_in_rfkill) 1351 { 1352 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1353 bool hw_rfkill; 1354 int ret; 1355 1356 /* This may fail if AMT took ownership of the device */ 1357 if (iwl_pcie_prepare_card_hw(trans)) { 1358 IWL_WARN(trans, "Exit HW not ready\n"); 1359 return -EIO; 1360 } 1361 1362 iwl_enable_rfkill_int(trans); 1363 1364 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1365 1366 /* 1367 * We enabled the RF-Kill interrupt and the handler may very 1368 * well be running. Disable the interrupts to make sure no other 1369 * interrupt can be fired. 1370 */ 1371 iwl_disable_interrupts(trans); 1372 1373 /* Make sure it finished running */ 1374 iwl_pcie_synchronize_irqs(trans); 1375 1376 mutex_lock(&trans_pcie->mutex); 1377 1378 /* If platform's RF_KILL switch is NOT set to KILL */ 1379 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1380 if (hw_rfkill && !run_in_rfkill) { 1381 ret = -ERFKILL; 1382 goto out; 1383 } 1384 1385 /* Someone called stop_device, don't try to start_fw */ 1386 if (trans_pcie->is_down) { 1387 IWL_WARN(trans, 1388 "Can't start_fw since the HW hasn't been started\n"); 1389 ret = -EIO; 1390 goto out; 1391 } 1392 1393 /* make sure rfkill handshake bits are cleared */ 1394 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1395 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1396 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1397 1398 /* clear (again), then enable host interrupts */ 1399 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1400 1401 ret = iwl_pcie_nic_init(trans); 1402 if (ret) { 1403 IWL_ERR(trans, "Unable to init nic\n"); 1404 goto out; 1405 } 1406 1407 /* 1408 * Now, we load the firmware and don't want to be interrupted, even 1409 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1410 * FH_TX interrupt which is needed to load the firmware). If the 1411 * RF-Kill switch is toggled, we will find out after having loaded 1412 * the firmware and return the proper value to the caller. 1413 */ 1414 iwl_enable_fw_load_int(trans); 1415 1416 /* really make sure rfkill handshake bits are cleared */ 1417 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1418 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1419 1420 /* Load the given image to the HW */ 1421 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1422 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1423 else 1424 ret = iwl_pcie_load_given_ucode(trans, fw); 1425 1426 /* re-check RF-Kill state since we may have missed the interrupt */ 1427 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1428 if (hw_rfkill && !run_in_rfkill) 1429 ret = -ERFKILL; 1430 1431 out: 1432 mutex_unlock(&trans_pcie->mutex); 1433 return ret; 1434 } 1435 1436 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1437 { 1438 iwl_pcie_reset_ict(trans); 1439 iwl_pcie_tx_start(trans, scd_addr); 1440 } 1441 1442 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1443 bool was_in_rfkill) 1444 { 1445 bool hw_rfkill; 1446 1447 /* 1448 * Check again since the RF kill state may have changed while 1449 * all the interrupts were disabled, in this case we couldn't 1450 * receive the RF kill interrupt and update the state in the 1451 * op_mode. 1452 * Don't call the op_mode if the rkfill state hasn't changed. 1453 * This allows the op_mode to call stop_device from the rfkill 1454 * notification without endless recursion. Under very rare 1455 * circumstances, we might have a small recursion if the rfkill 1456 * state changed exactly now while we were called from stop_device. 1457 * This is very unlikely but can happen and is supported. 1458 */ 1459 hw_rfkill = iwl_is_rfkill_set(trans); 1460 if (hw_rfkill) { 1461 set_bit(STATUS_RFKILL_HW, &trans->status); 1462 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1463 } else { 1464 clear_bit(STATUS_RFKILL_HW, &trans->status); 1465 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1466 } 1467 if (hw_rfkill != was_in_rfkill) 1468 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1469 } 1470 1471 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1472 { 1473 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1474 bool was_in_rfkill; 1475 1476 iwl_op_mode_time_point(trans->op_mode, 1477 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1478 NULL); 1479 1480 mutex_lock(&trans_pcie->mutex); 1481 trans_pcie->opmode_down = true; 1482 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1483 _iwl_trans_pcie_stop_device(trans); 1484 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1485 mutex_unlock(&trans_pcie->mutex); 1486 } 1487 1488 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1489 { 1490 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1491 IWL_TRANS_GET_PCIE_TRANS(trans); 1492 1493 lockdep_assert_held(&trans_pcie->mutex); 1494 1495 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1496 state ? "disabled" : "enabled"); 1497 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1498 if (trans->trans_cfg->gen2) 1499 _iwl_trans_pcie_gen2_stop_device(trans); 1500 else 1501 _iwl_trans_pcie_stop_device(trans); 1502 } 1503 } 1504 1505 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1506 bool test, bool reset) 1507 { 1508 iwl_disable_interrupts(trans); 1509 1510 /* 1511 * in testing mode, the host stays awake and the 1512 * hardware won't be reset (not even partially) 1513 */ 1514 if (test) 1515 return; 1516 1517 iwl_pcie_disable_ict(trans); 1518 1519 iwl_pcie_synchronize_irqs(trans); 1520 1521 iwl_clear_bit(trans, CSR_GP_CNTRL, 1522 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1523 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1524 1525 if (reset) { 1526 /* 1527 * reset TX queues -- some of their registers reset during S3 1528 * so if we don't reset everything here the D3 image would try 1529 * to execute some invalid memory upon resume 1530 */ 1531 iwl_trans_pcie_tx_reset(trans); 1532 } 1533 1534 iwl_pcie_set_pwr(trans, true); 1535 } 1536 1537 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) 1538 { 1539 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1540 int ret; 1541 1542 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) { 1543 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1544 suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : 1545 UREG_DOORBELL_TO_ISR6_RESUME); 1546 } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 1547 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, 1548 suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : 1549 CSR_IPC_SLEEP_CONTROL_RESUME); 1550 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1551 UREG_DOORBELL_TO_ISR6_SLEEP_CTRL); 1552 } else { 1553 return 0; 1554 } 1555 1556 ret = wait_event_timeout(trans_pcie->sx_waitq, 1557 trans_pcie->sx_complete, 2 * HZ); 1558 1559 /* Invalidate it toward next suspend or resume */ 1560 trans_pcie->sx_complete = false; 1561 1562 if (!ret) { 1563 IWL_ERR(trans, "Timeout %s D3\n", 1564 suspend ? "entering" : "exiting"); 1565 return -ETIMEDOUT; 1566 } 1567 1568 return 0; 1569 } 1570 1571 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1572 bool reset) 1573 { 1574 int ret; 1575 1576 if (!reset) 1577 /* Enable persistence mode to avoid reset */ 1578 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1579 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1580 1581 ret = iwl_pcie_d3_handshake(trans, true); 1582 if (ret) 1583 return ret; 1584 1585 iwl_pcie_d3_complete_suspend(trans, test, reset); 1586 1587 return 0; 1588 } 1589 1590 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1591 enum iwl_d3_status *status, 1592 bool test, bool reset) 1593 { 1594 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1595 u32 val; 1596 int ret; 1597 1598 if (test) { 1599 iwl_enable_interrupts(trans); 1600 *status = IWL_D3_STATUS_ALIVE; 1601 ret = 0; 1602 goto out; 1603 } 1604 1605 iwl_set_bit(trans, CSR_GP_CNTRL, 1606 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1607 1608 ret = iwl_finish_nic_init(trans); 1609 if (ret) 1610 return ret; 1611 1612 /* 1613 * Reconfigure IVAR table in case of MSIX or reset ict table in 1614 * MSI mode since HW reset erased it. 1615 * Also enables interrupts - none will happen as 1616 * the device doesn't know we're waking it up, only when 1617 * the opmode actually tells it after this call. 1618 */ 1619 iwl_pcie_conf_msix_hw(trans_pcie); 1620 if (!trans_pcie->msix_enabled) 1621 iwl_pcie_reset_ict(trans); 1622 iwl_enable_interrupts(trans); 1623 1624 iwl_pcie_set_pwr(trans, false); 1625 1626 if (!reset) { 1627 iwl_clear_bit(trans, CSR_GP_CNTRL, 1628 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1629 } else { 1630 iwl_trans_pcie_tx_reset(trans); 1631 1632 ret = iwl_pcie_rx_init(trans); 1633 if (ret) { 1634 IWL_ERR(trans, 1635 "Failed to resume the device (RX reset)\n"); 1636 return ret; 1637 } 1638 } 1639 1640 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1641 iwl_read_umac_prph(trans, WFPM_GP2)); 1642 1643 val = iwl_read32(trans, CSR_RESET); 1644 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1645 *status = IWL_D3_STATUS_RESET; 1646 else 1647 *status = IWL_D3_STATUS_ALIVE; 1648 1649 out: 1650 if (*status == IWL_D3_STATUS_ALIVE) 1651 ret = iwl_pcie_d3_handshake(trans, false); 1652 1653 return ret; 1654 } 1655 1656 static void 1657 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1658 struct iwl_trans *trans, 1659 const struct iwl_cfg_trans_params *cfg_trans) 1660 { 1661 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1662 int max_irqs, num_irqs, i, ret; 1663 u16 pci_cmd; 1664 u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 1665 1666 if (!cfg_trans->mq_rx_supported) 1667 goto enable_msi; 1668 1669 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 1670 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 1671 1672 max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 1673 for (i = 0; i < max_irqs; i++) 1674 trans_pcie->msix_entries[i].entry = i; 1675 1676 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1677 MSIX_MIN_INTERRUPT_VECTORS, 1678 max_irqs); 1679 if (num_irqs < 0) { 1680 IWL_DEBUG_INFO(trans, 1681 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1682 num_irqs); 1683 goto enable_msi; 1684 } 1685 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1686 1687 IWL_DEBUG_INFO(trans, 1688 "MSI-X enabled. %d interrupt vectors were allocated\n", 1689 num_irqs); 1690 1691 /* 1692 * In case the OS provides fewer interrupts than requested, different 1693 * causes will share the same interrupt vector as follows: 1694 * One interrupt less: non rx causes shared with FBQ. 1695 * Two interrupts less: non rx causes shared with FBQ and RSS. 1696 * More than two interrupts: we will use fewer RSS queues. 1697 */ 1698 if (num_irqs <= max_irqs - 2) { 1699 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1700 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1701 IWL_SHARED_IRQ_FIRST_RSS; 1702 } else if (num_irqs == max_irqs - 1) { 1703 trans_pcie->trans->num_rx_queues = num_irqs; 1704 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1705 } else { 1706 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1707 } 1708 1709 IWL_DEBUG_INFO(trans, 1710 "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 1711 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 1712 1713 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 1714 1715 trans_pcie->alloc_vecs = num_irqs; 1716 trans_pcie->msix_enabled = true; 1717 return; 1718 1719 enable_msi: 1720 ret = pci_enable_msi(pdev); 1721 if (ret) { 1722 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1723 /* enable rfkill interrupt: hw bug w/a */ 1724 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1725 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1726 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1727 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1728 } 1729 } 1730 } 1731 1732 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1733 { 1734 int iter_rx_q, i, ret, cpu, offset; 1735 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1736 1737 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1738 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1739 offset = 1 + i; 1740 for (; i < iter_rx_q ; i++) { 1741 /* 1742 * Get the cpu prior to the place to search 1743 * (i.e. return will be > i - 1). 1744 */ 1745 cpu = cpumask_next(i - offset, cpu_online_mask); 1746 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1747 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1748 &trans_pcie->affinity_mask[i]); 1749 if (ret) 1750 IWL_ERR(trans_pcie->trans, 1751 "Failed to set affinity mask for IRQ %d\n", 1752 trans_pcie->msix_entries[i].vector); 1753 } 1754 } 1755 1756 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1757 struct iwl_trans_pcie *trans_pcie) 1758 { 1759 int i; 1760 1761 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1762 int ret; 1763 struct msix_entry *msix_entry; 1764 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1765 1766 if (!qname) 1767 return -ENOMEM; 1768 1769 msix_entry = &trans_pcie->msix_entries[i]; 1770 ret = devm_request_threaded_irq(&pdev->dev, 1771 msix_entry->vector, 1772 iwl_pcie_msix_isr, 1773 (i == trans_pcie->def_irq) ? 1774 iwl_pcie_irq_msix_handler : 1775 iwl_pcie_irq_rx_msix_handler, 1776 IRQF_SHARED, 1777 qname, 1778 msix_entry); 1779 if (ret) { 1780 IWL_ERR(trans_pcie->trans, 1781 "Error allocating IRQ %d\n", i); 1782 1783 return ret; 1784 } 1785 } 1786 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1787 1788 return 0; 1789 } 1790 1791 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 1792 { 1793 u32 hpm, wprot; 1794 1795 switch (trans->trans_cfg->device_family) { 1796 case IWL_DEVICE_FAMILY_9000: 1797 wprot = PREG_PRPH_WPROT_9000; 1798 break; 1799 case IWL_DEVICE_FAMILY_22000: 1800 wprot = PREG_PRPH_WPROT_22000; 1801 break; 1802 default: 1803 return 0; 1804 } 1805 1806 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 1807 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 1808 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 1809 1810 if (wprot_val & PREG_WFPM_ACCESS) { 1811 IWL_ERR(trans, 1812 "Error, can not clear persistence bit\n"); 1813 return -EPERM; 1814 } 1815 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 1816 hpm & ~PERSISTENCE_BIT); 1817 } 1818 1819 return 0; 1820 } 1821 1822 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 1823 { 1824 int ret; 1825 1826 ret = iwl_finish_nic_init(trans); 1827 if (ret < 0) 1828 return ret; 1829 1830 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1831 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1832 udelay(20); 1833 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1834 HPM_HIPM_GEN_CFG_CR_PG_EN | 1835 HPM_HIPM_GEN_CFG_CR_SLP_EN); 1836 udelay(20); 1837 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 1838 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1839 1840 return iwl_trans_pcie_sw_reset(trans, true); 1841 } 1842 1843 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1844 { 1845 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1846 int err; 1847 1848 lockdep_assert_held(&trans_pcie->mutex); 1849 1850 err = iwl_pcie_prepare_card_hw(trans); 1851 if (err) { 1852 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1853 return err; 1854 } 1855 1856 err = iwl_trans_pcie_clear_persistence_bit(trans); 1857 if (err) 1858 return err; 1859 1860 err = iwl_trans_pcie_sw_reset(trans, true); 1861 if (err) 1862 return err; 1863 1864 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 1865 trans->trans_cfg->integrated) { 1866 err = iwl_pcie_gen2_force_power_gating(trans); 1867 if (err) 1868 return err; 1869 } 1870 1871 err = iwl_pcie_apm_init(trans); 1872 if (err) 1873 return err; 1874 1875 iwl_pcie_init_msix(trans_pcie); 1876 1877 /* From now on, the op_mode will be kept updated about RF kill state */ 1878 iwl_enable_rfkill_int(trans); 1879 1880 trans_pcie->opmode_down = false; 1881 1882 /* Set is_down to false here so that...*/ 1883 trans_pcie->is_down = false; 1884 1885 /* ...rfkill can call stop_device and set it false if needed */ 1886 iwl_pcie_check_hw_rf_kill(trans); 1887 1888 return 0; 1889 } 1890 1891 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1892 { 1893 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1894 int ret; 1895 1896 mutex_lock(&trans_pcie->mutex); 1897 ret = _iwl_trans_pcie_start_hw(trans); 1898 mutex_unlock(&trans_pcie->mutex); 1899 1900 return ret; 1901 } 1902 1903 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1904 { 1905 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1906 1907 mutex_lock(&trans_pcie->mutex); 1908 1909 /* disable interrupts - don't enable HW RF kill interrupt */ 1910 iwl_disable_interrupts(trans); 1911 1912 iwl_pcie_apm_stop(trans, true); 1913 1914 iwl_disable_interrupts(trans); 1915 1916 iwl_pcie_disable_ict(trans); 1917 1918 mutex_unlock(&trans_pcie->mutex); 1919 1920 iwl_pcie_synchronize_irqs(trans); 1921 } 1922 1923 #if defined(__linux__) 1924 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1925 { 1926 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1927 } 1928 1929 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1930 { 1931 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1932 } 1933 1934 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1935 { 1936 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1937 } 1938 #elif defined(__FreeBSD__) 1939 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1940 { 1941 1942 IWL_DEBUG_PCI_RW(trans, "W1 %#010x %#04x\n", ofs, val); 1943 bus_write_1((struct resource *)IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base, ofs, val); 1944 } 1945 1946 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1947 { 1948 1949 IWL_DEBUG_PCI_RW(trans, "W4 %#010x %#010x\n", ofs, val); 1950 bus_write_4((struct resource *)IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base, ofs, val); 1951 } 1952 1953 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1954 { 1955 u32 v; 1956 1957 v = bus_read_4((struct resource *)IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base, ofs); 1958 IWL_DEBUG_PCI_RW(trans, "R4 %#010x %#010x\n", ofs, v); 1959 return (v); 1960 } 1961 #endif 1962 1963 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 1964 { 1965 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1966 return 0x00FFFFFF; 1967 else 1968 return 0x000FFFFF; 1969 } 1970 1971 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1972 { 1973 u32 mask = iwl_trans_pcie_prph_msk(trans); 1974 1975 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1976 ((reg & mask) | (3 << 24))); 1977 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1978 } 1979 1980 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1981 u32 val) 1982 { 1983 u32 mask = iwl_trans_pcie_prph_msk(trans); 1984 1985 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1986 ((addr & mask) | (3 << 24))); 1987 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1988 } 1989 1990 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1991 const struct iwl_trans_config *trans_cfg) 1992 { 1993 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1994 1995 /* free all first - we might be reconfigured for a different size */ 1996 iwl_pcie_free_rbs_pool(trans); 1997 1998 trans->txqs.cmd.q_id = trans_cfg->cmd_queue; 1999 trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; 2000 trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 2001 trans->txqs.page_offs = trans_cfg->cb_data_offs; 2002 trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 2003 trans->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver; 2004 2005 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 2006 trans_pcie->n_no_reclaim_cmds = 0; 2007 else 2008 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 2009 if (trans_pcie->n_no_reclaim_cmds) 2010 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 2011 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 2012 2013 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 2014 trans_pcie->rx_page_order = 2015 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 2016 trans_pcie->rx_buf_bytes = 2017 iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 2018 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 2019 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 2020 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 2021 2022 trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; 2023 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 2024 2025 trans->command_groups = trans_cfg->command_groups; 2026 trans->command_groups_size = trans_cfg->command_groups_size; 2027 2028 /* Initialize NAPI here - it should be before registering to mac80211 2029 * in the opmode but after the HW struct is allocated. 2030 * As this function may be called again in some corner cases don't 2031 * do anything if NAPI was already initialized. 2032 */ 2033 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 2034 init_dummy_netdev(&trans_pcie->napi_dev); 2035 2036 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 2037 } 2038 2039 void iwl_trans_pcie_free(struct iwl_trans *trans) 2040 { 2041 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2042 int i; 2043 2044 iwl_pcie_synchronize_irqs(trans); 2045 2046 if (trans->trans_cfg->gen2) 2047 iwl_txq_gen2_tx_free(trans); 2048 else 2049 iwl_pcie_tx_free(trans); 2050 iwl_pcie_rx_free(trans); 2051 2052 if (trans_pcie->rba.alloc_wq) { 2053 destroy_workqueue(trans_pcie->rba.alloc_wq); 2054 trans_pcie->rba.alloc_wq = NULL; 2055 } 2056 2057 if (trans_pcie->msix_enabled) { 2058 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 2059 irq_set_affinity_hint( 2060 trans_pcie->msix_entries[i].vector, 2061 NULL); 2062 } 2063 2064 trans_pcie->msix_enabled = false; 2065 } else { 2066 iwl_pcie_free_ict(trans); 2067 } 2068 2069 iwl_pcie_free_fw_monitor(trans); 2070 2071 if (trans_pcie->pnvm_dram.size) 2072 dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size, 2073 trans_pcie->pnvm_dram.block, 2074 trans_pcie->pnvm_dram.physical); 2075 2076 if (trans_pcie->reduce_power_dram.size) 2077 dma_free_coherent(trans->dev, 2078 trans_pcie->reduce_power_dram.size, 2079 trans_pcie->reduce_power_dram.block, 2080 trans_pcie->reduce_power_dram.physical); 2081 2082 mutex_destroy(&trans_pcie->mutex); 2083 iwl_trans_free(trans); 2084 } 2085 2086 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 2087 { 2088 if (state) 2089 set_bit(STATUS_TPOWER_PMI, &trans->status); 2090 else 2091 clear_bit(STATUS_TPOWER_PMI, &trans->status); 2092 } 2093 2094 struct iwl_trans_pcie_removal { 2095 struct pci_dev *pdev; 2096 struct work_struct work; 2097 }; 2098 2099 static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 2100 { 2101 struct iwl_trans_pcie_removal *removal = 2102 container_of(wk, struct iwl_trans_pcie_removal, work); 2103 struct pci_dev *pdev = removal->pdev; 2104 static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 2105 2106 dev_err(&pdev->dev, "Device gone - attempting removal\n"); 2107 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 2108 pci_lock_rescan_remove(); 2109 pci_dev_put(pdev); 2110 pci_stop_and_remove_bus_device(pdev); 2111 pci_unlock_rescan_remove(); 2112 2113 kfree(removal); 2114 module_put(THIS_MODULE); 2115 } 2116 2117 /* 2118 * This version doesn't disable BHs but rather assumes they're 2119 * already disabled. 2120 */ 2121 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2122 { 2123 int ret; 2124 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2125 u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 2126 u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 2127 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 2128 u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2129 2130 spin_lock(&trans_pcie->reg_lock); 2131 2132 if (trans_pcie->cmd_hold_nic_awake) 2133 goto out; 2134 2135 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 2136 write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 2137 mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2138 poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2139 } 2140 2141 /* this bit wakes up the NIC */ 2142 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); 2143 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2144 udelay(2); 2145 2146 /* 2147 * These bits say the device is running, and should keep running for 2148 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2149 * but they do not indicate that embedded SRAM is restored yet; 2150 * HW with volatile SRAM must save/restore contents to/from 2151 * host DRAM when sleeping/waking for power-saving. 2152 * Each direction takes approximately 1/4 millisecond; with this 2153 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2154 * series of register accesses are expected (e.g. reading Event Log), 2155 * to keep device from sleeping. 2156 * 2157 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2158 * SRAM is okay/restored. We don't check that here because this call 2159 * is just for hardware register access; but GP1 MAC_SLEEP 2160 * check is a good idea before accessing the SRAM of HW with 2161 * volatile SRAM (e.g. reading Event Log). 2162 * 2163 * 5000 series and later (including 1000 series) have non-volatile SRAM, 2164 * and do not save/restore SRAM when power cycling. 2165 */ 2166 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); 2167 if (unlikely(ret < 0)) { 2168 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 2169 2170 WARN_ONCE(1, 2171 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 2172 cntrl); 2173 2174 iwl_trans_pcie_dump_regs(trans); 2175 2176 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 2177 struct iwl_trans_pcie_removal *removal; 2178 2179 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2180 goto err; 2181 2182 IWL_ERR(trans, "Device gone - scheduling removal!\n"); 2183 2184 /* 2185 * get a module reference to avoid doing this 2186 * while unloading anyway and to avoid 2187 * scheduling a work with code that's being 2188 * removed. 2189 */ 2190 if (!try_module_get(THIS_MODULE)) { 2191 IWL_ERR(trans, 2192 "Module is being unloaded - abort\n"); 2193 goto err; 2194 } 2195 2196 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2197 if (!removal) { 2198 module_put(THIS_MODULE); 2199 goto err; 2200 } 2201 /* 2202 * we don't need to clear this flag, because 2203 * the trans will be freed and reallocated. 2204 */ 2205 set_bit(STATUS_TRANS_DEAD, &trans->status); 2206 2207 removal->pdev = to_pci_dev(trans->dev); 2208 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2209 pci_dev_get(removal->pdev); 2210 schedule_work(&removal->work); 2211 } else { 2212 iwl_write32(trans, CSR_RESET, 2213 CSR_RESET_REG_FLAG_FORCE_NMI); 2214 } 2215 2216 err: 2217 spin_unlock(&trans_pcie->reg_lock); 2218 return false; 2219 } 2220 2221 out: 2222 /* 2223 * Fool sparse by faking we release the lock - sparse will 2224 * track nic_access anyway. 2225 */ 2226 __release(&trans_pcie->reg_lock); 2227 return true; 2228 } 2229 2230 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2231 { 2232 bool ret; 2233 2234 local_bh_disable(); 2235 ret = __iwl_trans_pcie_grab_nic_access(trans); 2236 if (ret) { 2237 /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2238 return ret; 2239 } 2240 local_bh_enable(); 2241 return false; 2242 } 2243 2244 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2245 { 2246 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2247 2248 lockdep_assert_held(&trans_pcie->reg_lock); 2249 2250 /* 2251 * Fool sparse by faking we acquiring the lock - sparse will 2252 * track nic_access anyway. 2253 */ 2254 __acquire(&trans_pcie->reg_lock); 2255 2256 if (trans_pcie->cmd_hold_nic_awake) 2257 goto out; 2258 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 2259 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2260 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 2261 else 2262 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2263 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2264 /* 2265 * Above we read the CSR_GP_CNTRL register, which will flush 2266 * any previous writes, but we need the write that clears the 2267 * MAC_ACCESS_REQ bit to be performed before any other writes 2268 * scheduled on different CPUs (after we drop reg_lock). 2269 */ 2270 out: 2271 spin_unlock_bh(&trans_pcie->reg_lock); 2272 } 2273 2274 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2275 void *buf, int dwords) 2276 { 2277 int offs = 0; 2278 u32 *vals = buf; 2279 2280 while (offs < dwords) { 2281 /* limit the time we spin here under lock to 1/2s */ 2282 unsigned long end = jiffies + HZ / 2; 2283 bool resched = false; 2284 2285 if (iwl_trans_grab_nic_access(trans)) { 2286 iwl_write32(trans, HBUS_TARG_MEM_RADDR, 2287 addr + 4 * offs); 2288 2289 while (offs < dwords) { 2290 vals[offs] = iwl_read32(trans, 2291 HBUS_TARG_MEM_RDAT); 2292 offs++; 2293 2294 if (time_after(jiffies, end)) { 2295 resched = true; 2296 break; 2297 } 2298 } 2299 iwl_trans_release_nic_access(trans); 2300 2301 if (resched) 2302 cond_resched(); 2303 } else { 2304 return -EBUSY; 2305 } 2306 } 2307 2308 return 0; 2309 } 2310 2311 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2312 const void *buf, int dwords) 2313 { 2314 int offs, ret = 0; 2315 const u32 *vals = buf; 2316 2317 if (iwl_trans_grab_nic_access(trans)) { 2318 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2319 for (offs = 0; offs < dwords; offs++) 2320 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2321 vals ? vals[offs] : 0); 2322 iwl_trans_release_nic_access(trans); 2323 } else { 2324 ret = -EBUSY; 2325 } 2326 return ret; 2327 } 2328 2329 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 2330 u32 *val) 2331 { 2332 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 2333 ofs, val); 2334 } 2335 2336 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2337 { 2338 int i; 2339 2340 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 2341 struct iwl_txq *txq = trans->txqs.txq[i]; 2342 2343 if (i == trans->txqs.cmd.q_id) 2344 continue; 2345 2346 spin_lock_bh(&txq->lock); 2347 2348 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2349 txq->block--; 2350 if (!txq->block) { 2351 iwl_write32(trans, HBUS_TARG_WRPTR, 2352 txq->write_ptr | (i << 8)); 2353 } 2354 } else if (block) { 2355 txq->block++; 2356 } 2357 2358 spin_unlock_bh(&txq->lock); 2359 } 2360 } 2361 2362 #define IWL_FLUSH_WAIT_MS 2000 2363 2364 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 2365 struct iwl_trans_rxq_dma_data *data) 2366 { 2367 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2368 2369 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 2370 return -EINVAL; 2371 2372 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 2373 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 2374 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 2375 data->fr_bd_wid = 0; 2376 2377 return 0; 2378 } 2379 2380 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2381 { 2382 struct iwl_txq *txq; 2383 unsigned long now = jiffies; 2384 bool overflow_tx; 2385 u8 wr_ptr; 2386 2387 /* Make sure the NIC is still alive in the bus */ 2388 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2389 return -ENODEV; 2390 2391 if (!test_bit(txq_idx, trans->txqs.queue_used)) 2392 return -EINVAL; 2393 2394 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2395 txq = trans->txqs.txq[txq_idx]; 2396 2397 spin_lock_bh(&txq->lock); 2398 overflow_tx = txq->overflow_tx || 2399 !skb_queue_empty(&txq->overflow_q); 2400 spin_unlock_bh(&txq->lock); 2401 2402 wr_ptr = READ_ONCE(txq->write_ptr); 2403 2404 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 2405 overflow_tx) && 2406 !time_after(jiffies, 2407 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2408 u8 write_ptr = READ_ONCE(txq->write_ptr); 2409 2410 /* 2411 * If write pointer moved during the wait, warn only 2412 * if the TX came from op mode. In case TX came from 2413 * trans layer (overflow TX) don't warn. 2414 */ 2415 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2416 "WR pointer moved while flushing %d -> %d\n", 2417 wr_ptr, write_ptr)) 2418 return -ETIMEDOUT; 2419 wr_ptr = write_ptr; 2420 2421 usleep_range(1000, 2000); 2422 2423 spin_lock_bh(&txq->lock); 2424 overflow_tx = txq->overflow_tx || 2425 !skb_queue_empty(&txq->overflow_q); 2426 spin_unlock_bh(&txq->lock); 2427 } 2428 2429 if (txq->read_ptr != txq->write_ptr) { 2430 IWL_ERR(trans, 2431 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2432 iwl_txq_log_scd_error(trans, txq); 2433 return -ETIMEDOUT; 2434 } 2435 2436 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2437 2438 return 0; 2439 } 2440 2441 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2442 { 2443 int cnt; 2444 int ret = 0; 2445 2446 /* waiting for all the tx frames complete might take a while */ 2447 for (cnt = 0; 2448 cnt < trans->trans_cfg->base_params->num_of_queues; 2449 cnt++) { 2450 2451 if (cnt == trans->txqs.cmd.q_id) 2452 continue; 2453 if (!test_bit(cnt, trans->txqs.queue_used)) 2454 continue; 2455 if (!(BIT(cnt) & txq_bm)) 2456 continue; 2457 2458 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2459 if (ret) 2460 break; 2461 } 2462 2463 return ret; 2464 } 2465 2466 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2467 u32 mask, u32 value) 2468 { 2469 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2470 2471 spin_lock_bh(&trans_pcie->reg_lock); 2472 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2473 spin_unlock_bh(&trans_pcie->reg_lock); 2474 } 2475 2476 static const char *get_csr_string(int cmd) 2477 { 2478 #define IWL_CMD(x) case x: return #x 2479 switch (cmd) { 2480 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2481 IWL_CMD(CSR_INT_COALESCING); 2482 IWL_CMD(CSR_INT); 2483 IWL_CMD(CSR_INT_MASK); 2484 IWL_CMD(CSR_FH_INT_STATUS); 2485 IWL_CMD(CSR_GPIO_IN); 2486 IWL_CMD(CSR_RESET); 2487 IWL_CMD(CSR_GP_CNTRL); 2488 IWL_CMD(CSR_HW_REV); 2489 IWL_CMD(CSR_EEPROM_REG); 2490 IWL_CMD(CSR_EEPROM_GP); 2491 IWL_CMD(CSR_OTP_GP_REG); 2492 IWL_CMD(CSR_GIO_REG); 2493 IWL_CMD(CSR_GP_UCODE_REG); 2494 IWL_CMD(CSR_GP_DRIVER_REG); 2495 IWL_CMD(CSR_UCODE_DRV_GP1); 2496 IWL_CMD(CSR_UCODE_DRV_GP2); 2497 IWL_CMD(CSR_LED_REG); 2498 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2499 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2500 IWL_CMD(CSR_ANA_PLL_CFG); 2501 IWL_CMD(CSR_HW_REV_WA_REG); 2502 IWL_CMD(CSR_MONITOR_STATUS_REG); 2503 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2504 default: 2505 return "UNKNOWN"; 2506 } 2507 #undef IWL_CMD 2508 } 2509 2510 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2511 { 2512 int i; 2513 static const u32 csr_tbl[] = { 2514 CSR_HW_IF_CONFIG_REG, 2515 CSR_INT_COALESCING, 2516 CSR_INT, 2517 CSR_INT_MASK, 2518 CSR_FH_INT_STATUS, 2519 CSR_GPIO_IN, 2520 CSR_RESET, 2521 CSR_GP_CNTRL, 2522 CSR_HW_REV, 2523 CSR_EEPROM_REG, 2524 CSR_EEPROM_GP, 2525 CSR_OTP_GP_REG, 2526 CSR_GIO_REG, 2527 CSR_GP_UCODE_REG, 2528 CSR_GP_DRIVER_REG, 2529 CSR_UCODE_DRV_GP1, 2530 CSR_UCODE_DRV_GP2, 2531 CSR_LED_REG, 2532 CSR_DRAM_INT_TBL_REG, 2533 CSR_GIO_CHICKEN_BITS, 2534 CSR_ANA_PLL_CFG, 2535 CSR_MONITOR_STATUS_REG, 2536 CSR_HW_REV_WA_REG, 2537 CSR_DBG_HPET_MEM_REG 2538 }; 2539 IWL_ERR(trans, "CSR values:\n"); 2540 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2541 "CSR_INT_PERIODIC_REG)\n"); 2542 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2543 IWL_ERR(trans, " %25s: 0X%08x\n", 2544 get_csr_string(csr_tbl[i]), 2545 iwl_read32(trans, csr_tbl[i])); 2546 } 2547 } 2548 2549 #ifdef CONFIG_IWLWIFI_DEBUGFS 2550 /* create and remove of files */ 2551 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2552 debugfs_create_file(#name, mode, parent, trans, \ 2553 &iwl_dbgfs_##name##_ops); \ 2554 } while (0) 2555 2556 /* file operation */ 2557 #define DEBUGFS_READ_FILE_OPS(name) \ 2558 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2559 .read = iwl_dbgfs_##name##_read, \ 2560 .open = simple_open, \ 2561 .llseek = generic_file_llseek, \ 2562 }; 2563 2564 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2565 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2566 .write = iwl_dbgfs_##name##_write, \ 2567 .open = simple_open, \ 2568 .llseek = generic_file_llseek, \ 2569 }; 2570 2571 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2572 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2573 .write = iwl_dbgfs_##name##_write, \ 2574 .read = iwl_dbgfs_##name##_read, \ 2575 .open = simple_open, \ 2576 .llseek = generic_file_llseek, \ 2577 }; 2578 2579 struct iwl_dbgfs_tx_queue_priv { 2580 struct iwl_trans *trans; 2581 }; 2582 2583 struct iwl_dbgfs_tx_queue_state { 2584 loff_t pos; 2585 }; 2586 2587 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2588 { 2589 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2590 struct iwl_dbgfs_tx_queue_state *state; 2591 2592 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2593 return NULL; 2594 2595 state = kmalloc(sizeof(*state), GFP_KERNEL); 2596 if (!state) 2597 return NULL; 2598 state->pos = *pos; 2599 return state; 2600 } 2601 2602 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2603 void *v, loff_t *pos) 2604 { 2605 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2606 struct iwl_dbgfs_tx_queue_state *state = v; 2607 2608 *pos = ++state->pos; 2609 2610 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2611 return NULL; 2612 2613 return state; 2614 } 2615 2616 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2617 { 2618 kfree(v); 2619 } 2620 2621 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2622 { 2623 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2624 struct iwl_dbgfs_tx_queue_state *state = v; 2625 struct iwl_trans *trans = priv->trans; 2626 struct iwl_txq *txq = trans->txqs.txq[state->pos]; 2627 2628 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2629 (unsigned int)state->pos, 2630 !!test_bit(state->pos, trans->txqs.queue_used), 2631 !!test_bit(state->pos, trans->txqs.queue_stopped)); 2632 if (txq) 2633 seq_printf(seq, 2634 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2635 txq->read_ptr, txq->write_ptr, 2636 txq->need_update, txq->frozen, 2637 txq->n_window, txq->ampdu); 2638 else 2639 seq_puts(seq, "(unallocated)"); 2640 2641 if (state->pos == trans->txqs.cmd.q_id) 2642 seq_puts(seq, " (HCMD)"); 2643 seq_puts(seq, "\n"); 2644 2645 return 0; 2646 } 2647 2648 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2649 .start = iwl_dbgfs_tx_queue_seq_start, 2650 .next = iwl_dbgfs_tx_queue_seq_next, 2651 .stop = iwl_dbgfs_tx_queue_seq_stop, 2652 .show = iwl_dbgfs_tx_queue_seq_show, 2653 }; 2654 2655 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2656 { 2657 struct iwl_dbgfs_tx_queue_priv *priv; 2658 2659 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2660 sizeof(*priv)); 2661 2662 if (!priv) 2663 return -ENOMEM; 2664 2665 priv->trans = inode->i_private; 2666 return 0; 2667 } 2668 2669 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2670 char __user *user_buf, 2671 size_t count, loff_t *ppos) 2672 { 2673 struct iwl_trans *trans = file->private_data; 2674 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2675 char *buf; 2676 int pos = 0, i, ret; 2677 size_t bufsz; 2678 2679 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2680 2681 if (!trans_pcie->rxq) 2682 return -EAGAIN; 2683 2684 buf = kzalloc(bufsz, GFP_KERNEL); 2685 if (!buf) 2686 return -ENOMEM; 2687 2688 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2689 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2690 2691 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2692 i); 2693 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2694 rxq->read); 2695 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2696 rxq->write); 2697 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2698 rxq->write_actual); 2699 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2700 rxq->need_update); 2701 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2702 rxq->free_count); 2703 if (rxq->rb_stts) { 2704 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 2705 rxq)); 2706 pos += scnprintf(buf + pos, bufsz - pos, 2707 "\tclosed_rb_num: %u\n", 2708 r & 0x0FFF); 2709 } else { 2710 pos += scnprintf(buf + pos, bufsz - pos, 2711 "\tclosed_rb_num: Not Allocated\n"); 2712 } 2713 } 2714 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2715 kfree(buf); 2716 2717 return ret; 2718 } 2719 2720 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2721 char __user *user_buf, 2722 size_t count, loff_t *ppos) 2723 { 2724 struct iwl_trans *trans = file->private_data; 2725 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2726 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2727 2728 int pos = 0; 2729 char *buf; 2730 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2731 ssize_t ret; 2732 2733 buf = kzalloc(bufsz, GFP_KERNEL); 2734 if (!buf) 2735 return -ENOMEM; 2736 2737 pos += scnprintf(buf + pos, bufsz - pos, 2738 "Interrupt Statistics Report:\n"); 2739 2740 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2741 isr_stats->hw); 2742 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2743 isr_stats->sw); 2744 if (isr_stats->sw || isr_stats->hw) { 2745 pos += scnprintf(buf + pos, bufsz - pos, 2746 "\tLast Restarting Code: 0x%X\n", 2747 isr_stats->err_code); 2748 } 2749 #ifdef CONFIG_IWLWIFI_DEBUG 2750 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2751 isr_stats->sch); 2752 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2753 isr_stats->alive); 2754 #endif 2755 pos += scnprintf(buf + pos, bufsz - pos, 2756 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2757 2758 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2759 isr_stats->ctkill); 2760 2761 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2762 isr_stats->wakeup); 2763 2764 pos += scnprintf(buf + pos, bufsz - pos, 2765 "Rx command responses:\t\t %u\n", isr_stats->rx); 2766 2767 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2768 isr_stats->tx); 2769 2770 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2771 isr_stats->unhandled); 2772 2773 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2774 kfree(buf); 2775 return ret; 2776 } 2777 2778 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2779 const char __user *user_buf, 2780 size_t count, loff_t *ppos) 2781 { 2782 struct iwl_trans *trans = file->private_data; 2783 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2784 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2785 u32 reset_flag; 2786 int ret; 2787 2788 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2789 if (ret) 2790 return ret; 2791 if (reset_flag == 0) 2792 memset(isr_stats, 0, sizeof(*isr_stats)); 2793 2794 return count; 2795 } 2796 2797 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2798 const char __user *user_buf, 2799 size_t count, loff_t *ppos) 2800 { 2801 struct iwl_trans *trans = file->private_data; 2802 2803 iwl_pcie_dump_csr(trans); 2804 2805 return count; 2806 } 2807 2808 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2809 char __user *user_buf, 2810 size_t count, loff_t *ppos) 2811 { 2812 struct iwl_trans *trans = file->private_data; 2813 char *buf = NULL; 2814 ssize_t ret; 2815 2816 ret = iwl_dump_fh(trans, &buf); 2817 if (ret < 0) 2818 return ret; 2819 if (!buf) 2820 return -EINVAL; 2821 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2822 kfree(buf); 2823 return ret; 2824 } 2825 2826 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2827 char __user *user_buf, 2828 size_t count, loff_t *ppos) 2829 { 2830 struct iwl_trans *trans = file->private_data; 2831 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2832 char buf[100]; 2833 int pos; 2834 2835 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2836 trans_pcie->debug_rfkill, 2837 !(iwl_read32(trans, CSR_GP_CNTRL) & 2838 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2839 2840 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2841 } 2842 2843 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2844 const char __user *user_buf, 2845 size_t count, loff_t *ppos) 2846 { 2847 struct iwl_trans *trans = file->private_data; 2848 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2849 bool new_value; 2850 int ret; 2851 2852 ret = kstrtobool_from_user(user_buf, count, &new_value); 2853 if (ret) 2854 return ret; 2855 if (new_value == trans_pcie->debug_rfkill) 2856 return count; 2857 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2858 trans_pcie->debug_rfkill, new_value); 2859 trans_pcie->debug_rfkill = new_value; 2860 iwl_pcie_handle_rfkill_irq(trans); 2861 2862 return count; 2863 } 2864 2865 static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2866 struct file *file) 2867 { 2868 struct iwl_trans *trans = inode->i_private; 2869 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2870 2871 if (!trans->dbg.dest_tlv || 2872 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2873 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2874 return -ENOENT; 2875 } 2876 2877 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2878 return -EBUSY; 2879 2880 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2881 return simple_open(inode, file); 2882 } 2883 2884 static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2885 struct file *file) 2886 { 2887 struct iwl_trans_pcie *trans_pcie = 2888 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2889 2890 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2891 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2892 return 0; 2893 } 2894 2895 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2896 void *buf, ssize_t *size, 2897 ssize_t *bytes_copied) 2898 { 2899 int buf_size_left = count - *bytes_copied; 2900 2901 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2902 if (*size > buf_size_left) 2903 *size = buf_size_left; 2904 2905 *size -= copy_to_user(user_buf, buf, *size); 2906 *bytes_copied += *size; 2907 2908 if (buf_size_left == *size) 2909 return true; 2910 return false; 2911 } 2912 2913 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2914 char __user *user_buf, 2915 size_t count, loff_t *ppos) 2916 { 2917 struct iwl_trans *trans = file->private_data; 2918 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2919 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2920 struct cont_rec *data = &trans_pcie->fw_mon_data; 2921 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2922 ssize_t size, bytes_copied = 0; 2923 bool b_full; 2924 2925 if (trans->dbg.dest_tlv) { 2926 write_ptr_addr = 2927 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 2928 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2929 } else { 2930 write_ptr_addr = MON_BUFF_WRPTR; 2931 wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2932 } 2933 2934 if (unlikely(!trans->dbg.rec_on)) 2935 return 0; 2936 2937 mutex_lock(&data->mutex); 2938 if (data->state == 2939 IWL_FW_MON_DBGFS_STATE_DISABLED) { 2940 mutex_unlock(&data->mutex); 2941 return 0; 2942 } 2943 2944 /* write_ptr position in bytes rather then DW */ 2945 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2946 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2947 2948 if (data->prev_wrap_cnt == wrap_cnt) { 2949 size = write_ptr - data->prev_wr_ptr; 2950 curr_buf = cpu_addr + data->prev_wr_ptr; 2951 b_full = iwl_write_to_user_buf(user_buf, count, 2952 curr_buf, &size, 2953 &bytes_copied); 2954 data->prev_wr_ptr += size; 2955 2956 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2957 write_ptr < data->prev_wr_ptr) { 2958 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2959 curr_buf = cpu_addr + data->prev_wr_ptr; 2960 b_full = iwl_write_to_user_buf(user_buf, count, 2961 curr_buf, &size, 2962 &bytes_copied); 2963 data->prev_wr_ptr += size; 2964 2965 if (!b_full) { 2966 size = write_ptr; 2967 b_full = iwl_write_to_user_buf(user_buf, count, 2968 cpu_addr, &size, 2969 &bytes_copied); 2970 data->prev_wr_ptr = size; 2971 data->prev_wrap_cnt++; 2972 } 2973 } else { 2974 if (data->prev_wrap_cnt == wrap_cnt - 1 && 2975 write_ptr > data->prev_wr_ptr) 2976 IWL_WARN(trans, 2977 "write pointer passed previous write pointer, start copying from the beginning\n"); 2978 else if (!unlikely(data->prev_wrap_cnt == 0 && 2979 data->prev_wr_ptr == 0)) 2980 IWL_WARN(trans, 2981 "monitor data is out of sync, start copying from the beginning\n"); 2982 2983 size = write_ptr; 2984 b_full = iwl_write_to_user_buf(user_buf, count, 2985 cpu_addr, &size, 2986 &bytes_copied); 2987 data->prev_wr_ptr = size; 2988 data->prev_wrap_cnt = wrap_cnt; 2989 } 2990 2991 mutex_unlock(&data->mutex); 2992 2993 return bytes_copied; 2994 } 2995 2996 static ssize_t iwl_dbgfs_rf_read(struct file *file, 2997 char __user *user_buf, 2998 size_t count, loff_t *ppos) 2999 { 3000 struct iwl_trans *trans = file->private_data; 3001 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3002 3003 if (!trans_pcie->rf_name[0]) 3004 return -ENODEV; 3005 3006 return simple_read_from_buffer(user_buf, count, ppos, 3007 trans_pcie->rf_name, 3008 strlen(trans_pcie->rf_name)); 3009 } 3010 3011 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 3012 DEBUGFS_READ_FILE_OPS(fh_reg); 3013 DEBUGFS_READ_FILE_OPS(rx_queue); 3014 DEBUGFS_WRITE_FILE_OPS(csr); 3015 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 3016 DEBUGFS_READ_FILE_OPS(rf); 3017 3018 static const struct file_operations iwl_dbgfs_tx_queue_ops = { 3019 .owner = THIS_MODULE, 3020 .open = iwl_dbgfs_tx_queue_open, 3021 .read = seq_read, 3022 .llseek = seq_lseek, 3023 .release = seq_release_private, 3024 }; 3025 3026 static const struct file_operations iwl_dbgfs_monitor_data_ops = { 3027 .read = iwl_dbgfs_monitor_data_read, 3028 .open = iwl_dbgfs_monitor_data_open, 3029 .release = iwl_dbgfs_monitor_data_release, 3030 }; 3031 3032 /* Create the debugfs files and directories */ 3033 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 3034 { 3035 struct dentry *dir = trans->dbgfs_dir; 3036 3037 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 3038 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 3039 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 3040 DEBUGFS_ADD_FILE(csr, dir, 0200); 3041 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 3042 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 3043 DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 3044 DEBUGFS_ADD_FILE(rf, dir, 0400); 3045 } 3046 3047 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 3048 { 3049 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3050 struct cont_rec *data = &trans_pcie->fw_mon_data; 3051 3052 mutex_lock(&data->mutex); 3053 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 3054 mutex_unlock(&data->mutex); 3055 } 3056 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 3057 3058 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 3059 { 3060 u32 cmdlen = 0; 3061 int i; 3062 3063 for (i = 0; i < trans->txqs.tfd.max_tbs; i++) 3064 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 3065 3066 return cmdlen; 3067 } 3068 3069 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3070 struct iwl_fw_error_dump_data **data, 3071 int allocated_rb_nums) 3072 { 3073 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3074 int max_len = trans_pcie->rx_buf_bytes; 3075 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3076 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3077 u32 i, r, j, rb_len = 0; 3078 3079 spin_lock(&rxq->lock); 3080 3081 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 3082 3083 for (i = rxq->read, j = 0; 3084 i != r && j < allocated_rb_nums; 3085 i = (i + 1) & RX_QUEUE_MASK, j++) { 3086 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3087 struct iwl_fw_error_dump_rb *rb; 3088 3089 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 3090 max_len, DMA_FROM_DEVICE); 3091 3092 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3093 3094 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3095 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3096 rb = (void *)(*data)->data; 3097 rb->index = cpu_to_le32(i); 3098 memcpy(rb->data, page_address(rxb->page), max_len); 3099 3100 *data = iwl_fw_error_next_data(*data); 3101 } 3102 3103 spin_unlock(&rxq->lock); 3104 3105 return rb_len; 3106 } 3107 #define IWL_CSR_TO_DUMP (0x250) 3108 3109 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3110 struct iwl_fw_error_dump_data **data) 3111 { 3112 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3113 __le32 *val; 3114 int i; 3115 3116 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3117 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3118 val = (void *)(*data)->data; 3119 3120 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3121 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3122 3123 *data = iwl_fw_error_next_data(*data); 3124 3125 return csr_len; 3126 } 3127 3128 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3129 struct iwl_fw_error_dump_data **data) 3130 { 3131 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3132 __le32 *val; 3133 int i; 3134 3135 if (!iwl_trans_grab_nic_access(trans)) 3136 return 0; 3137 3138 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3139 (*data)->len = cpu_to_le32(fh_regs_len); 3140 val = (void *)(*data)->data; 3141 3142 if (!trans->trans_cfg->gen2) 3143 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3144 i += sizeof(u32)) 3145 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3146 else 3147 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3148 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3149 i += sizeof(u32)) 3150 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3151 i)); 3152 3153 iwl_trans_release_nic_access(trans); 3154 3155 *data = iwl_fw_error_next_data(*data); 3156 3157 return sizeof(**data) + fh_regs_len; 3158 } 3159 3160 static u32 3161 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3162 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3163 u32 monitor_len) 3164 { 3165 u32 buf_size_in_dwords = (monitor_len >> 2); 3166 u32 *buffer = (u32 *)fw_mon_data->data; 3167 u32 i; 3168 3169 if (!iwl_trans_grab_nic_access(trans)) 3170 return 0; 3171 3172 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3173 for (i = 0; i < buf_size_in_dwords; i++) 3174 buffer[i] = iwl_read_umac_prph_no_grab(trans, 3175 MON_DMARB_RD_DATA_ADDR); 3176 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3177 3178 iwl_trans_release_nic_access(trans); 3179 3180 return monitor_len; 3181 } 3182 3183 static void 3184 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 3185 struct iwl_fw_error_dump_fw_mon *fw_mon_data) 3186 { 3187 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 3188 3189 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3190 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3191 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3192 write_ptr = DBGC_CUR_DBGBUF_STATUS; 3193 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 3194 } else if (trans->dbg.dest_tlv) { 3195 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3196 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3197 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3198 } else { 3199 base = MON_BUFF_BASE_ADDR; 3200 write_ptr = MON_BUFF_WRPTR; 3201 wrap_cnt = MON_BUFF_CYCLE_CNT; 3202 } 3203 3204 write_ptr_val = iwl_read_prph(trans, write_ptr); 3205 fw_mon_data->fw_mon_cycle_cnt = 3206 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 3207 fw_mon_data->fw_mon_base_ptr = 3208 cpu_to_le32(iwl_read_prph(trans, base)); 3209 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3210 fw_mon_data->fw_mon_base_high_ptr = 3211 cpu_to_le32(iwl_read_prph(trans, base_high)); 3212 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3213 /* convert wrtPtr to DWs, to align with all HWs */ 3214 write_ptr_val >>= 2; 3215 } 3216 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 3217 } 3218 3219 static u32 3220 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3221 struct iwl_fw_error_dump_data **data, 3222 u32 monitor_len) 3223 { 3224 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3225 u32 len = 0; 3226 3227 if (trans->dbg.dest_tlv || 3228 (fw_mon->size && 3229 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3230 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3231 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3232 3233 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3234 fw_mon_data = (void *)(*data)->data; 3235 3236 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3237 3238 len += sizeof(**data) + sizeof(*fw_mon_data); 3239 if (fw_mon->size) { 3240 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 3241 monitor_len = fw_mon->size; 3242 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 3243 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3244 /* 3245 * Update pointers to reflect actual values after 3246 * shifting 3247 */ 3248 if (trans->dbg.dest_tlv->version) { 3249 base = (iwl_read_prph(trans, base) & 3250 IWL_LDBG_M2S_BUF_BA_MSK) << 3251 trans->dbg.dest_tlv->base_shift; 3252 base *= IWL_M2S_UNIT_SIZE; 3253 base += trans->cfg->smem_offset; 3254 } else { 3255 base = iwl_read_prph(trans, base) << 3256 trans->dbg.dest_tlv->base_shift; 3257 } 3258 3259 iwl_trans_read_mem(trans, base, fw_mon_data->data, 3260 monitor_len / sizeof(u32)); 3261 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3262 monitor_len = 3263 iwl_trans_pci_dump_marbh_monitor(trans, 3264 fw_mon_data, 3265 monitor_len); 3266 } else { 3267 /* Didn't match anything - output no monitor data */ 3268 monitor_len = 0; 3269 } 3270 3271 len += monitor_len; 3272 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3273 } 3274 3275 return len; 3276 } 3277 3278 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3279 { 3280 if (trans->dbg.fw_mon.size) { 3281 *len += sizeof(struct iwl_fw_error_dump_data) + 3282 sizeof(struct iwl_fw_error_dump_fw_mon) + 3283 trans->dbg.fw_mon.size; 3284 return trans->dbg.fw_mon.size; 3285 } else if (trans->dbg.dest_tlv) { 3286 u32 base, end, cfg_reg, monitor_len; 3287 3288 if (trans->dbg.dest_tlv->version == 1) { 3289 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3290 cfg_reg = iwl_read_prph(trans, cfg_reg); 3291 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3292 trans->dbg.dest_tlv->base_shift; 3293 base *= IWL_M2S_UNIT_SIZE; 3294 base += trans->cfg->smem_offset; 3295 3296 monitor_len = 3297 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3298 trans->dbg.dest_tlv->end_shift; 3299 monitor_len *= IWL_M2S_UNIT_SIZE; 3300 } else { 3301 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3302 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3303 3304 base = iwl_read_prph(trans, base) << 3305 trans->dbg.dest_tlv->base_shift; 3306 end = iwl_read_prph(trans, end) << 3307 trans->dbg.dest_tlv->end_shift; 3308 3309 /* Make "end" point to the actual end */ 3310 if (trans->trans_cfg->device_family >= 3311 IWL_DEVICE_FAMILY_8000 || 3312 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 3313 end += (1 << trans->dbg.dest_tlv->end_shift); 3314 monitor_len = end - base; 3315 } 3316 *len += sizeof(struct iwl_fw_error_dump_data) + 3317 sizeof(struct iwl_fw_error_dump_fw_mon) + 3318 monitor_len; 3319 return monitor_len; 3320 } 3321 return 0; 3322 } 3323 3324 static struct iwl_trans_dump_data * 3325 iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3326 u32 dump_mask, 3327 const struct iwl_dump_sanitize_ops *sanitize_ops, 3328 void *sanitize_ctx) 3329 { 3330 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3331 struct iwl_fw_error_dump_data *data; 3332 struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; 3333 struct iwl_fw_error_dump_txcmd *txcmd; 3334 struct iwl_trans_dump_data *dump_data; 3335 u32 len, num_rbs = 0, monitor_len = 0; 3336 int i, ptr; 3337 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3338 !trans->trans_cfg->mq_rx_supported && 3339 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 3340 3341 if (!dump_mask) 3342 return NULL; 3343 3344 /* transport dump header */ 3345 len = sizeof(*dump_data); 3346 3347 /* host commands */ 3348 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3349 len += sizeof(*data) + 3350 cmdq->n_window * (sizeof(*txcmd) + 3351 TFD_MAX_PAYLOAD_SIZE); 3352 3353 /* FW monitor */ 3354 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3355 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3356 3357 /* CSR registers */ 3358 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3359 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3360 3361 /* FH registers */ 3362 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3363 if (trans->trans_cfg->gen2) 3364 len += sizeof(*data) + 3365 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3366 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3367 else 3368 len += sizeof(*data) + 3369 (FH_MEM_UPPER_BOUND - 3370 FH_MEM_LOWER_BOUND); 3371 } 3372 3373 if (dump_rbs) { 3374 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3375 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3376 /* RBs */ 3377 num_rbs = 3378 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3379 & 0x0FFF; 3380 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3381 len += num_rbs * (sizeof(*data) + 3382 sizeof(struct iwl_fw_error_dump_rb) + 3383 (PAGE_SIZE << trans_pcie->rx_page_order)); 3384 } 3385 3386 /* Paged memory for gen2 HW */ 3387 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3388 for (i = 0; i < trans->init_dram.paging_cnt; i++) 3389 len += sizeof(*data) + 3390 sizeof(struct iwl_fw_error_dump_paging) + 3391 trans->init_dram.paging[i].size; 3392 3393 dump_data = vzalloc(len); 3394 if (!dump_data) 3395 return NULL; 3396 3397 len = 0; 3398 data = (void *)dump_data->data; 3399 3400 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3401 u16 tfd_size = trans->txqs.tfd.size; 3402 3403 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3404 txcmd = (void *)data->data; 3405 spin_lock_bh(&cmdq->lock); 3406 ptr = cmdq->write_ptr; 3407 for (i = 0; i < cmdq->n_window; i++) { 3408 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 3409 u8 tfdidx; 3410 u32 caplen, cmdlen; 3411 3412 if (trans->trans_cfg->use_tfh) 3413 tfdidx = idx; 3414 else 3415 tfdidx = ptr; 3416 3417 cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3418 (u8 *)cmdq->tfds + 3419 tfd_size * tfdidx); 3420 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3421 3422 if (cmdlen) { 3423 len += sizeof(*txcmd) + caplen; 3424 txcmd->cmdlen = cpu_to_le32(cmdlen); 3425 txcmd->caplen = cpu_to_le32(caplen); 3426 memcpy(txcmd->data, cmdq->entries[idx].cmd, 3427 caplen); 3428 if (sanitize_ops && sanitize_ops->frob_hcmd) 3429 sanitize_ops->frob_hcmd(sanitize_ctx, 3430 txcmd->data, 3431 caplen); 3432 txcmd = (void *)((u8 *)txcmd->data + caplen); 3433 } 3434 3435 ptr = iwl_txq_dec_wrap(trans, ptr); 3436 } 3437 spin_unlock_bh(&cmdq->lock); 3438 3439 data->len = cpu_to_le32(len); 3440 len += sizeof(*data); 3441 data = iwl_fw_error_next_data(data); 3442 } 3443 3444 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3445 len += iwl_trans_pcie_dump_csr(trans, &data); 3446 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3447 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3448 if (dump_rbs) 3449 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3450 3451 /* Paged memory for gen2 HW */ 3452 if (trans->trans_cfg->gen2 && 3453 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3454 for (i = 0; i < trans->init_dram.paging_cnt; i++) { 3455 struct iwl_fw_error_dump_paging *paging; 3456 u32 page_len = trans->init_dram.paging[i].size; 3457 3458 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3459 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3460 paging = (void *)data->data; 3461 paging->index = cpu_to_le32(i); 3462 memcpy(paging->data, 3463 trans->init_dram.paging[i].block, page_len); 3464 data = iwl_fw_error_next_data(data); 3465 3466 len += sizeof(*data) + sizeof(*paging) + page_len; 3467 } 3468 } 3469 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3470 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3471 3472 dump_data->len = len; 3473 3474 return dump_data; 3475 } 3476 3477 static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 3478 { 3479 if (enable) 3480 iwl_enable_interrupts(trans); 3481 else 3482 iwl_disable_interrupts(trans); 3483 } 3484 3485 static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3486 { 3487 u32 inta_addr, sw_err_bit; 3488 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3489 3490 if (trans_pcie->msix_enabled) { 3491 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3492 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3493 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3494 else 3495 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 3496 } else { 3497 inta_addr = CSR_INT; 3498 sw_err_bit = CSR_INT_BIT_SW_ERR; 3499 } 3500 3501 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 3502 } 3503 3504 #define IWL_TRANS_COMMON_OPS \ 3505 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3506 .write8 = iwl_trans_pcie_write8, \ 3507 .write32 = iwl_trans_pcie_write32, \ 3508 .read32 = iwl_trans_pcie_read32, \ 3509 .read_prph = iwl_trans_pcie_read_prph, \ 3510 .write_prph = iwl_trans_pcie_write_prph, \ 3511 .read_mem = iwl_trans_pcie_read_mem, \ 3512 .write_mem = iwl_trans_pcie_write_mem, \ 3513 .read_config32 = iwl_trans_pcie_read_config32, \ 3514 .configure = iwl_trans_pcie_configure, \ 3515 .set_pmi = iwl_trans_pcie_set_pmi, \ 3516 .sw_reset = iwl_trans_pcie_sw_reset, \ 3517 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3518 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3519 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3520 .dump_data = iwl_trans_pcie_dump_data, \ 3521 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3522 .d3_resume = iwl_trans_pcie_d3_resume, \ 3523 .interrupts = iwl_trans_pci_interrupts, \ 3524 .sync_nmi = iwl_trans_pcie_sync_nmi, \ 3525 .imr_dma_data = iwl_trans_pcie_copy_imr \ 3526 3527 static const struct iwl_trans_ops trans_ops_pcie = { 3528 IWL_TRANS_COMMON_OPS, 3529 .start_hw = iwl_trans_pcie_start_hw, 3530 .fw_alive = iwl_trans_pcie_fw_alive, 3531 .start_fw = iwl_trans_pcie_start_fw, 3532 .stop_device = iwl_trans_pcie_stop_device, 3533 3534 .send_cmd = iwl_pcie_enqueue_hcmd, 3535 3536 .tx = iwl_trans_pcie_tx, 3537 .reclaim = iwl_txq_reclaim, 3538 3539 .txq_disable = iwl_trans_pcie_txq_disable, 3540 .txq_enable = iwl_trans_pcie_txq_enable, 3541 3542 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 3543 3544 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3545 3546 .freeze_txq_timer = iwl_trans_txq_freeze_timer, 3547 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3548 #ifdef CONFIG_IWLWIFI_DEBUGFS 3549 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3550 #endif 3551 }; 3552 3553 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3554 IWL_TRANS_COMMON_OPS, 3555 .start_hw = iwl_trans_pcie_start_hw, 3556 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3557 .start_fw = iwl_trans_pcie_gen2_start_fw, 3558 .stop_device = iwl_trans_pcie_gen2_stop_device, 3559 3560 .send_cmd = iwl_pcie_gen2_enqueue_hcmd, 3561 3562 .tx = iwl_txq_gen2_tx, 3563 .reclaim = iwl_txq_reclaim, 3564 3565 .set_q_ptrs = iwl_txq_set_q_ptrs, 3566 3567 .txq_alloc = iwl_txq_dyn_alloc, 3568 .txq_free = iwl_txq_dyn_free, 3569 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 3570 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3571 .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm, 3572 .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power, 3573 #ifdef CONFIG_IWLWIFI_DEBUGFS 3574 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3575 #endif 3576 }; 3577 3578 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3579 const struct pci_device_id *ent, 3580 const struct iwl_cfg_trans_params *cfg_trans) 3581 { 3582 struct iwl_trans_pcie *trans_pcie; 3583 struct iwl_trans *trans; 3584 int ret, addr_size; 3585 const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3586 void __iomem * const *table; 3587 3588 if (!cfg_trans->gen2) 3589 ops = &trans_ops_pcie; 3590 3591 ret = pcim_enable_device(pdev); 3592 if (ret) 3593 return ERR_PTR(ret); 3594 3595 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3596 cfg_trans); 3597 if (!trans) 3598 return ERR_PTR(-ENOMEM); 3599 3600 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3601 3602 trans_pcie->trans = trans; 3603 trans_pcie->opmode_down = true; 3604 spin_lock_init(&trans_pcie->irq_lock); 3605 spin_lock_init(&trans_pcie->reg_lock); 3606 spin_lock_init(&trans_pcie->alloc_page_lock); 3607 mutex_init(&trans_pcie->mutex); 3608 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3609 init_waitqueue_head(&trans_pcie->fw_reset_waitq); 3610 init_waitqueue_head(&trans_pcie->imr_waitq); 3611 3612 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3613 WQ_HIGHPRI | WQ_UNBOUND, 1); 3614 if (!trans_pcie->rba.alloc_wq) { 3615 ret = -ENOMEM; 3616 goto out_free_trans; 3617 } 3618 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3619 3620 trans_pcie->debug_rfkill = -1; 3621 3622 if (!cfg_trans->base_params->pcie_l1_allowed) { 3623 /* 3624 * W/A - seems to solve weird behavior. We need to remove this 3625 * if we don't want to stay in L1 all the time. This wastes a 3626 * lot of power. 3627 */ 3628 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3629 PCIE_LINK_STATE_L1 | 3630 PCIE_LINK_STATE_CLKPM); 3631 } 3632 3633 trans_pcie->def_rx_queue = 0; 3634 3635 pci_set_master(pdev); 3636 3637 addr_size = trans->txqs.tfd.addr_size; 3638 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3639 if (ret) { 3640 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3641 /* both attempts failed: */ 3642 if (ret) { 3643 dev_err(&pdev->dev, "No suitable DMA available\n"); 3644 goto out_no_pci; 3645 } 3646 } 3647 3648 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3649 if (ret) { 3650 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3651 goto out_no_pci; 3652 } 3653 3654 #if defined(__FreeBSD__) 3655 linuxkpi_pcim_want_to_use_bus_functions(pdev); 3656 #endif 3657 table = pcim_iomap_table(pdev); 3658 if (!table) { 3659 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3660 ret = -ENOMEM; 3661 goto out_no_pci; 3662 } 3663 3664 trans_pcie->hw_base = table[0]; 3665 if (!trans_pcie->hw_base) { 3666 dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); 3667 ret = -ENODEV; 3668 goto out_no_pci; 3669 } 3670 3671 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3672 * PCI Tx retries from interfering with C3 CPU state */ 3673 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3674 3675 trans_pcie->pci_dev = pdev; 3676 iwl_disable_interrupts(trans); 3677 3678 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3679 if (trans->hw_rev == 0xffffffff) { 3680 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 3681 ret = -EIO; 3682 goto out_no_pci; 3683 } 3684 3685 /* 3686 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3687 * changed, and now the revision step also includes bit 0-1 (no more 3688 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3689 * in the old format. 3690 */ 3691 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 3692 trans->hw_rev_step = trans->hw_rev & 0xF; 3693 else 3694 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; 3695 3696 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 3697 3698 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3699 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3700 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3701 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3702 3703 init_waitqueue_head(&trans_pcie->sx_waitq); 3704 3705 3706 if (trans_pcie->msix_enabled) { 3707 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3708 if (ret) 3709 goto out_no_pci; 3710 } else { 3711 ret = iwl_pcie_alloc_ict(trans); 3712 if (ret) 3713 goto out_no_pci; 3714 3715 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3716 iwl_pcie_isr, 3717 iwl_pcie_irq_handler, 3718 IRQF_SHARED, DRV_NAME, trans); 3719 if (ret) { 3720 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3721 goto out_free_ict; 3722 } 3723 } 3724 3725 #ifdef CONFIG_IWLWIFI_DEBUGFS 3726 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3727 mutex_init(&trans_pcie->fw_mon_data.mutex); 3728 #endif 3729 3730 iwl_dbg_tlv_init(trans); 3731 3732 return trans; 3733 3734 out_free_ict: 3735 iwl_pcie_free_ict(trans); 3736 out_no_pci: 3737 destroy_workqueue(trans_pcie->rba.alloc_wq); 3738 out_free_trans: 3739 iwl_trans_free(trans); 3740 return ERR_PTR(ret); 3741 } 3742 3743 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans, 3744 u32 dst_addr, u64 src_addr, u32 byte_cnt) 3745 { 3746 iwl_write_prph(trans, IMR_UREG_CHICK, 3747 iwl_read_prph(trans, IMR_UREG_CHICK) | 3748 IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK); 3749 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); 3750 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, 3751 (u32)(src_addr & 0xFFFFFFFF)); 3752 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, 3753 iwl_get_dma_hi_addr(src_addr)); 3754 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); 3755 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, 3756 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS | 3757 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS | 3758 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK); 3759 } 3760 3761 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans, 3762 u32 dst_addr, u64 src_addr, u32 byte_cnt) 3763 { 3764 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3765 int ret = -1; 3766 3767 trans_pcie->imr_status = IMR_D2S_REQUESTED; 3768 iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt); 3769 ret = wait_event_timeout(trans_pcie->imr_waitq, 3770 trans_pcie->imr_status != 3771 IMR_D2S_REQUESTED, 5 * HZ); 3772 if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) { 3773 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n"); 3774 iwl_trans_pcie_dump_regs(trans); 3775 return -ETIMEDOUT; 3776 } 3777 trans_pcie->imr_status = IMR_D2S_IDLE; 3778 return 0; 3779 }
Cache object: 4e8780e5e55d853f17c86be16f8fb92d
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