Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/dev/rtw88/fw.h
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1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_FW_H_ 6 #define __RTW_FW_H_ 7 8 #define H2C_PKT_SIZE 32 9 #define H2C_PKT_HDR_SIZE 8 10 11 /* FW bin information */ 12 #define FW_HDR_SIZE 64 13 #define FW_HDR_CHKSUM_SIZE 8 14 15 #define FW_NLO_INFO_CHECK_SIZE 4 16 17 #define FIFO_PAGE_SIZE_SHIFT 12 18 #define FIFO_PAGE_SIZE 4096 19 #define FIFO_DUMP_ADDR 0x8000 20 21 #define DLFW_PAGE_SIZE_SHIFT_LEGACY 12 22 #define DLFW_PAGE_SIZE_LEGACY 0x1000 23 #define DLFW_BLK_SIZE_SHIFT_LEGACY 2 24 #define DLFW_BLK_SIZE_LEGACY 4 25 #define FW_START_ADDR_LEGACY 0x1000 26 27 #define BCN_LOSS_CNT 10 28 #define BCN_FILTER_NOTIFY_SIGNAL_CHANGE 0 29 #define BCN_FILTER_CONNECTION_LOSS 1 30 #define BCN_FILTER_CONNECTED 2 31 #define BCN_FILTER_NOTIFY_BEACON_LOSS 3 32 33 #define SCAN_NOTIFY_TIMEOUT msecs_to_jiffies(10) 34 35 #define RTW_CHANNEL_TIME 45 36 #define RTW_OFF_CHAN_TIME 100 37 #define RTW_PASS_CHAN_TIME 105 38 #define RTW_DFS_CHAN_TIME 20 39 #define RTW_CH_INFO_SIZE 4 40 #define RTW_EX_CH_INFO_SIZE 3 41 #define RTW_EX_CH_INFO_HDR_SIZE 2 42 #define RTW_SCAN_WIDTH 0 43 #define RTW_PRI_CH_IDX 1 44 #define RTW_PROBE_PG_CNT 2 45 46 enum rtw_c2h_cmd_id { 47 C2H_CCX_TX_RPT = 0x03, 48 C2H_BT_INFO = 0x09, 49 C2H_BT_MP_INFO = 0x0b, 50 C2H_BT_HID_INFO = 0x45, 51 C2H_RA_RPT = 0x0c, 52 C2H_HW_FEATURE_REPORT = 0x19, 53 C2H_WLAN_INFO = 0x27, 54 C2H_WLAN_RFON = 0x32, 55 C2H_BCN_FILTER_NOTIFY = 0x36, 56 C2H_ADAPTIVITY = 0x37, 57 C2H_SCAN_RESULT = 0x38, 58 C2H_HW_FEATURE_DUMP = 0xfd, 59 C2H_HALMAC = 0xff, 60 }; 61 62 enum rtw_c2h_cmd_id_ext { 63 C2H_SCAN_STATUS_RPT = 0x3, 64 C2H_CCX_RPT = 0x0f, 65 C2H_CHAN_SWITCH = 0x22, 66 }; 67 68 struct rtw_c2h_cmd { 69 u8 id; 70 u8 seq; 71 u8 payload[]; 72 } __packed; 73 74 struct rtw_c2h_adaptivity { 75 u8 density; 76 u8 igi; 77 u8 l2h_th_init; 78 u8 l2h; 79 u8 h2l; 80 u8 option; 81 } __packed; 82 83 enum rtw_rsvd_packet_type { 84 RSVD_BEACON, 85 RSVD_DUMMY, 86 RSVD_PS_POLL, 87 RSVD_PROBE_RESP, 88 RSVD_NULL, 89 RSVD_QOS_NULL, 90 RSVD_LPS_PG_DPK, 91 RSVD_LPS_PG_INFO, 92 RSVD_PROBE_REQ, 93 RSVD_NLO_INFO, 94 RSVD_CH_INFO, 95 }; 96 97 enum rtw_fw_rf_type { 98 FW_RF_1T2R = 0, 99 FW_RF_2T4R = 1, 100 FW_RF_2T2R = 2, 101 FW_RF_2T3R = 3, 102 FW_RF_1T1R = 4, 103 FW_RF_2T2R_GREEN = 5, 104 FW_RF_3T3R = 6, 105 FW_RF_3T4R = 7, 106 FW_RF_4T4R = 8, 107 FW_RF_MAX_TYPE = 0xF, 108 }; 109 110 enum rtw_fw_feature { 111 FW_FEATURE_SIG = BIT(0), 112 FW_FEATURE_LPS_C2H = BIT(1), 113 FW_FEATURE_LCLK = BIT(2), 114 FW_FEATURE_PG = BIT(3), 115 FW_FEATURE_TX_WAKE = BIT(4), 116 FW_FEATURE_BCN_FILTER = BIT(5), 117 FW_FEATURE_NOTIFY_SCAN = BIT(6), 118 FW_FEATURE_ADAPTIVITY = BIT(7), 119 FW_FEATURE_SCAN_OFFLOAD = BIT(8), 120 FW_FEATURE_MAX = BIT(31), 121 }; 122 123 enum rtw_beacon_filter_offload_mode { 124 BCN_FILTER_OFFLOAD_MODE_0 = 0, 125 BCN_FILTER_OFFLOAD_MODE_1, 126 BCN_FILTER_OFFLOAD_MODE_2, 127 BCN_FILTER_OFFLOAD_MODE_3, 128 129 BCN_FILTER_OFFLOAD_MODE_DEFAULT = BCN_FILTER_OFFLOAD_MODE_0, 130 }; 131 132 struct rtw_coex_info_req { 133 u8 seq; 134 u8 op_code; 135 u8 para1; 136 u8 para2; 137 u8 para3; 138 }; 139 140 struct rtw_iqk_para { 141 u8 clear; 142 u8 segment_iqk; 143 }; 144 145 struct rtw_lps_pg_dpk_hdr { 146 u16 dpk_path_ok; 147 u8 dpk_txagc[2]; 148 u16 dpk_gs[2]; 149 u32 coef[2][20]; 150 u8 dpk_ch; 151 } __packed; 152 153 struct rtw_lps_pg_info_hdr { 154 u8 macid; 155 u8 mbssid; 156 u8 pattern_count; 157 u8 mu_tab_group_id; 158 u8 sec_cam_count; 159 u8 tx_bu_page_count; 160 u16 rsvd; 161 u8 sec_cam[MAX_PG_CAM_BACKUP_NUM]; 162 } __packed; 163 164 struct rtw_rsvd_page { 165 /* associated with each vif */ 166 struct list_head vif_list; 167 struct rtw_vif *rtwvif; 168 169 /* associated when build rsvd page */ 170 struct list_head build_list; 171 172 struct sk_buff *skb; 173 enum rtw_rsvd_packet_type type; 174 u8 page; 175 u16 tim_offset; 176 bool add_txdesc; 177 struct cfg80211_ssid *ssid; 178 u16 probe_req_size; 179 }; 180 181 enum rtw_keep_alive_pkt_type { 182 KEEP_ALIVE_NULL_PKT = 0, 183 KEEP_ALIVE_ARP_RSP = 1, 184 }; 185 186 struct rtw_nlo_info_hdr { 187 u8 nlo_count; 188 u8 hidden_ap_count; 189 u8 rsvd1[2]; 190 u8 pattern_check[FW_NLO_INFO_CHECK_SIZE]; 191 u8 rsvd2[8]; 192 u8 ssid_len[16]; 193 u8 chiper[16]; 194 u8 rsvd3[16]; 195 u8 location[8]; 196 } __packed; 197 198 enum rtw_packet_type { 199 RTW_PACKET_PROBE_REQ = 0x00, 200 201 RTW_PACKET_UNDEFINE = 0x7FFFFFFF, 202 }; 203 204 struct rtw_fw_wow_keep_alive_para { 205 bool adopt; 206 u8 pkt_type; 207 u8 period; /* unit: sec */ 208 }; 209 210 struct rtw_fw_wow_disconnect_para { 211 bool adopt; 212 u8 period; /* unit: sec */ 213 u8 retry_count; 214 }; 215 216 enum rtw_channel_type { 217 RTW_CHANNEL_PASSIVE, 218 RTW_CHANNEL_ACTIVE, 219 RTW_CHANNEL_RADAR, 220 }; 221 222 enum rtw_scan_extra_id { 223 RTW_SCAN_EXTRA_ID_DFS, 224 }; 225 226 enum rtw_scan_extra_info { 227 RTW_SCAN_EXTRA_ACTION_SCAN, 228 }; 229 230 enum rtw_scan_report_code { 231 RTW_SCAN_REPORT_SUCCESS = 0x00, 232 RTW_SCAN_REPORT_ERR_PHYDM = 0x01, 233 RTW_SCAN_REPORT_ERR_ID = 0x02, 234 RTW_SCAN_REPORT_ERR_TX = 0x03, 235 RTW_SCAN_REPORT_CANCELED = 0x10, 236 RTW_SCAN_REPORT_CANCELED_EXT = 0x11, 237 RTW_SCAN_REPORT_FW_DISABLED = 0xF0, 238 }; 239 240 enum rtw_scan_notify_id { 241 RTW_SCAN_NOTIFY_ID_PRESWITCH = 0x00, 242 RTW_SCAN_NOTIFY_ID_POSTSWITCH = 0x01, 243 RTW_SCAN_NOTIFY_ID_PROBE_PRETX = 0x02, 244 RTW_SCAN_NOTIFY_ID_PROBE_ISSUETX = 0x03, 245 RTW_SCAN_NOTIFY_ID_NULL0_PRETX = 0x04, 246 RTW_SCAN_NOTIFY_ID_NULL0_ISSUETX = 0x05, 247 RTW_SCAN_NOTIFY_ID_NULL0_POSTTX = 0x06, 248 RTW_SCAN_NOTIFY_ID_NULL1_PRETX = 0x07, 249 RTW_SCAN_NOTIFY_ID_NULL1_ISSUETX = 0x08, 250 RTW_SCAN_NOTIFY_ID_NULL1_POSTTX = 0x09, 251 RTW_SCAN_NOTIFY_ID_DWELLEXT = 0x0A, 252 }; 253 254 enum rtw_scan_notify_status { 255 RTW_SCAN_NOTIFY_STATUS_SUCCESS = 0x00, 256 RTW_SCAN_NOTIFY_STATUS_FAILURE = 0x01, 257 RTW_SCAN_NOTIFY_STATUS_RESOURCE = 0x02, 258 RTW_SCAN_NOTIFY_STATUS_TIMEOUT = 0x03, 259 }; 260 261 struct rtw_ch_switch_option { 262 u8 periodic_option; 263 u32 tsf_high; 264 u32 tsf_low; 265 u8 dest_ch_en; 266 u8 absolute_time_en; 267 u8 dest_ch; 268 u8 normal_period; 269 u8 normal_period_sel; 270 u8 normal_cycle; 271 u8 slow_period; 272 u8 slow_period_sel; 273 u8 nlo_en; 274 bool switch_en; 275 bool back_op_en; 276 }; 277 278 struct rtw_fw_hdr { 279 __le16 signature; 280 u8 category; 281 u8 function; 282 __le16 version; /* 0x04 */ 283 u8 subversion; 284 u8 subindex; 285 __le32 rsvd; /* 0x08 */ 286 __le32 feature; /* 0x0C */ 287 u8 month; /* 0x10 */ 288 u8 day; 289 u8 hour; 290 u8 min; 291 __le16 year; /* 0x14 */ 292 __le16 rsvd3; 293 u8 mem_usage; /* 0x18 */ 294 u8 rsvd4[3]; 295 __le16 h2c_fmt_ver; /* 0x1C */ 296 __le16 rsvd5; 297 __le32 dmem_addr; /* 0x20 */ 298 __le32 dmem_size; 299 __le32 rsvd6; 300 __le32 rsvd7; 301 __le32 imem_size; /* 0x30 */ 302 __le32 emem_size; 303 __le32 emem_addr; 304 __le32 imem_addr; 305 } __packed; 306 307 struct rtw_fw_hdr_legacy { 308 __le16 signature; 309 u8 category; 310 u8 function; 311 __le16 version; /* 0x04 */ 312 u8 subversion1; 313 u8 subversion2; 314 u8 month; /* 0x08 */ 315 u8 day; 316 u8 hour; 317 u8 minute; 318 __le16 size; 319 __le16 rsvd2; 320 __le32 idx; /* 0x10 */ 321 __le32 rsvd3; 322 __le32 rsvd4; /* 0x18 */ 323 __le32 rsvd5; 324 } __packed; 325 326 /* C2H */ 327 #define GET_CCX_REPORT_SEQNUM_V0(c2h_payload) (c2h_payload[6] & 0xfc) 328 #define GET_CCX_REPORT_STATUS_V0(c2h_payload) (c2h_payload[0] & 0xc0) 329 #define GET_CCX_REPORT_SEQNUM_V1(c2h_payload) (c2h_payload[8] & 0xfc) 330 #define GET_CCX_REPORT_STATUS_V1(c2h_payload) (c2h_payload[9] & 0xc0) 331 332 #define GET_SCAN_REPORT_RETURN_CODE(c2h_payload) (c2h_payload[2] & 0xff) 333 334 #define GET_CHAN_SWITCH_CENTRAL_CH(c2h_payload) (c2h_payload[2]) 335 #define GET_CHAN_SWITCH_ID(c2h_payload) (c2h_payload[3]) 336 #define GET_CHAN_SWITCH_STATUS(c2h_payload) (c2h_payload[4]) 337 #define GET_RA_REPORT_RATE(c2h_payload) (c2h_payload[0] & 0x7f) 338 #define GET_RA_REPORT_SGI(c2h_payload) ((c2h_payload[0] & 0x80) >> 7) 339 #define GET_RA_REPORT_BW(c2h_payload) (c2h_payload[6]) 340 #define GET_RA_REPORT_MACID(c2h_payload) (c2h_payload[1]) 341 342 #define GET_BCN_FILTER_NOTIFY_TYPE(c2h_payload) (c2h_payload[1] & 0xf) 343 #define GET_BCN_FILTER_NOTIFY_EVENT(c2h_payload) (c2h_payload[1] & 0x10) 344 #define GET_BCN_FILTER_NOTIFY_RSSI(c2h_payload) (c2h_payload[2] - 100) 345 346 /* PKT H2C */ 347 #define H2C_PKT_CMD_ID 0xFF 348 #define H2C_PKT_CATEGORY 0x01 349 350 #define H2C_PKT_GENERAL_INFO 0x0D 351 #define H2C_PKT_PHYDM_INFO 0x11 352 #define H2C_PKT_IQK 0x0E 353 354 #define H2C_PKT_CH_SWITCH 0x02 355 #define H2C_PKT_UPDATE_PKT 0x0C 356 #define H2C_PKT_SCAN_OFFLOAD 0x19 357 358 #define H2C_PKT_CH_SWITCH_LEN 0x20 359 #define H2C_PKT_UPDATE_PKT_LEN 0x4 360 361 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ 362 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0)) 363 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ 364 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 365 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ 366 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16)) 367 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ 368 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0)) 369 370 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id) 371 { 372 SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY); 373 SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID); 374 SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id); 375 } 376 377 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ 378 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16)) 379 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ 380 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 381 382 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ 383 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0)) 384 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ 385 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 386 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ 387 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 388 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ 389 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 390 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \ 391 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28)) 392 #define IQK_SET_CLEAR(h2c_pkt, value) \ 393 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 394 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \ 395 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 396 397 #define CHSW_INFO_SET_CH(pkt, value) \ 398 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0)) 399 #define CHSW_INFO_SET_PRI_CH_IDX(pkt, value) \ 400 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8)) 401 #define CHSW_INFO_SET_BW(pkt, value) \ 402 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12)) 403 #define CHSW_INFO_SET_TIMEOUT(pkt, value) \ 404 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16)) 405 #define CHSW_INFO_SET_ACTION_ID(pkt, value) \ 406 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24)) 407 #define CHSW_INFO_SET_EXTRA_INFO(pkt, value) \ 408 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, BIT(31)) 409 410 #define CH_INFO_SET_CH(pkt, value) \ 411 u8p_replace_bits((u8 *)(pkt) + 0x00, value, GENMASK(7, 0)) 412 #define CH_INFO_SET_PRI_CH_IDX(pkt, value) \ 413 u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(3, 0)) 414 #define CH_INFO_SET_BW(pkt, value) \ 415 u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(7, 4)) 416 #define CH_INFO_SET_TIMEOUT(pkt, value) \ 417 u8p_replace_bits((u8 *)(pkt) + 0x02, value, GENMASK(7, 0)) 418 #define CH_INFO_SET_ACTION_ID(pkt, value) \ 419 u8p_replace_bits((u8 *)(pkt) + 0x03, value, GENMASK(6, 0)) 420 #define CH_INFO_SET_EXTRA_INFO(pkt, value) \ 421 u8p_replace_bits((u8 *)(pkt) + 0x03, value, BIT(7)) 422 423 #define EXTRA_CH_INFO_SET_ID(pkt, value) \ 424 u8p_replace_bits((u8 *)(pkt) + 0x04, value, GENMASK(6, 0)) 425 #define EXTRA_CH_INFO_SET_INFO(pkt, value) \ 426 u8p_replace_bits((u8 *)(pkt) + 0x04, value, BIT(7)) 427 #define EXTRA_CH_INFO_SET_SIZE(pkt, value) \ 428 u8p_replace_bits((u8 *)(pkt) + 0x05, value, GENMASK(7, 0)) 429 #define EXTRA_CH_INFO_SET_DFS_EXT_TIME(pkt, value) \ 430 u8p_replace_bits((u8 *)(pkt) + 0x06, value, GENMASK(7, 0)) 431 432 #define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \ 433 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0)) 434 #define UPDATE_PKT_SET_PKT_ID(h2c_pkt, value) \ 435 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 436 #define UPDATE_PKT_SET_LOCATION(h2c_pkt, value) \ 437 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24)) 438 439 #define CH_SWITCH_SET_START(h2c_pkt, value) \ 440 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 441 #define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \ 442 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 443 #define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \ 444 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2)) 445 #define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \ 446 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3)) 447 #define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value) \ 448 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(5)) 449 #define CH_SWITCH_SET_BACK_OP_EN(h2c_pkt, value) \ 450 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(6)) 451 #define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \ 452 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 453 #define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \ 454 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16)) 455 #define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \ 456 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24)) 457 #define CH_SWITCH_SET_DEST_BW(h2c_pkt, value) \ 458 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28)) 459 #define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \ 460 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0)) 461 #define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \ 462 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8)) 463 #define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \ 464 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14)) 465 #define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \ 466 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16)) 467 #define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \ 468 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22)) 469 #define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \ 470 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24)) 471 #define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \ 472 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0)) 473 #define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \ 474 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0)) 475 #define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \ 476 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0)) 477 478 #define SCAN_OFFLOAD_SET_START(h2c_pkt, value) \ 479 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0)) 480 #define SCAN_OFFLOAD_SET_BACK_OP_EN(h2c_pkt, value) \ 481 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1)) 482 #define SCAN_OFFLOAD_SET_RANDOM_SEQ_EN(h2c_pkt, value) \ 483 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2)) 484 #define SCAN_OFFLOAD_SET_NO_CCK_EN(h2c_pkt, value) \ 485 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(3)) 486 #define SCAN_OFFLOAD_SET_VERBOSE(h2c_pkt, value) \ 487 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(4)) 488 #define SCAN_OFFLOAD_SET_CH_NUM(h2c_pkt, value) \ 489 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8)) 490 #define SCAN_OFFLOAD_SET_CH_INFO_SIZE(h2c_pkt, value) \ 491 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 16)) 492 #define SCAN_OFFLOAD_SET_CH_INFO_LOC(h2c_pkt, value) \ 493 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0)) 494 #define SCAN_OFFLOAD_SET_OP_CH(h2c_pkt, value) \ 495 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 8)) 496 #define SCAN_OFFLOAD_SET_OP_PRI_CH_IDX(h2c_pkt, value) \ 497 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(19, 16)) 498 #define SCAN_OFFLOAD_SET_OP_BW(h2c_pkt, value) \ 499 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 20)) 500 #define SCAN_OFFLOAD_SET_OP_PORT_ID(h2c_pkt, value) \ 501 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(26, 24)) 502 #define SCAN_OFFLOAD_SET_OP_DWELL_TIME(h2c_pkt, value) \ 503 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(15, 0)) 504 #define SCAN_OFFLOAD_SET_OP_GAP_TIME(h2c_pkt, value) \ 505 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 16)) 506 #define SCAN_OFFLOAD_SET_MODE(h2c_pkt, value) \ 507 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(3, 0)) 508 #define SCAN_OFFLOAD_SET_SSID_NUM(h2c_pkt, value) \ 509 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(7, 4)) 510 #define SCAN_OFFLOAD_SET_PKT_LOC(h2c_pkt, value) \ 511 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(15, 8)) 512 513 /* Command H2C */ 514 #define H2C_CMD_RSVD_PAGE 0x0 515 #define H2C_CMD_MEDIA_STATUS_RPT 0x01 516 #define H2C_CMD_SET_PWR_MODE 0x20 517 #define H2C_CMD_LPS_PG_INFO 0x2b 518 #define H2C_CMD_RA_INFO 0x40 519 #define H2C_CMD_RSSI_MONITOR 0x42 520 #define H2C_CMD_BCN_FILTER_OFFLOAD_P0 0x56 521 #define H2C_CMD_BCN_FILTER_OFFLOAD_P1 0x57 522 #define H2C_CMD_WL_PHY_INFO 0x58 523 #define H2C_CMD_SCAN 0x59 524 #define H2C_CMD_ADAPTIVITY 0x5A 525 526 #define H2C_CMD_COEX_TDMA_TYPE 0x60 527 #define H2C_CMD_QUERY_BT_INFO 0x61 528 #define H2C_CMD_FORCE_BT_TX_POWER 0x62 529 #define H2C_CMD_IGNORE_WLAN_ACTION 0x63 530 #define H2C_CMD_WL_CH_INFO 0x66 531 #define H2C_CMD_QUERY_BT_MP_INFO 0x67 532 #define H2C_CMD_BT_WIFI_CONTROL 0x69 533 #define H2C_CMD_WIFI_CALIBRATION 0x6d 534 #define H2C_CMD_QUERY_BT_HID_INFO 0x73 535 536 #define H2C_CMD_KEEP_ALIVE 0x03 537 #define H2C_CMD_DISCONNECT_DECISION 0x04 538 #define H2C_CMD_WOWLAN 0x80 539 #define H2C_CMD_REMOTE_WAKE_CTRL 0x81 540 #define H2C_CMD_AOAC_GLOBAL_INFO 0x82 541 #define H2C_CMD_NLO_INFO 0x8C 542 543 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \ 544 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0)) 545 546 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \ 547 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 548 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \ 549 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 550 551 #define SET_WL_PHY_INFO_TX_TP(h2c_pkt, value) \ 552 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(17, 8)) 553 #define SET_WL_PHY_INFO_RX_TP(h2c_pkt, value) \ 554 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(27, 18)) 555 #define SET_WL_PHY_INFO_TX_RATE_DESC(h2c_pkt, value) \ 556 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 557 #define SET_WL_PHY_INFO_RX_RATE_DESC(h2c_pkt, value) \ 558 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 559 #define SET_WL_PHY_INFO_RX_EVM(h2c_pkt, value) \ 560 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 561 #define SET_BCN_FILTER_OFFLOAD_P1_MACID(h2c_pkt, value) \ 562 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 563 #define SET_BCN_FILTER_OFFLOAD_P1_ENABLE(h2c_pkt, value) \ 564 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(16)) 565 #define SET_BCN_FILTER_OFFLOAD_P1_HYST(h2c_pkt, value) \ 566 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 17)) 567 #define SET_BCN_FILTER_OFFLOAD_P1_OFFLOAD_MODE(h2c_pkt, value) \ 568 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 21)) 569 #define SET_BCN_FILTER_OFFLOAD_P1_THRESHOLD(h2c_pkt, value) \ 570 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 571 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_LOSS_CNT(h2c_pkt, value) \ 572 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(3, 0)) 573 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_INTERVAL(h2c_pkt, value) \ 574 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(13, 4)) 575 576 #define SET_SCAN_START(h2c_pkt, value) \ 577 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 578 579 #define SET_ADAPTIVITY_MODE(h2c_pkt, value) \ 580 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(11, 8)) 581 #define SET_ADAPTIVITY_OPTION(h2c_pkt, value) \ 582 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12)) 583 #define SET_ADAPTIVITY_IGI(h2c_pkt, value) \ 584 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 585 #define SET_ADAPTIVITY_L2H(h2c_pkt, value) \ 586 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 587 #define SET_ADAPTIVITY_DENSITY(h2c_pkt, value) \ 588 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 589 590 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \ 591 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8)) 592 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \ 593 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16)) 594 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \ 595 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20)) 596 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \ 597 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 598 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \ 599 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5)) 600 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \ 601 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 602 #define LPS_PG_INFO_LOC(h2c_pkt, value) \ 603 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 604 #define LPS_PG_DPK_LOC(h2c_pkt, value) \ 605 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 606 #define LPS_PG_SEC_CAM_EN(h2c_pkt, value) \ 607 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 608 #define LPS_PG_PATTERN_CAM_EN(h2c_pkt, value) \ 609 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 610 #define SET_RSSI_INFO_MACID(h2c_pkt, value) \ 611 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 612 #define SET_RSSI_INFO_RSSI(h2c_pkt, value) \ 613 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 614 #define SET_RSSI_INFO_STBC(h2c_pkt, value) \ 615 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1)) 616 #define SET_RA_INFO_MACID(h2c_pkt, value) \ 617 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 618 #define SET_RA_INFO_RATE_ID(h2c_pkt, value) \ 619 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16)) 620 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value) \ 621 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21)) 622 #define SET_RA_INFO_SGI_EN(h2c_pkt, value) \ 623 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23)) 624 #define SET_RA_INFO_BW_MODE(h2c_pkt, value) \ 625 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24)) 626 #define SET_RA_INFO_LDPC(h2c_pkt, value) \ 627 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26)) 628 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value) \ 629 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27)) 630 #define SET_RA_INFO_VHT_EN(h2c_pkt, value) \ 631 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28)) 632 #define SET_RA_INFO_DIS_PT(h2c_pkt, value) \ 633 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30)) 634 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value) \ 635 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 636 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value) \ 637 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 638 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value) \ 639 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 640 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \ 641 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24)) 642 #define SET_QUERY_BT_INFO(h2c_pkt, value) \ 643 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 644 #define SET_WL_CH_INFO_LINK(h2c_pkt, value) \ 645 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 646 #define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \ 647 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 648 #define SET_WL_CH_INFO_BW(h2c_pkt, value) \ 649 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 650 #define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \ 651 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12)) 652 #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \ 653 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 654 #define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \ 655 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 656 #define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \ 657 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 658 #define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \ 659 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 660 #define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \ 661 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 662 #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \ 663 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 664 #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \ 665 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 666 #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \ 667 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 668 #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \ 669 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 670 #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \ 671 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 672 #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \ 673 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 674 #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \ 675 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 676 #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \ 677 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 678 #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \ 679 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 680 #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \ 681 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0)) 682 #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \ 683 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8)) 684 #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \ 685 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16)) 686 687 #define SET_COEX_QUERY_HID_INFO_SUBID(h2c_pkt, value) \ 688 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 689 #define SET_COEX_QUERY_HID_INFO_DATA1(h2c_pkt, value) \ 690 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 691 692 #define SET_KEEP_ALIVE_ENABLE(h2c_pkt, value) \ 693 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 694 #define SET_KEEP_ALIVE_ADOPT(h2c_pkt, value) \ 695 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 696 #define SET_KEEP_ALIVE_PKT_TYPE(h2c_pkt, value) \ 697 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 698 #define SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \ 699 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 700 701 #define SET_DISCONNECT_DECISION_ENABLE(h2c_pkt, value) \ 702 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 703 #define SET_DISCONNECT_DECISION_ADOPT(h2c_pkt, value) \ 704 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 705 #define SET_DISCONNECT_DECISION_CHECK_PERIOD(h2c_pkt, value) \ 706 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 707 #define SET_DISCONNECT_DECISION_TRY_PKT_NUM(h2c_pkt, value) \ 708 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24)) 709 710 #define SET_WOWLAN_FUNC_ENABLE(h2c_pkt, value) \ 711 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 712 #define SET_WOWLAN_PATTERN_MATCH_ENABLE(h2c_pkt, value) \ 713 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 714 #define SET_WOWLAN_MAGIC_PKT_ENABLE(h2c_pkt, value) \ 715 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 716 #define SET_WOWLAN_UNICAST_PKT_ENABLE(h2c_pkt, value) \ 717 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(11)) 718 #define SET_WOWLAN_REKEY_WAKEUP_ENABLE(h2c_pkt, value) \ 719 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(14)) 720 #define SET_WOWLAN_DEAUTH_WAKEUP_ENABLE(h2c_pkt, value) \ 721 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(15)) 722 723 #define SET_REMOTE_WAKECTRL_ENABLE(h2c_pkt, value) \ 724 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 725 #define SET_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(h2c_pkt, value) \ 726 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(12)) 727 728 #define SET_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(h2c_pkt, value) \ 729 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8)) 730 #define SET_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(h2c_pkt, value) \ 731 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 732 733 #define SET_NLO_FUN_EN(h2c_pkt, value) \ 734 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 735 #define SET_NLO_PS_32K(h2c_pkt, value) \ 736 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9)) 737 #define SET_NLO_IGNORE_SECURITY(h2c_pkt, value) \ 738 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10)) 739 #define SET_NLO_LOC_NLO_INFO(h2c_pkt, value) \ 740 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16)) 741 742 #define GET_FW_DUMP_LEN(_header) \ 743 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(15, 0)) 744 #define GET_FW_DUMP_SEQ(_header) \ 745 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(22, 16)) 746 #define GET_FW_DUMP_MORE(_header) \ 747 le32_get_bits(*((__le32 *)(_header) + 0x00), BIT(23)) 748 #define GET_FW_DUMP_VERSION(_header) \ 749 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(31, 24)) 750 #define GET_FW_DUMP_TLV_TYPE(_header) \ 751 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(15, 0)) 752 #define GET_FW_DUMP_TLV_LEN(_header) \ 753 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(31, 16)) 754 #define GET_FW_DUMP_TLV_VAL(_header) \ 755 le32_get_bits(*((__le32 *)(_header) + 0x02), GENMASK(31, 0)) 756 757 #define RFK_SET_INFORM_START(h2c_pkt, value) \ 758 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8)) 759 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb) 760 { 761 u32 pkt_offset; 762 763 pkt_offset = *((u32 *)skb->cb); 764 return (struct rtw_c2h_cmd *)(skb->data + pkt_offset); 765 } 766 767 static inline bool rtw_fw_feature_check(struct rtw_fw_state *fw, 768 enum rtw_fw_feature feature) 769 { 770 return !!(fw->feature & feature); 771 } 772 773 void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset, 774 struct sk_buff *skb); 775 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb); 776 void rtw_fw_send_general_info(struct rtw_dev *rtwdev); 777 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev); 778 779 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para); 780 void rtw_fw_inform_rfk_status(struct rtw_dev *rtwdev, bool start); 781 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev); 782 void rtw_fw_set_pg_info(struct rtw_dev *rtwdev); 783 void rtw_fw_query_bt_info(struct rtw_dev *rtwdev); 784 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw); 785 void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev, 786 struct rtw_coex_info_req *req); 787 void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl); 788 void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable); 789 void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev, 790 u8 para1, u8 para2, u8 para3, u8 para4, u8 para5); 791 void rtw_fw_coex_query_hid_info(struct rtw_dev *rtwdev, u8 sub_id, u8 data); 792 793 void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data); 794 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 795 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 796 bool reset_ra_mask); 797 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn); 798 void rtw_fw_update_wl_phy_info(struct rtw_dev *rtwdev); 799 void rtw_fw_beacon_filter_config(struct rtw_dev *rtwdev, bool connect, 800 struct ieee80211_vif *vif); 801 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr, 802 u8 *buf, u32 size); 803 void rtw_remove_rsvd_page(struct rtw_dev *rtwdev, 804 struct rtw_vif *rtwvif); 805 void rtw_add_rsvd_page_bcn(struct rtw_dev *rtwdev, 806 struct rtw_vif *rtwvif); 807 void rtw_add_rsvd_page_pno(struct rtw_dev *rtwdev, 808 struct rtw_vif *rtwvif); 809 void rtw_add_rsvd_page_sta(struct rtw_dev *rtwdev, 810 struct rtw_vif *rtwvif); 811 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev); 812 void rtw_fw_update_beacon_work(struct work_struct *work); 813 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev); 814 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev, 815 u32 offset, u32 size, u32 *buf); 816 void rtw_fw_set_remote_wake_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); 817 void rtw_fw_set_wowlan_ctrl_cmd(struct rtw_dev *rtwdev, bool enable); 818 void rtw_fw_set_keep_alive_cmd(struct rtw_dev *rtwdev, bool enable); 819 void rtw_fw_set_disconnect_decision_cmd(struct rtw_dev *rtwdev, bool enable); 820 void rtw_fw_set_aoac_global_info_cmd(struct rtw_dev *rtwdev, 821 u8 pairwise_key_enc, 822 u8 group_key_enc); 823 824 void rtw_fw_set_nlo_info(struct rtw_dev *rtwdev, bool enable); 825 void rtw_fw_update_pkt_probe_req(struct rtw_dev *rtwdev, 826 struct cfg80211_ssid *ssid); 827 void rtw_fw_channel_switch(struct rtw_dev *rtwdev, bool enable); 828 void rtw_fw_h2c_cmd_dbg(struct rtw_dev *rtwdev, u8 *h2c); 829 void rtw_fw_c2h_cmd_isr(struct rtw_dev *rtwdev); 830 int rtw_fw_dump_fifo(struct rtw_dev *rtwdev, u8 fifo_sel, u32 addr, u32 size, 831 u32 *buffer); 832 void rtw_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 833 void rtw_fw_adaptivity(struct rtw_dev *rtwdev); 834 void rtw_store_op_chan(struct rtw_dev *rtwdev); 835 void rtw_hw_scan_start(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 836 struct ieee80211_scan_request *req); 837 void rtw_hw_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 838 bool aborted); 839 int rtw_hw_scan_offload(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 840 bool enable); 841 void rtw_hw_scan_status_report(struct rtw_dev *rtwdev, struct sk_buff *skb); 842 void rtw_hw_scan_chan_switch(struct rtw_dev *rtwdev, struct sk_buff *skb); 843 void rtw_hw_scan_abort(struct rtw_dev *rtwdev, struct ieee80211_vif *vif); 844 #endif
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