Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/dev/rtw88/main.c
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1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #if defined(__FreeBSD__) 6 #define LINUXKPI_PARAM_PREFIX rtw88_ 7 #endif 8 9 #include <linux/devcoredump.h> 10 11 #include "main.h" 12 #include "regd.h" 13 #include "fw.h" 14 #include "ps.h" 15 #include "sec.h" 16 #include "mac.h" 17 #include "coex.h" 18 #include "phy.h" 19 #include "reg.h" 20 #include "efuse.h" 21 #include "tx.h" 22 #include "debug.h" 23 #include "bf.h" 24 #include "sar.h" 25 26 bool rtw_disable_lps_deep_mode; 27 EXPORT_SYMBOL(rtw_disable_lps_deep_mode); 28 bool rtw_bf_support = true; 29 unsigned int rtw_debug_mask; 30 EXPORT_SYMBOL(rtw_debug_mask); 31 /* EDCCA is enabled during normal behavior. For debugging purpose in 32 * a noisy environment, it can be disabled via edcca debugfs. Because 33 * all rtw88 devices will probably be affected if environment is noisy, 34 * rtw_edcca_enabled is just declared by driver instead of by device. 35 * So, turning it off will take effect for all rtw88 devices before 36 * there is a tough reason to maintain rtw_edcca_enabled by device. 37 */ 38 bool rtw_edcca_enabled = true; 39 40 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644); 41 module_param_named(support_bf, rtw_bf_support, bool, 0644); 42 module_param_named(debug_mask, rtw_debug_mask, uint, 0644); 43 44 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS"); 45 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support"); 46 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 47 48 static struct ieee80211_channel rtw_channeltable_2g[] = { 49 {.center_freq = 2412, .hw_value = 1,}, 50 {.center_freq = 2417, .hw_value = 2,}, 51 {.center_freq = 2422, .hw_value = 3,}, 52 {.center_freq = 2427, .hw_value = 4,}, 53 {.center_freq = 2432, .hw_value = 5,}, 54 {.center_freq = 2437, .hw_value = 6,}, 55 {.center_freq = 2442, .hw_value = 7,}, 56 {.center_freq = 2447, .hw_value = 8,}, 57 {.center_freq = 2452, .hw_value = 9,}, 58 {.center_freq = 2457, .hw_value = 10,}, 59 {.center_freq = 2462, .hw_value = 11,}, 60 {.center_freq = 2467, .hw_value = 12,}, 61 {.center_freq = 2472, .hw_value = 13,}, 62 {.center_freq = 2484, .hw_value = 14,}, 63 }; 64 65 static struct ieee80211_channel rtw_channeltable_5g[] = { 66 {.center_freq = 5180, .hw_value = 36,}, 67 {.center_freq = 5200, .hw_value = 40,}, 68 {.center_freq = 5220, .hw_value = 44,}, 69 {.center_freq = 5240, .hw_value = 48,}, 70 {.center_freq = 5260, .hw_value = 52,}, 71 {.center_freq = 5280, .hw_value = 56,}, 72 {.center_freq = 5300, .hw_value = 60,}, 73 {.center_freq = 5320, .hw_value = 64,}, 74 {.center_freq = 5500, .hw_value = 100,}, 75 {.center_freq = 5520, .hw_value = 104,}, 76 {.center_freq = 5540, .hw_value = 108,}, 77 {.center_freq = 5560, .hw_value = 112,}, 78 {.center_freq = 5580, .hw_value = 116,}, 79 {.center_freq = 5600, .hw_value = 120,}, 80 {.center_freq = 5620, .hw_value = 124,}, 81 {.center_freq = 5640, .hw_value = 128,}, 82 {.center_freq = 5660, .hw_value = 132,}, 83 {.center_freq = 5680, .hw_value = 136,}, 84 {.center_freq = 5700, .hw_value = 140,}, 85 {.center_freq = 5720, .hw_value = 144,}, 86 {.center_freq = 5745, .hw_value = 149,}, 87 {.center_freq = 5765, .hw_value = 153,}, 88 {.center_freq = 5785, .hw_value = 157,}, 89 {.center_freq = 5805, .hw_value = 161,}, 90 {.center_freq = 5825, .hw_value = 165, 91 .flags = IEEE80211_CHAN_NO_HT40MINUS}, 92 }; 93 94 static struct ieee80211_rate rtw_ratetable[] = { 95 {.bitrate = 10, .hw_value = 0x00,}, 96 {.bitrate = 20, .hw_value = 0x01,}, 97 {.bitrate = 55, .hw_value = 0x02,}, 98 {.bitrate = 110, .hw_value = 0x03,}, 99 {.bitrate = 60, .hw_value = 0x04,}, 100 {.bitrate = 90, .hw_value = 0x05,}, 101 {.bitrate = 120, .hw_value = 0x06,}, 102 {.bitrate = 180, .hw_value = 0x07,}, 103 {.bitrate = 240, .hw_value = 0x08,}, 104 {.bitrate = 360, .hw_value = 0x09,}, 105 {.bitrate = 480, .hw_value = 0x0a,}, 106 {.bitrate = 540, .hw_value = 0x0b,}, 107 }; 108 109 u16 rtw_desc_to_bitrate(u8 desc_rate) 110 { 111 struct ieee80211_rate rate; 112 113 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n")) 114 return 0; 115 116 rate = rtw_ratetable[desc_rate]; 117 118 return rate.bitrate; 119 } 120 121 static struct ieee80211_supported_band rtw_band_2ghz = { 122 .band = NL80211_BAND_2GHZ, 123 124 .channels = rtw_channeltable_2g, 125 .n_channels = ARRAY_SIZE(rtw_channeltable_2g), 126 127 .bitrates = rtw_ratetable, 128 .n_bitrates = ARRAY_SIZE(rtw_ratetable), 129 130 .ht_cap = {0}, 131 .vht_cap = {0}, 132 }; 133 134 static struct ieee80211_supported_band rtw_band_5ghz = { 135 .band = NL80211_BAND_5GHZ, 136 137 .channels = rtw_channeltable_5g, 138 .n_channels = ARRAY_SIZE(rtw_channeltable_5g), 139 140 /* 5G has no CCK rates */ 141 .bitrates = rtw_ratetable + 4, 142 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4, 143 144 .ht_cap = {0}, 145 .vht_cap = {0}, 146 }; 147 148 struct rtw_watch_dog_iter_data { 149 struct rtw_dev *rtwdev; 150 struct rtw_vif *rtwvif; 151 }; 152 153 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif) 154 { 155 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 156 u8 fix_rate_enable = 0; 157 u8 new_csi_rate_idx; 158 159 if (rtwvif->bfee.role != RTW_BFEE_SU && 160 rtwvif->bfee.role != RTW_BFEE_MU) 161 return; 162 163 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi, 164 bf_info->cur_csi_rpt_rate, 165 fix_rate_enable, &new_csi_rate_idx); 166 167 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) 168 bf_info->cur_csi_rpt_rate = new_csi_rate_idx; 169 } 170 171 static void rtw_vif_watch_dog_iter(void *data, u8 *mac, 172 struct ieee80211_vif *vif) 173 { 174 struct rtw_watch_dog_iter_data *iter_data = data; 175 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 176 177 if (vif->type == NL80211_IFTYPE_STATION) 178 if (vif->bss_conf.assoc) 179 iter_data->rtwvif = rtwvif; 180 181 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif); 182 183 rtwvif->stats.tx_unicast = 0; 184 rtwvif->stats.rx_unicast = 0; 185 rtwvif->stats.tx_cnt = 0; 186 rtwvif->stats.rx_cnt = 0; 187 } 188 189 /* process TX/RX statistics periodically for hardware, 190 * the information helps hardware to enhance performance 191 */ 192 static void rtw_watch_dog_work(struct work_struct *work) 193 { 194 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 195 watch_dog_work.work); 196 struct rtw_traffic_stats *stats = &rtwdev->stats; 197 struct rtw_watch_dog_iter_data data = {}; 198 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 199 bool ps_active; 200 201 mutex_lock(&rtwdev->mutex); 202 203 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags)) 204 goto unlock; 205 206 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 207 RTW_WATCH_DOG_DELAY_TIME); 208 209 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100) 210 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 211 else 212 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); 213 214 rtw_coex_wl_status_check(rtwdev); 215 rtw_coex_query_bt_hid_list(rtwdev); 216 217 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags)) 218 rtw_coex_wl_status_change_notify(rtwdev, 0); 219 220 if (stats->tx_cnt > RTW_LPS_THRESHOLD || 221 stats->rx_cnt > RTW_LPS_THRESHOLD) 222 ps_active = true; 223 else 224 ps_active = false; 225 226 ewma_tp_add(&stats->tx_ewma_tp, 227 (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); 228 ewma_tp_add(&stats->rx_ewma_tp, 229 (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); 230 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 231 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 232 233 /* reset tx/rx statictics */ 234 stats->tx_unicast = 0; 235 stats->rx_unicast = 0; 236 stats->tx_cnt = 0; 237 stats->rx_cnt = 0; 238 239 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 240 goto unlock; 241 242 /* make sure BB/RF is working for dynamic mech */ 243 rtw_leave_lps(rtwdev); 244 245 rtw_phy_dynamic_mechanism(rtwdev); 246 247 data.rtwdev = rtwdev; 248 /* use atomic version to avoid taking local->iflist_mtx mutex */ 249 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_watch_dog_iter, &data); 250 251 /* fw supports only one station associated to enter lps, if there are 252 * more than two stations associated to the AP, then we can not enter 253 * lps, because fw does not handle the overlapped beacon interval 254 * 255 * mac80211 should iterate vifs and determine if driver can enter 256 * ps by passing IEEE80211_CONF_PS to us, all we need to do is to 257 * get that vif and check if device is having traffic more than the 258 * threshold. 259 */ 260 if (rtwdev->ps_enabled && data.rtwvif && !ps_active && 261 !rtwdev->beacon_loss) 262 rtw_enter_lps(rtwdev, data.rtwvif->port); 263 264 rtwdev->watch_dog_cnt++; 265 266 unlock: 267 mutex_unlock(&rtwdev->mutex); 268 } 269 270 static void rtw_c2h_work(struct work_struct *work) 271 { 272 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work); 273 struct sk_buff *skb, *tmp; 274 275 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) { 276 skb_unlink(skb, &rtwdev->c2h_queue); 277 rtw_fw_c2h_cmd_handle(rtwdev, skb); 278 dev_kfree_skb_any(skb); 279 } 280 } 281 282 static void rtw_ips_work(struct work_struct *work) 283 { 284 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work); 285 286 mutex_lock(&rtwdev->mutex); 287 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE) 288 rtw_enter_ips(rtwdev); 289 mutex_unlock(&rtwdev->mutex); 290 } 291 292 static u8 rtw_acquire_macid(struct rtw_dev *rtwdev) 293 { 294 unsigned long mac_id; 295 296 mac_id = find_first_zero_bit(rtwdev->mac_id_map, RTW_MAX_MAC_ID_NUM); 297 if (mac_id < RTW_MAX_MAC_ID_NUM) 298 set_bit(mac_id, rtwdev->mac_id_map); 299 300 return mac_id; 301 } 302 303 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 304 struct ieee80211_vif *vif) 305 { 306 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 307 int i; 308 309 si->mac_id = rtw_acquire_macid(rtwdev); 310 if (si->mac_id >= RTW_MAX_MAC_ID_NUM) 311 return -ENOSPC; 312 313 si->sta = sta; 314 si->vif = vif; 315 si->init_ra_lv = 1; 316 ewma_rssi_init(&si->avg_rssi); 317 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 318 rtw_txq_init(rtwdev, sta->txq[i]); 319 320 rtw_update_sta_info(rtwdev, si, true); 321 rtw_fw_media_status_report(rtwdev, si->mac_id, true); 322 323 rtwdev->sta_cnt++; 324 rtwdev->beacon_loss = false; 325 #if defined(__linux__) 326 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n", 327 sta->addr, si->mac_id); 328 #elif defined(__FreeBSD__) 329 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %6D joined with macid %d\n", 330 sta->addr, ":", si->mac_id); 331 #endif 332 333 return 0; 334 } 335 336 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 337 bool fw_exist) 338 { 339 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 340 int i; 341 342 rtw_release_macid(rtwdev, si->mac_id); 343 if (fw_exist) 344 rtw_fw_media_status_report(rtwdev, si->mac_id, false); 345 346 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 347 rtw_txq_cleanup(rtwdev, sta->txq[i]); 348 349 kfree(si->mask); 350 351 rtwdev->sta_cnt--; 352 #if defined(__linux__) 353 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n", 354 sta->addr, si->mac_id); 355 #elif defined(__FreeBSD__) 356 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %6D with macid %d left\n", 357 sta->addr, ":", si->mac_id); 358 #endif 359 } 360 361 struct rtw_fwcd_hdr { 362 u32 item; 363 u32 size; 364 u32 padding1; 365 u32 padding2; 366 } __packed; 367 368 static int rtw_fwcd_prep(struct rtw_dev *rtwdev) 369 { 370 struct rtw_chip_info *chip = rtwdev->chip; 371 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 372 const struct rtw_fwcd_segs *segs = chip->fwcd_segs; 373 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); 374 u8 i; 375 376 if (segs) { 377 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr); 378 379 for (i = 0; i < segs->num; i++) 380 prep_size += segs->segs[i]; 381 } 382 383 desc->data = vmalloc(prep_size); 384 if (!desc->data) 385 return -ENOMEM; 386 387 desc->size = prep_size; 388 desc->next = desc->data; 389 390 return 0; 391 } 392 393 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size) 394 { 395 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 396 struct rtw_fwcd_hdr *hdr; 397 u8 *next; 398 399 if (!desc->data) { 400 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n"); 401 return NULL; 402 } 403 404 next = desc->next + sizeof(struct rtw_fwcd_hdr); 405 if (next - desc->data + size > desc->size) { 406 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n"); 407 return NULL; 408 } 409 410 hdr = (struct rtw_fwcd_hdr *)(desc->next); 411 hdr->item = item; 412 hdr->size = size; 413 hdr->padding1 = 0x01234567; 414 hdr->padding2 = 0x89abcdef; 415 desc->next = next + size; 416 417 return next; 418 } 419 420 static void rtw_fwcd_dump(struct rtw_dev *rtwdev) 421 { 422 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 423 424 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n"); 425 426 /* Data will be freed after lifetime of device coredump. After calling 427 * dev_coredump, data is supposed to be handled by the device coredump 428 * framework. Note that a new dump will be discarded if a previous one 429 * hasn't been released yet. 430 */ 431 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL); 432 } 433 434 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self) 435 { 436 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc; 437 438 if (free_self) { 439 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n"); 440 vfree(desc->data); 441 } 442 443 desc->data = NULL; 444 desc->next = NULL; 445 } 446 447 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev) 448 { 449 u32 size = rtwdev->chip->fw_rxff_size; 450 u32 *buf; 451 u8 seq; 452 453 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size); 454 if (!buf) 455 return -ENOMEM; 456 457 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) { 458 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n"); 459 return -EINVAL; 460 } 461 462 if (GET_FW_DUMP_LEN(buf) == 0) { 463 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n"); 464 return -EINVAL; 465 } 466 467 seq = GET_FW_DUMP_SEQ(buf); 468 if (seq > 0) { 469 rtw_dbg(rtwdev, RTW_DBG_FW, 470 "fw crash dump's seq is wrong: %d\n", seq); 471 return -EINVAL; 472 } 473 474 return 0; 475 } 476 477 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 478 u32 fwcd_item) 479 { 480 u32 rxff = rtwdev->chip->fw_rxff_size; 481 u32 dump_size, done_size = 0; 482 u8 *buf; 483 int ret; 484 485 buf = rtw_fwcd_next(rtwdev, fwcd_item, size); 486 if (!buf) 487 return -ENOMEM; 488 489 while (size) { 490 dump_size = size > rxff ? rxff : size; 491 492 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size, 493 dump_size); 494 if (ret) { 495 rtw_err(rtwdev, 496 "ddma fw 0x%x [+0x%x] to fw fifo fail\n", 497 ocp_src, done_size); 498 return ret; 499 } 500 501 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, 502 dump_size, (u32 *)(buf + done_size)); 503 if (ret) { 504 rtw_err(rtwdev, 505 "dump fw 0x%x [+0x%x] from fw fifo fail\n", 506 ocp_src, done_size); 507 return ret; 508 } 509 510 size -= dump_size; 511 done_size += dump_size; 512 } 513 514 return 0; 515 } 516 EXPORT_SYMBOL(rtw_dump_fw); 517 518 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size) 519 { 520 u8 *buf; 521 u32 i; 522 523 if (addr & 0x3) { 524 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr); 525 return -EINVAL; 526 } 527 528 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size); 529 if (!buf) 530 return -ENOMEM; 531 532 for (i = 0; i < size; i += 4) 533 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i); 534 535 return 0; 536 } 537 EXPORT_SYMBOL(rtw_dump_reg); 538 539 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 540 struct ieee80211_bss_conf *conf) 541 { 542 if (conf && conf->assoc) { 543 rtwvif->aid = conf->aid; 544 rtwvif->net_type = RTW_NET_MGD_LINKED; 545 } else { 546 rtwvif->aid = 0; 547 rtwvif->net_type = RTW_NET_NO_LINK; 548 } 549 } 550 551 static void rtw_reset_key_iter(struct ieee80211_hw *hw, 552 struct ieee80211_vif *vif, 553 struct ieee80211_sta *sta, 554 struct ieee80211_key_conf *key, 555 void *data) 556 { 557 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 558 struct rtw_sec_desc *sec = &rtwdev->sec; 559 560 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx); 561 } 562 563 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta) 564 { 565 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 566 567 if (rtwdev->sta_cnt == 0) { 568 rtw_warn(rtwdev, "sta count before reset should not be 0\n"); 569 return; 570 } 571 rtw_sta_remove(rtwdev, sta, false); 572 } 573 574 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 575 { 576 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 577 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 578 579 rtw_bf_disassoc(rtwdev, vif, NULL); 580 rtw_vif_assoc_changed(rtwvif, NULL); 581 rtw_txq_cleanup(rtwdev, vif->txq); 582 } 583 584 void rtw_fw_recovery(struct rtw_dev *rtwdev) 585 { 586 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags)) 587 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work); 588 } 589 590 static void __fw_recovery_work(struct rtw_dev *rtwdev) 591 { 592 int ret = 0; 593 594 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags); 595 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags); 596 597 ret = rtw_fwcd_prep(rtwdev); 598 if (ret) 599 goto free; 600 ret = rtw_fw_dump_crash_log(rtwdev); 601 if (ret) 602 goto free; 603 ret = rtw_chip_dump_fw_crash(rtwdev); 604 if (ret) 605 goto free; 606 607 rtw_fwcd_dump(rtwdev); 608 free: 609 rtw_fwcd_free(rtwdev, !!ret); 610 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0); 611 612 WARN(1, "firmware crash, start reset and recover\n"); 613 614 rcu_read_lock(); 615 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev); 616 rcu_read_unlock(); 617 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev); 618 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev); 619 rtw_enter_ips(rtwdev); 620 } 621 622 static void rtw_fw_recovery_work(struct work_struct *work) 623 { 624 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, 625 fw_recovery_work); 626 627 mutex_lock(&rtwdev->mutex); 628 __fw_recovery_work(rtwdev); 629 mutex_unlock(&rtwdev->mutex); 630 631 ieee80211_restart_hw(rtwdev->hw); 632 } 633 634 struct rtw_txq_ba_iter_data { 635 }; 636 637 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta) 638 { 639 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 640 int ret; 641 u8 tid; 642 643 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 644 while (tid != IEEE80211_NUM_TIDS) { 645 clear_bit(tid, si->tid_ba); 646 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 647 if (ret == -EINVAL) { 648 struct ieee80211_txq *txq; 649 struct rtw_txq *rtwtxq; 650 651 txq = sta->txq[tid]; 652 rtwtxq = (struct rtw_txq *)txq->drv_priv; 653 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags); 654 } 655 656 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS); 657 } 658 } 659 660 static void rtw_txq_ba_work(struct work_struct *work) 661 { 662 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work); 663 struct rtw_txq_ba_iter_data data; 664 665 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data); 666 } 667 668 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel) 669 { 670 if (IS_CH_2G_BAND(channel)) 671 pkt_stat->band = NL80211_BAND_2GHZ; 672 else if (IS_CH_5G_BAND(channel)) 673 pkt_stat->band = NL80211_BAND_5GHZ; 674 else 675 return; 676 677 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band); 678 } 679 EXPORT_SYMBOL(rtw_set_rx_freq_band); 680 681 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period) 682 { 683 rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE); 684 rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1); 685 } 686 687 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 688 struct rtw_channel_params *chan_params) 689 { 690 struct ieee80211_channel *channel = chandef->chan; 691 enum nl80211_chan_width width = chandef->width; 692 u8 *cch_by_bw = chan_params->cch_by_bw; 693 u32 primary_freq, center_freq; 694 u8 center_chan; 695 u8 bandwidth = RTW_CHANNEL_WIDTH_20; 696 u8 primary_chan_idx = 0; 697 u8 i; 698 699 center_chan = channel->hw_value; 700 primary_freq = channel->center_freq; 701 center_freq = chandef->center_freq1; 702 703 /* assign the center channel used while 20M bw is selected */ 704 cch_by_bw[RTW_CHANNEL_WIDTH_20] = channel->hw_value; 705 706 switch (width) { 707 case NL80211_CHAN_WIDTH_20_NOHT: 708 case NL80211_CHAN_WIDTH_20: 709 bandwidth = RTW_CHANNEL_WIDTH_20; 710 primary_chan_idx = RTW_SC_DONT_CARE; 711 break; 712 case NL80211_CHAN_WIDTH_40: 713 bandwidth = RTW_CHANNEL_WIDTH_40; 714 if (primary_freq > center_freq) { 715 primary_chan_idx = RTW_SC_20_UPPER; 716 center_chan -= 2; 717 } else { 718 primary_chan_idx = RTW_SC_20_LOWER; 719 center_chan += 2; 720 } 721 break; 722 case NL80211_CHAN_WIDTH_80: 723 bandwidth = RTW_CHANNEL_WIDTH_80; 724 if (primary_freq > center_freq) { 725 if (primary_freq - center_freq == 10) { 726 primary_chan_idx = RTW_SC_20_UPPER; 727 center_chan -= 2; 728 } else { 729 primary_chan_idx = RTW_SC_20_UPMOST; 730 center_chan -= 6; 731 } 732 /* assign the center channel used 733 * while 40M bw is selected 734 */ 735 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan + 4; 736 } else { 737 if (center_freq - primary_freq == 10) { 738 primary_chan_idx = RTW_SC_20_LOWER; 739 center_chan += 2; 740 } else { 741 primary_chan_idx = RTW_SC_20_LOWEST; 742 center_chan += 6; 743 } 744 /* assign the center channel used 745 * while 40M bw is selected 746 */ 747 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_chan - 4; 748 } 749 break; 750 default: 751 center_chan = 0; 752 break; 753 } 754 755 chan_params->center_chan = center_chan; 756 chan_params->bandwidth = bandwidth; 757 chan_params->primary_chan_idx = primary_chan_idx; 758 759 /* assign the center channel used while current bw is selected */ 760 cch_by_bw[bandwidth] = center_chan; 761 762 for (i = bandwidth + 1; i <= RTW_MAX_CHANNEL_WIDTH; i++) 763 cch_by_bw[i] = 0; 764 } 765 766 void rtw_set_channel(struct rtw_dev *rtwdev) 767 { 768 struct ieee80211_hw *hw = rtwdev->hw; 769 struct rtw_hal *hal = &rtwdev->hal; 770 struct rtw_chip_info *chip = rtwdev->chip; 771 struct rtw_channel_params ch_param; 772 u8 center_chan, bandwidth, primary_chan_idx; 773 u8 i; 774 775 rtw_get_channel_params(&hw->conf.chandef, &ch_param); 776 if (WARN(ch_param.center_chan == 0, "Invalid channel\n")) 777 return; 778 779 center_chan = ch_param.center_chan; 780 bandwidth = ch_param.bandwidth; 781 primary_chan_idx = ch_param.primary_chan_idx; 782 783 hal->current_band_width = bandwidth; 784 hal->current_channel = center_chan; 785 hal->current_primary_channel_index = primary_chan_idx; 786 hal->current_band_type = center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G; 787 788 switch (center_chan) { 789 case 1 ... 14: 790 hal->sar_band = RTW_SAR_BAND_0; 791 break; 792 case 36 ... 64: 793 hal->sar_band = RTW_SAR_BAND_1; 794 break; 795 case 100 ... 144: 796 hal->sar_band = RTW_SAR_BAND_3; 797 break; 798 case 149 ... 177: 799 hal->sar_band = RTW_SAR_BAND_4; 800 break; 801 default: 802 WARN(1, "unknown ch(%u) to SAR band\n", center_chan); 803 hal->sar_band = RTW_SAR_BAND_0; 804 break; 805 } 806 807 for (i = RTW_CHANNEL_WIDTH_20; i <= RTW_MAX_CHANNEL_WIDTH; i++) 808 hal->cch_by_bw[i] = ch_param.cch_by_bw[i]; 809 810 chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx); 811 812 if (hal->current_band_type == RTW_BAND_5G) { 813 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G); 814 } else { 815 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 816 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G); 817 else 818 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN); 819 } 820 821 rtw_phy_set_tx_power_level(rtwdev, center_chan); 822 823 /* if the channel isn't set for scanning, we will do RF calibration 824 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration 825 * during scanning on each channel takes too long. 826 */ 827 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 828 rtwdev->need_rfk = true; 829 } 830 831 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev) 832 { 833 struct rtw_chip_info *chip = rtwdev->chip; 834 835 if (rtwdev->need_rfk) { 836 rtwdev->need_rfk = false; 837 chip->ops->phy_calibration(rtwdev); 838 } 839 } 840 841 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr) 842 { 843 int i; 844 845 for (i = 0; i < ETH_ALEN; i++) 846 rtw_write8(rtwdev, start + i, addr[i]); 847 } 848 849 void rtw_vif_port_config(struct rtw_dev *rtwdev, 850 struct rtw_vif *rtwvif, 851 u32 config) 852 { 853 u32 addr, mask; 854 855 if (config & PORT_SET_MAC_ADDR) { 856 addr = rtwvif->conf->mac_addr.addr; 857 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr); 858 } 859 if (config & PORT_SET_BSSID) { 860 addr = rtwvif->conf->bssid.addr; 861 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid); 862 } 863 if (config & PORT_SET_NET_TYPE) { 864 addr = rtwvif->conf->net_type.addr; 865 mask = rtwvif->conf->net_type.mask; 866 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); 867 } 868 if (config & PORT_SET_AID) { 869 addr = rtwvif->conf->aid.addr; 870 mask = rtwvif->conf->aid.mask; 871 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); 872 } 873 if (config & PORT_SET_BCN_CTRL) { 874 addr = rtwvif->conf->bcn_ctrl.addr; 875 mask = rtwvif->conf->bcn_ctrl.mask; 876 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); 877 } 878 } 879 880 static u8 hw_bw_cap_to_bitamp(u8 bw_cap) 881 { 882 u8 bw = 0; 883 884 switch (bw_cap) { 885 case EFUSE_HW_CAP_IGNORE: 886 case EFUSE_HW_CAP_SUPP_BW80: 887 bw |= BIT(RTW_CHANNEL_WIDTH_80); 888 fallthrough; 889 case EFUSE_HW_CAP_SUPP_BW40: 890 bw |= BIT(RTW_CHANNEL_WIDTH_40); 891 fallthrough; 892 default: 893 bw |= BIT(RTW_CHANNEL_WIDTH_20); 894 break; 895 } 896 897 return bw; 898 } 899 900 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num) 901 { 902 struct rtw_hal *hal = &rtwdev->hal; 903 struct rtw_chip_info *chip = rtwdev->chip; 904 905 if (hw_ant_num == EFUSE_HW_CAP_IGNORE || 906 hw_ant_num >= hal->rf_path_num) 907 return; 908 909 switch (hw_ant_num) { 910 case 1: 911 hal->rf_type = RF_1T1R; 912 hal->rf_path_num = 1; 913 if (!chip->fix_rf_phy_num) 914 hal->rf_phy_num = hal->rf_path_num; 915 hal->antenna_tx = BB_PATH_A; 916 hal->antenna_rx = BB_PATH_A; 917 break; 918 default: 919 WARN(1, "invalid hw configuration from efuse\n"); 920 break; 921 } 922 } 923 924 static u64 get_vht_ra_mask(struct ieee80211_sta *sta) 925 { 926 u64 ra_mask = 0; 927 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 928 u8 vht_mcs_cap; 929 int i, nss; 930 931 /* 4SS, every two bits for MCS7/8/9 */ 932 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) { 933 vht_mcs_cap = mcs_map & 0x3; 934 switch (vht_mcs_cap) { 935 case 2: /* MCS9 */ 936 ra_mask |= 0x3ffULL << nss; 937 break; 938 case 1: /* MCS8 */ 939 ra_mask |= 0x1ffULL << nss; 940 break; 941 case 0: /* MCS7 */ 942 ra_mask |= 0x0ffULL << nss; 943 break; 944 default: 945 break; 946 } 947 } 948 949 return ra_mask; 950 } 951 952 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num) 953 { 954 u8 rate_id = 0; 955 956 switch (wireless_set) { 957 case WIRELESS_CCK: 958 rate_id = RTW_RATEID_B_20M; 959 break; 960 case WIRELESS_OFDM: 961 rate_id = RTW_RATEID_G; 962 break; 963 case WIRELESS_CCK | WIRELESS_OFDM: 964 rate_id = RTW_RATEID_BG; 965 break; 966 case WIRELESS_OFDM | WIRELESS_HT: 967 if (tx_num == 1) 968 rate_id = RTW_RATEID_GN_N1SS; 969 else if (tx_num == 2) 970 rate_id = RTW_RATEID_GN_N2SS; 971 else if (tx_num == 3) 972 rate_id = RTW_RATEID_ARFR5_N_3SS; 973 break; 974 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT: 975 if (bw_mode == RTW_CHANNEL_WIDTH_40) { 976 if (tx_num == 1) 977 rate_id = RTW_RATEID_BGN_40M_1SS; 978 else if (tx_num == 2) 979 rate_id = RTW_RATEID_BGN_40M_2SS; 980 else if (tx_num == 3) 981 rate_id = RTW_RATEID_ARFR5_N_3SS; 982 else if (tx_num == 4) 983 rate_id = RTW_RATEID_ARFR7_N_4SS; 984 } else { 985 if (tx_num == 1) 986 rate_id = RTW_RATEID_BGN_20M_1SS; 987 else if (tx_num == 2) 988 rate_id = RTW_RATEID_BGN_20M_2SS; 989 else if (tx_num == 3) 990 rate_id = RTW_RATEID_ARFR5_N_3SS; 991 else if (tx_num == 4) 992 rate_id = RTW_RATEID_ARFR7_N_4SS; 993 } 994 break; 995 case WIRELESS_OFDM | WIRELESS_VHT: 996 if (tx_num == 1) 997 rate_id = RTW_RATEID_ARFR1_AC_1SS; 998 else if (tx_num == 2) 999 rate_id = RTW_RATEID_ARFR0_AC_2SS; 1000 else if (tx_num == 3) 1001 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1002 else if (tx_num == 4) 1003 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1004 break; 1005 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT: 1006 if (bw_mode >= RTW_CHANNEL_WIDTH_80) { 1007 if (tx_num == 1) 1008 rate_id = RTW_RATEID_ARFR1_AC_1SS; 1009 else if (tx_num == 2) 1010 rate_id = RTW_RATEID_ARFR0_AC_2SS; 1011 else if (tx_num == 3) 1012 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1013 else if (tx_num == 4) 1014 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1015 } else { 1016 if (tx_num == 1) 1017 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS; 1018 else if (tx_num == 2) 1019 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS; 1020 else if (tx_num == 3) 1021 rate_id = RTW_RATEID_ARFR4_AC_3SS; 1022 else if (tx_num == 4) 1023 rate_id = RTW_RATEID_ARFR6_AC_4SS; 1024 } 1025 break; 1026 default: 1027 break; 1028 } 1029 1030 return rate_id; 1031 } 1032 1033 #define RA_MASK_CCK_RATES 0x0000f 1034 #define RA_MASK_OFDM_RATES 0x00ff0 1035 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0) 1036 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8) 1037 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16) 1038 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \ 1039 RA_MASK_HT_RATES_2SS | \ 1040 RA_MASK_HT_RATES_3SS) 1041 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0) 1042 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10) 1043 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20) 1044 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \ 1045 RA_MASK_VHT_RATES_2SS | \ 1046 RA_MASK_VHT_RATES_3SS) 1047 #define RA_MASK_CCK_IN_BG 0x00005 1048 #define RA_MASK_CCK_IN_HT 0x00005 1049 #define RA_MASK_CCK_IN_VHT 0x00005 1050 #define RA_MASK_OFDM_IN_VHT 0x00010 1051 #define RA_MASK_OFDM_IN_HT_2G 0x00010 1052 #define RA_MASK_OFDM_IN_HT_5G 0x00030 1053 1054 static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set) 1055 { 1056 u8 rssi_level = si->rssi_level; 1057 1058 if (wireless_set == WIRELESS_CCK) 1059 return 0xffffffffffffffffULL; 1060 1061 if (rssi_level == 0) 1062 return 0xffffffffffffffffULL; 1063 else if (rssi_level == 1) 1064 return 0xfffffffffffffff0ULL; 1065 else if (rssi_level == 2) 1066 return 0xffffffffffffefe0ULL; 1067 else if (rssi_level == 3) 1068 return 0xffffffffffffcfc0ULL; 1069 else if (rssi_level == 4) 1070 return 0xffffffffffff8f80ULL; 1071 else 1072 return 0xffffffffffff0f00ULL; 1073 } 1074 1075 static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak) 1076 { 1077 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 1078 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1079 1080 if (ra_mask == 0) 1081 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 1082 1083 return ra_mask; 1084 } 1085 1086 static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1087 u64 ra_mask, bool is_vht_enable) 1088 { 1089 struct rtw_hal *hal = &rtwdev->hal; 1090 const struct cfg80211_bitrate_mask *mask = si->mask; 1091 u64 cfg_mask = GENMASK_ULL(63, 0); 1092 u8 band; 1093 1094 if (!si->use_cfg_mask) 1095 return ra_mask; 1096 1097 band = hal->current_band_type; 1098 if (band == RTW_BAND_2G) { 1099 band = NL80211_BAND_2GHZ; 1100 cfg_mask = mask->control[band].legacy; 1101 } else if (band == RTW_BAND_5G) { 1102 band = NL80211_BAND_5GHZ; 1103 cfg_mask = u64_encode_bits(mask->control[band].legacy, 1104 RA_MASK_OFDM_RATES); 1105 } 1106 1107 if (!is_vht_enable) { 1108 if (ra_mask & RA_MASK_HT_RATES_1SS) 1109 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 1110 RA_MASK_HT_RATES_1SS); 1111 if (ra_mask & RA_MASK_HT_RATES_2SS) 1112 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 1113 RA_MASK_HT_RATES_2SS); 1114 } else { 1115 if (ra_mask & RA_MASK_VHT_RATES_1SS) 1116 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 1117 RA_MASK_VHT_RATES_1SS); 1118 if (ra_mask & RA_MASK_VHT_RATES_2SS) 1119 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 1120 RA_MASK_VHT_RATES_2SS); 1121 } 1122 1123 ra_mask &= cfg_mask; 1124 1125 return ra_mask; 1126 } 1127 1128 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si, 1129 bool reset_ra_mask) 1130 { 1131 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1132 struct ieee80211_sta *sta = si->sta; 1133 struct rtw_efuse *efuse = &rtwdev->efuse; 1134 struct rtw_hal *hal = &rtwdev->hal; 1135 u8 wireless_set; 1136 u8 bw_mode; 1137 u8 rate_id; 1138 u8 rf_type = RF_1T1R; 1139 u8 stbc_en = 0; 1140 u8 ldpc_en = 0; 1141 u8 tx_num = 1; 1142 u64 ra_mask = 0; 1143 u64 ra_mask_bak = 0; 1144 bool is_vht_enable = false; 1145 bool is_support_sgi = false; 1146 1147 if (sta->deflink.vht_cap.vht_supported) { 1148 is_vht_enable = true; 1149 ra_mask |= get_vht_ra_mask(sta); 1150 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 1151 stbc_en = VHT_STBC_EN; 1152 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 1153 ldpc_en = VHT_LDPC_EN; 1154 } else if (sta->deflink.ht_cap.ht_supported) { 1155 ra_mask |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) | 1156 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 1157 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 1158 stbc_en = HT_STBC_EN; 1159 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 1160 ldpc_en = HT_LDPC_EN; 1161 } 1162 1163 if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss) 1164 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS; 1165 1166 if (hal->current_band_type == RTW_BAND_5G) { 1167 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 1168 ra_mask_bak = ra_mask; 1169 if (sta->deflink.vht_cap.vht_supported) { 1170 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT; 1171 wireless_set = WIRELESS_OFDM | WIRELESS_VHT; 1172 } else if (sta->deflink.ht_cap.ht_supported) { 1173 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G; 1174 wireless_set = WIRELESS_OFDM | WIRELESS_HT; 1175 } else { 1176 wireless_set = WIRELESS_OFDM; 1177 } 1178 dm_info->rrsr_val_init = RRSR_INIT_5G; 1179 } else if (hal->current_band_type == RTW_BAND_2G) { 1180 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 1181 ra_mask_bak = ra_mask; 1182 if (sta->deflink.vht_cap.vht_supported) { 1183 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT | 1184 RA_MASK_OFDM_IN_VHT; 1185 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1186 WIRELESS_HT | WIRELESS_VHT; 1187 } else if (sta->deflink.ht_cap.ht_supported) { 1188 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT | 1189 RA_MASK_OFDM_IN_HT_2G; 1190 wireless_set = WIRELESS_CCK | WIRELESS_OFDM | 1191 WIRELESS_HT; 1192 #if defined(__linux__) 1193 } else if (sta->deflink.supp_rates[0] <= 0xf) { 1194 #elif defined(__FreeBSD__) 1195 } else if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] <= 0xf) { 1196 #endif 1197 wireless_set = WIRELESS_CCK; 1198 } else { 1199 ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG; 1200 wireless_set = WIRELESS_CCK | WIRELESS_OFDM; 1201 } 1202 dm_info->rrsr_val_init = RRSR_INIT_2G; 1203 } else { 1204 rtw_err(rtwdev, "Unknown band type\n"); 1205 ra_mask_bak = ra_mask; 1206 wireless_set = 0; 1207 } 1208 1209 switch (sta->deflink.bandwidth) { 1210 case IEEE80211_STA_RX_BW_80: 1211 bw_mode = RTW_CHANNEL_WIDTH_80; 1212 is_support_sgi = sta->deflink.vht_cap.vht_supported && 1213 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 1214 break; 1215 case IEEE80211_STA_RX_BW_40: 1216 bw_mode = RTW_CHANNEL_WIDTH_40; 1217 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1218 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 1219 break; 1220 default: 1221 bw_mode = RTW_CHANNEL_WIDTH_20; 1222 is_support_sgi = sta->deflink.ht_cap.ht_supported && 1223 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 1224 break; 1225 } 1226 1227 if (sta->deflink.vht_cap.vht_supported && ra_mask & 0xffc00000) { 1228 tx_num = 2; 1229 rf_type = RF_2T2R; 1230 } else if (sta->deflink.ht_cap.ht_supported && ra_mask & 0xfff00000) { 1231 tx_num = 2; 1232 rf_type = RF_2T2R; 1233 } 1234 1235 rate_id = get_rate_id(wireless_set, bw_mode, tx_num); 1236 1237 ra_mask &= rtw_rate_mask_rssi(si, wireless_set); 1238 ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak); 1239 ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable); 1240 1241 si->bw_mode = bw_mode; 1242 si->stbc_en = stbc_en; 1243 si->ldpc_en = ldpc_en; 1244 si->rf_type = rf_type; 1245 si->wireless_set = wireless_set; 1246 si->sgi_enable = is_support_sgi; 1247 si->vht_enable = is_vht_enable; 1248 si->ra_mask = ra_mask; 1249 si->rate_id = rate_id; 1250 1251 rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask); 1252 } 1253 1254 static int rtw_wait_firmware_completion(struct rtw_dev *rtwdev) 1255 { 1256 struct rtw_chip_info *chip = rtwdev->chip; 1257 struct rtw_fw_state *fw; 1258 1259 fw = &rtwdev->fw; 1260 wait_for_completion(&fw->completion); 1261 if (!fw->firmware) 1262 return -EINVAL; 1263 1264 if (chip->wow_fw_name) { 1265 fw = &rtwdev->wow_fw; 1266 wait_for_completion(&fw->completion); 1267 if (!fw->firmware) 1268 return -EINVAL; 1269 } 1270 1271 return 0; 1272 } 1273 1274 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev, 1275 struct rtw_fw_state *fw) 1276 { 1277 struct rtw_chip_info *chip = rtwdev->chip; 1278 1279 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported || 1280 !fw->feature) 1281 return LPS_DEEP_MODE_NONE; 1282 1283 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) && 1284 rtw_fw_feature_check(fw, FW_FEATURE_PG)) 1285 return LPS_DEEP_MODE_PG; 1286 1287 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) && 1288 rtw_fw_feature_check(fw, FW_FEATURE_LCLK)) 1289 return LPS_DEEP_MODE_LCLK; 1290 1291 return LPS_DEEP_MODE_NONE; 1292 } 1293 1294 static int rtw_power_on(struct rtw_dev *rtwdev) 1295 { 1296 struct rtw_chip_info *chip = rtwdev->chip; 1297 struct rtw_fw_state *fw = &rtwdev->fw; 1298 bool wifi_only; 1299 int ret; 1300 1301 ret = rtw_hci_setup(rtwdev); 1302 if (ret) { 1303 rtw_err(rtwdev, "failed to setup hci\n"); 1304 goto err; 1305 } 1306 1307 /* power on MAC before firmware downloaded */ 1308 ret = rtw_mac_power_on(rtwdev); 1309 if (ret) { 1310 rtw_err(rtwdev, "failed to power on mac\n"); 1311 goto err; 1312 } 1313 1314 ret = rtw_wait_firmware_completion(rtwdev); 1315 if (ret) { 1316 rtw_err(rtwdev, "failed to wait firmware completion\n"); 1317 goto err_off; 1318 } 1319 1320 ret = rtw_download_firmware(rtwdev, fw); 1321 if (ret) { 1322 rtw_err(rtwdev, "failed to download firmware\n"); 1323 goto err_off; 1324 } 1325 1326 /* config mac after firmware downloaded */ 1327 ret = rtw_mac_init(rtwdev); 1328 if (ret) { 1329 rtw_err(rtwdev, "failed to configure mac\n"); 1330 goto err_off; 1331 } 1332 1333 chip->ops->phy_set_param(rtwdev); 1334 1335 ret = rtw_hci_start(rtwdev); 1336 if (ret) { 1337 rtw_err(rtwdev, "failed to start hci\n"); 1338 goto err_off; 1339 } 1340 1341 /* send H2C after HCI has started */ 1342 rtw_fw_send_general_info(rtwdev); 1343 rtw_fw_send_phydm_info(rtwdev); 1344 1345 wifi_only = !rtwdev->efuse.btcoex; 1346 rtw_coex_power_on_setting(rtwdev); 1347 rtw_coex_init_hw_config(rtwdev, wifi_only); 1348 1349 return 0; 1350 1351 err_off: 1352 rtw_mac_power_off(rtwdev); 1353 1354 err: 1355 return ret; 1356 } 1357 1358 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start) 1359 { 1360 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN)) 1361 return; 1362 1363 if (start) { 1364 rtw_fw_scan_notify(rtwdev, true); 1365 } else { 1366 reinit_completion(&rtwdev->fw_scan_density); 1367 rtw_fw_scan_notify(rtwdev, false); 1368 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density, 1369 SCAN_NOTIFY_TIMEOUT)) 1370 rtw_warn(rtwdev, "firmware failed to report density after scan\n"); 1371 } 1372 } 1373 1374 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 1375 const u8 *mac_addr, bool hw_scan) 1376 { 1377 u32 config = 0; 1378 int ret = 0; 1379 1380 rtw_leave_lps(rtwdev); 1381 1382 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) { 1383 ret = rtw_leave_ips(rtwdev); 1384 if (ret) { 1385 rtw_err(rtwdev, "failed to leave idle state\n"); 1386 return; 1387 } 1388 } 1389 1390 ether_addr_copy(rtwvif->mac_addr, mac_addr); 1391 config |= PORT_SET_MAC_ADDR; 1392 rtw_vif_port_config(rtwdev, rtwvif, config); 1393 1394 rtw_coex_scan_notify(rtwdev, COEX_SCAN_START); 1395 rtw_core_fw_scan_notify(rtwdev, true); 1396 1397 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1398 set_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1399 } 1400 1401 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 1402 bool hw_scan) 1403 { 1404 struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL; 1405 u32 config = 0; 1406 1407 if (!rtwvif) 1408 return; 1409 1410 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags); 1411 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags); 1412 1413 rtw_core_fw_scan_notify(rtwdev, false); 1414 1415 ether_addr_copy(rtwvif->mac_addr, vif->addr); 1416 config |= PORT_SET_MAC_ADDR; 1417 rtw_vif_port_config(rtwdev, rtwvif, config); 1418 1419 rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH); 1420 1421 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 1422 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 1423 } 1424 1425 int rtw_core_start(struct rtw_dev *rtwdev) 1426 { 1427 int ret; 1428 1429 ret = rtw_power_on(rtwdev); 1430 if (ret) 1431 return ret; 1432 1433 rtw_sec_enable_sec_engine(rtwdev); 1434 1435 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw); 1436 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw); 1437 1438 /* rcr reset after powered on */ 1439 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr); 1440 1441 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work, 1442 RTW_WATCH_DOG_DELAY_TIME); 1443 1444 set_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1445 1446 return 0; 1447 } 1448 1449 static void rtw_power_off(struct rtw_dev *rtwdev) 1450 { 1451 rtw_hci_stop(rtwdev); 1452 rtw_coex_power_off_setting(rtwdev); 1453 rtw_mac_power_off(rtwdev); 1454 } 1455 1456 void rtw_core_stop(struct rtw_dev *rtwdev) 1457 { 1458 struct rtw_coex *coex = &rtwdev->coex; 1459 1460 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags); 1461 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags); 1462 1463 mutex_unlock(&rtwdev->mutex); 1464 1465 cancel_work_sync(&rtwdev->c2h_work); 1466 cancel_work_sync(&rtwdev->update_beacon_work); 1467 cancel_delayed_work_sync(&rtwdev->watch_dog_work); 1468 cancel_delayed_work_sync(&coex->bt_relink_work); 1469 cancel_delayed_work_sync(&coex->bt_reenable_work); 1470 cancel_delayed_work_sync(&coex->defreeze_work); 1471 cancel_delayed_work_sync(&coex->wl_remain_work); 1472 cancel_delayed_work_sync(&coex->bt_remain_work); 1473 cancel_delayed_work_sync(&coex->wl_connecting_work); 1474 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work); 1475 cancel_delayed_work_sync(&coex->wl_ccklock_work); 1476 1477 mutex_lock(&rtwdev->mutex); 1478 1479 rtw_power_off(rtwdev); 1480 } 1481 1482 static void rtw_init_ht_cap(struct rtw_dev *rtwdev, 1483 struct ieee80211_sta_ht_cap *ht_cap) 1484 { 1485 struct rtw_efuse *efuse = &rtwdev->efuse; 1486 struct rtw_chip_info *chip = rtwdev->chip; 1487 1488 ht_cap->ht_supported = true; 1489 ht_cap->cap = 0; 1490 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 1491 IEEE80211_HT_CAP_MAX_AMSDU | 1492 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 1493 1494 if (rtw_chip_has_rx_ldpc(rtwdev)) 1495 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 1496 if (rtw_chip_has_tx_stbc(rtwdev)) 1497 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; 1498 1499 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) 1500 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 1501 IEEE80211_HT_CAP_DSSSCCK40 | 1502 IEEE80211_HT_CAP_SGI_40; 1503 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 1504 ht_cap->ampdu_density = chip->ampdu_density; 1505 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 1506 if (efuse->hw_cap.nss > 1) { 1507 ht_cap->mcs.rx_mask[0] = 0xFF; 1508 ht_cap->mcs.rx_mask[1] = 0xFF; 1509 ht_cap->mcs.rx_mask[4] = 0x01; 1510 ht_cap->mcs.rx_highest = cpu_to_le16(300); 1511 } else { 1512 ht_cap->mcs.rx_mask[0] = 0xFF; 1513 ht_cap->mcs.rx_mask[1] = 0x00; 1514 ht_cap->mcs.rx_mask[4] = 0x01; 1515 ht_cap->mcs.rx_highest = cpu_to_le16(150); 1516 } 1517 } 1518 1519 static void rtw_init_vht_cap(struct rtw_dev *rtwdev, 1520 struct ieee80211_sta_vht_cap *vht_cap) 1521 { 1522 struct rtw_efuse *efuse = &rtwdev->efuse; 1523 u16 mcs_map; 1524 __le16 highest; 1525 1526 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && 1527 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT) 1528 return; 1529 1530 vht_cap->vht_supported = true; 1531 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 1532 IEEE80211_VHT_CAP_SHORT_GI_80 | 1533 IEEE80211_VHT_CAP_RXSTBC_1 | 1534 IEEE80211_VHT_CAP_HTC_VHT | 1535 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 1536 0; 1537 if (rtwdev->hal.rf_path_num > 1) 1538 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 1539 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 1540 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 1541 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap << 1542 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT); 1543 1544 if (rtw_chip_has_rx_ldpc(rtwdev)) 1545 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 1546 1547 mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | 1548 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 | 1549 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 | 1550 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 | 1551 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 | 1552 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 | 1553 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14; 1554 if (efuse->hw_cap.nss > 1) { 1555 highest = cpu_to_le16(780); 1556 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << 2; 1557 } else { 1558 highest = cpu_to_le16(390); 1559 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << 2; 1560 } 1561 1562 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map); 1563 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); 1564 vht_cap->vht_mcs.rx_highest = highest; 1565 vht_cap->vht_mcs.tx_highest = highest; 1566 } 1567 1568 static void rtw_set_supported_band(struct ieee80211_hw *hw, 1569 struct rtw_chip_info *chip) 1570 { 1571 struct rtw_dev *rtwdev = hw->priv; 1572 struct ieee80211_supported_band *sband; 1573 1574 if (chip->band & RTW_BAND_2G) { 1575 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL); 1576 if (!sband) 1577 goto err_out; 1578 if (chip->ht_supported) 1579 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1580 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 1581 } 1582 1583 if (chip->band & RTW_BAND_5G) { 1584 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL); 1585 if (!sband) 1586 goto err_out; 1587 if (chip->ht_supported) 1588 rtw_init_ht_cap(rtwdev, &sband->ht_cap); 1589 if (chip->vht_supported) 1590 rtw_init_vht_cap(rtwdev, &sband->vht_cap); 1591 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 1592 } 1593 1594 return; 1595 1596 err_out: 1597 rtw_err(rtwdev, "failed to set supported band\n"); 1598 } 1599 1600 static void rtw_unset_supported_band(struct ieee80211_hw *hw, 1601 struct rtw_chip_info *chip) 1602 { 1603 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 1604 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 1605 } 1606 1607 static void rtw_vif_smps_iter(void *data, u8 *mac, 1608 struct ieee80211_vif *vif) 1609 { 1610 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 1611 1612 if (vif->type != NL80211_IFTYPE_STATION || !vif->bss_conf.assoc) 1613 return; 1614 1615 if (rtwdev->hal.txrx_1ss) 1616 ieee80211_request_smps(vif, IEEE80211_SMPS_STATIC); 1617 else 1618 ieee80211_request_smps(vif, IEEE80211_SMPS_OFF); 1619 } 1620 1621 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss) 1622 { 1623 struct rtw_chip_info *chip = rtwdev->chip; 1624 struct rtw_hal *hal = &rtwdev->hal; 1625 1626 if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss) 1627 return; 1628 1629 rtwdev->hal.txrx_1ss = txrx_1ss; 1630 if (txrx_1ss) 1631 chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false); 1632 else 1633 chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx, 1634 hal->antenna_rx, false); 1635 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev); 1636 } 1637 1638 static void __update_firmware_feature(struct rtw_dev *rtwdev, 1639 struct rtw_fw_state *fw) 1640 { 1641 u32 feature; 1642 const struct rtw_fw_hdr *fw_hdr = 1643 (const struct rtw_fw_hdr *)fw->firmware->data; 1644 1645 feature = le32_to_cpu(fw_hdr->feature); 1646 fw->feature = feature & FW_FEATURE_SIG ? feature : 0; 1647 } 1648 1649 static void __update_firmware_info(struct rtw_dev *rtwdev, 1650 struct rtw_fw_state *fw) 1651 { 1652 const struct rtw_fw_hdr *fw_hdr = 1653 (const struct rtw_fw_hdr *)fw->firmware->data; 1654 1655 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver); 1656 fw->version = le16_to_cpu(fw_hdr->version); 1657 fw->sub_version = fw_hdr->subversion; 1658 fw->sub_index = fw_hdr->subindex; 1659 1660 __update_firmware_feature(rtwdev, fw); 1661 } 1662 1663 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev, 1664 struct rtw_fw_state *fw) 1665 { 1666 struct rtw_fw_hdr_legacy *legacy = 1667 #if defined(__linux__) 1668 (struct rtw_fw_hdr_legacy *)fw->firmware->data; 1669 #elif defined(__FreeBSD__) 1670 __DECONST(struct rtw_fw_hdr_legacy *, fw->firmware->data); 1671 #endif 1672 1673 fw->h2c_version = 0; 1674 fw->version = le16_to_cpu(legacy->version); 1675 fw->sub_version = legacy->subversion1; 1676 fw->sub_index = legacy->subversion2; 1677 } 1678 1679 static void update_firmware_info(struct rtw_dev *rtwdev, 1680 struct rtw_fw_state *fw) 1681 { 1682 if (rtw_chip_wcpu_11n(rtwdev)) 1683 __update_firmware_info_legacy(rtwdev, fw); 1684 else 1685 __update_firmware_info(rtwdev, fw); 1686 } 1687 1688 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context) 1689 { 1690 struct rtw_fw_state *fw = context; 1691 struct rtw_dev *rtwdev = fw->rtwdev; 1692 1693 if (!firmware || !firmware->data) { 1694 rtw_err(rtwdev, "failed to request firmware\n"); 1695 complete_all(&fw->completion); 1696 return; 1697 } 1698 1699 fw->firmware = firmware; 1700 update_firmware_info(rtwdev, fw); 1701 complete_all(&fw->completion); 1702 1703 rtw_info(rtwdev, "Firmware version %u.%u.%u, H2C version %u\n", 1704 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version); 1705 } 1706 1707 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type) 1708 { 1709 const char *fw_name; 1710 struct rtw_fw_state *fw; 1711 int ret; 1712 1713 switch (type) { 1714 case RTW_WOWLAN_FW: 1715 fw = &rtwdev->wow_fw; 1716 fw_name = rtwdev->chip->wow_fw_name; 1717 break; 1718 1719 case RTW_NORMAL_FW: 1720 fw = &rtwdev->fw; 1721 fw_name = rtwdev->chip->fw_name; 1722 break; 1723 1724 default: 1725 rtw_warn(rtwdev, "unsupported firmware type\n"); 1726 return -ENOENT; 1727 } 1728 1729 fw->rtwdev = rtwdev; 1730 init_completion(&fw->completion); 1731 1732 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev, 1733 GFP_KERNEL, fw, rtw_load_firmware_cb); 1734 if (ret) { 1735 rtw_err(rtwdev, "failed to async firmware request\n"); 1736 return ret; 1737 } 1738 1739 return 0; 1740 } 1741 1742 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev) 1743 { 1744 struct rtw_chip_info *chip = rtwdev->chip; 1745 struct rtw_hal *hal = &rtwdev->hal; 1746 struct rtw_efuse *efuse = &rtwdev->efuse; 1747 1748 switch (rtw_hci_type(rtwdev)) { 1749 case RTW_HCI_TYPE_PCIE: 1750 rtwdev->hci.rpwm_addr = 0x03d9; 1751 rtwdev->hci.cpwm_addr = 0x03da; 1752 break; 1753 default: 1754 rtw_err(rtwdev, "unsupported hci type\n"); 1755 return -EINVAL; 1756 } 1757 1758 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1); 1759 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version); 1760 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1; 1761 if (hal->chip_version & BIT_RF_TYPE_ID) { 1762 hal->rf_type = RF_2T2R; 1763 hal->rf_path_num = 2; 1764 hal->antenna_tx = BB_PATH_AB; 1765 hal->antenna_rx = BB_PATH_AB; 1766 } else { 1767 hal->rf_type = RF_1T1R; 1768 hal->rf_path_num = 1; 1769 hal->antenna_tx = BB_PATH_A; 1770 hal->antenna_rx = BB_PATH_A; 1771 } 1772 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num : 1773 hal->rf_path_num; 1774 1775 efuse->physical_size = chip->phy_efuse_size; 1776 efuse->logical_size = chip->log_efuse_size; 1777 efuse->protect_size = chip->ptct_efuse_size; 1778 1779 /* default use ack */ 1780 rtwdev->hal.rcr |= BIT_VHT_DACK; 1781 1782 hal->bfee_sts_cap = 3; 1783 1784 return 0; 1785 } 1786 1787 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev) 1788 { 1789 struct rtw_fw_state *fw = &rtwdev->fw; 1790 int ret; 1791 1792 ret = rtw_hci_setup(rtwdev); 1793 if (ret) { 1794 rtw_err(rtwdev, "failed to setup hci\n"); 1795 goto err; 1796 } 1797 1798 ret = rtw_mac_power_on(rtwdev); 1799 if (ret) { 1800 rtw_err(rtwdev, "failed to power on mac\n"); 1801 goto err; 1802 } 1803 1804 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP); 1805 1806 wait_for_completion(&fw->completion); 1807 if (!fw->firmware) { 1808 ret = -EINVAL; 1809 rtw_err(rtwdev, "failed to load firmware\n"); 1810 goto err; 1811 } 1812 1813 ret = rtw_download_firmware(rtwdev, fw); 1814 if (ret) { 1815 rtw_err(rtwdev, "failed to download firmware\n"); 1816 goto err_off; 1817 } 1818 1819 return 0; 1820 1821 err_off: 1822 rtw_mac_power_off(rtwdev); 1823 1824 err: 1825 return ret; 1826 } 1827 1828 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev) 1829 { 1830 struct rtw_efuse *efuse = &rtwdev->efuse; 1831 u8 hw_feature[HW_FEATURE_LEN]; 1832 u8 id; 1833 u8 bw; 1834 int i; 1835 1836 id = rtw_read8(rtwdev, REG_C2HEVT); 1837 if (id != C2H_HW_FEATURE_REPORT) { 1838 rtw_err(rtwdev, "failed to read hw feature report\n"); 1839 return -EBUSY; 1840 } 1841 1842 for (i = 0; i < HW_FEATURE_LEN; i++) 1843 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i); 1844 1845 rtw_write8(rtwdev, REG_C2HEVT, 0); 1846 1847 bw = GET_EFUSE_HW_CAP_BW(hw_feature); 1848 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw); 1849 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature); 1850 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature); 1851 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature); 1852 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature); 1853 1854 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num); 1855 1856 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE || 1857 efuse->hw_cap.nss > rtwdev->hal.rf_path_num) 1858 efuse->hw_cap.nss = rtwdev->hal.rf_path_num; 1859 1860 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 1861 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 1862 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 1863 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 1864 1865 return 0; 1866 } 1867 1868 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev) 1869 { 1870 rtw_hci_stop(rtwdev); 1871 rtw_mac_power_off(rtwdev); 1872 } 1873 1874 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev) 1875 { 1876 struct rtw_efuse *efuse = &rtwdev->efuse; 1877 int ret; 1878 1879 mutex_lock(&rtwdev->mutex); 1880 1881 /* power on mac to read efuse */ 1882 ret = rtw_chip_efuse_enable(rtwdev); 1883 if (ret) 1884 goto out_unlock; 1885 1886 ret = rtw_parse_efuse_map(rtwdev); 1887 if (ret) 1888 goto out_disable; 1889 1890 ret = rtw_dump_hw_feature(rtwdev); 1891 if (ret) 1892 goto out_disable; 1893 1894 ret = rtw_check_supported_rfe(rtwdev); 1895 if (ret) 1896 goto out_disable; 1897 1898 if (efuse->crystal_cap == 0xff) 1899 efuse->crystal_cap = 0; 1900 if (efuse->pa_type_2g == 0xff) 1901 efuse->pa_type_2g = 0; 1902 if (efuse->pa_type_5g == 0xff) 1903 efuse->pa_type_5g = 0; 1904 if (efuse->lna_type_2g == 0xff) 1905 efuse->lna_type_2g = 0; 1906 if (efuse->lna_type_5g == 0xff) 1907 efuse->lna_type_5g = 0; 1908 if (efuse->channel_plan == 0xff) 1909 efuse->channel_plan = 0x7f; 1910 if (efuse->rf_board_option == 0xff) 1911 efuse->rf_board_option = 0; 1912 if (efuse->bt_setting & BIT(0)) 1913 efuse->share_ant = true; 1914 if (efuse->regd == 0xff) 1915 efuse->regd = 0; 1916 if (efuse->tx_bb_swing_setting_2g == 0xff) 1917 efuse->tx_bb_swing_setting_2g = 0; 1918 if (efuse->tx_bb_swing_setting_5g == 0xff) 1919 efuse->tx_bb_swing_setting_5g = 0; 1920 1921 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20; 1922 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0; 1923 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0; 1924 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0; 1925 efuse->ext_lna_2g = efuse->lna_type_5g & BIT(3) ? 1 : 0; 1926 1927 out_disable: 1928 rtw_chip_efuse_disable(rtwdev); 1929 1930 out_unlock: 1931 mutex_unlock(&rtwdev->mutex); 1932 return ret; 1933 } 1934 1935 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev) 1936 { 1937 struct rtw_hal *hal = &rtwdev->hal; 1938 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 1939 1940 if (!rfe_def) 1941 return -ENODEV; 1942 1943 rtw_phy_setup_phy_cond(rtwdev, 0); 1944 1945 rtw_phy_init_tx_power(rtwdev); 1946 if (rfe_def->agc_btg_tbl) 1947 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); 1948 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl); 1949 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl); 1950 rtw_phy_tx_power_by_rate_config(hal); 1951 rtw_phy_tx_power_limit_config(hal); 1952 1953 return 0; 1954 } 1955 1956 int rtw_chip_info_setup(struct rtw_dev *rtwdev) 1957 { 1958 int ret; 1959 1960 ret = rtw_chip_parameter_setup(rtwdev); 1961 if (ret) { 1962 rtw_err(rtwdev, "failed to setup chip parameters\n"); 1963 goto err_out; 1964 } 1965 1966 ret = rtw_chip_efuse_info_setup(rtwdev); 1967 if (ret) { 1968 rtw_err(rtwdev, "failed to setup chip efuse info\n"); 1969 goto err_out; 1970 } 1971 1972 ret = rtw_chip_board_info_setup(rtwdev); 1973 if (ret) { 1974 rtw_err(rtwdev, "failed to setup chip board info\n"); 1975 goto err_out; 1976 } 1977 1978 return 0; 1979 1980 err_out: 1981 return ret; 1982 } 1983 EXPORT_SYMBOL(rtw_chip_info_setup); 1984 1985 static void rtw_stats_init(struct rtw_dev *rtwdev) 1986 { 1987 struct rtw_traffic_stats *stats = &rtwdev->stats; 1988 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1989 int i; 1990 1991 ewma_tp_init(&stats->tx_ewma_tp); 1992 ewma_tp_init(&stats->rx_ewma_tp); 1993 1994 for (i = 0; i < RTW_EVM_NUM; i++) 1995 ewma_evm_init(&dm_info->ewma_evm[i]); 1996 for (i = 0; i < RTW_SNR_NUM; i++) 1997 ewma_snr_init(&dm_info->ewma_snr[i]); 1998 } 1999 2000 int rtw_core_init(struct rtw_dev *rtwdev) 2001 { 2002 struct rtw_chip_info *chip = rtwdev->chip; 2003 struct rtw_coex *coex = &rtwdev->coex; 2004 int ret; 2005 2006 INIT_LIST_HEAD(&rtwdev->rsvd_page_list); 2007 INIT_LIST_HEAD(&rtwdev->txqs); 2008 2009 timer_setup(&rtwdev->tx_report.purge_timer, 2010 rtw_tx_report_purge_timer, 0); 2011 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 2012 2013 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work); 2014 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work); 2015 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work); 2016 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work); 2017 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work); 2018 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work); 2019 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work); 2020 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work, 2021 rtw_coex_bt_multi_link_remain_work); 2022 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work); 2023 INIT_WORK(&rtwdev->tx_work, rtw_tx_work); 2024 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work); 2025 INIT_WORK(&rtwdev->ips_work, rtw_ips_work); 2026 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work); 2027 INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work); 2028 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work); 2029 skb_queue_head_init(&rtwdev->c2h_queue); 2030 skb_queue_head_init(&rtwdev->coex.queue); 2031 skb_queue_head_init(&rtwdev->tx_report.queue); 2032 2033 spin_lock_init(&rtwdev->rf_lock); 2034 spin_lock_init(&rtwdev->h2c.lock); 2035 spin_lock_init(&rtwdev->txq_lock); 2036 spin_lock_init(&rtwdev->tx_report.q_lock); 2037 2038 mutex_init(&rtwdev->mutex); 2039 mutex_init(&rtwdev->coex.mutex); 2040 mutex_init(&rtwdev->hal.tx_power_mutex); 2041 2042 init_waitqueue_head(&rtwdev->coex.wait); 2043 init_completion(&rtwdev->lps_leave_check); 2044 init_completion(&rtwdev->fw_scan_density); 2045 2046 rtwdev->sec.total_cam_num = 32; 2047 rtwdev->hal.current_channel = 1; 2048 rtwdev->dm_info.fix_rate = U8_MAX; 2049 set_bit(RTW_BC_MC_MACID, rtwdev->mac_id_map); 2050 2051 rtw_stats_init(rtwdev); 2052 2053 /* default rx filter setting */ 2054 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV | 2055 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS | 2056 BIT_AB | BIT_AM | BIT_APM; 2057 2058 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW); 2059 if (ret) { 2060 rtw_warn(rtwdev, "no firmware loaded\n"); 2061 return ret; 2062 } 2063 2064 if (chip->wow_fw_name) { 2065 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW); 2066 if (ret) { 2067 rtw_warn(rtwdev, "no wow firmware loaded\n"); 2068 wait_for_completion(&rtwdev->fw.completion); 2069 if (rtwdev->fw.firmware) 2070 release_firmware(rtwdev->fw.firmware); 2071 return ret; 2072 } 2073 } 2074 2075 #if defined(__FreeBSD__) 2076 rtw_wait_firmware_completion(rtwdev); 2077 #endif 2078 2079 return 0; 2080 } 2081 EXPORT_SYMBOL(rtw_core_init); 2082 2083 void rtw_core_deinit(struct rtw_dev *rtwdev) 2084 { 2085 struct rtw_fw_state *fw = &rtwdev->fw; 2086 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw; 2087 struct rtw_rsvd_page *rsvd_pkt, *tmp; 2088 unsigned long flags; 2089 2090 rtw_wait_firmware_completion(rtwdev); 2091 2092 if (fw->firmware) 2093 release_firmware(fw->firmware); 2094 2095 if (wow_fw->firmware) 2096 release_firmware(wow_fw->firmware); 2097 2098 destroy_workqueue(rtwdev->tx_wq); 2099 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags); 2100 skb_queue_purge(&rtwdev->tx_report.queue); 2101 skb_queue_purge(&rtwdev->coex.queue); 2102 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags); 2103 2104 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list, 2105 build_list) { 2106 list_del(&rsvd_pkt->build_list); 2107 kfree(rsvd_pkt); 2108 } 2109 2110 mutex_destroy(&rtwdev->mutex); 2111 mutex_destroy(&rtwdev->coex.mutex); 2112 mutex_destroy(&rtwdev->hal.tx_power_mutex); 2113 } 2114 EXPORT_SYMBOL(rtw_core_deinit); 2115 2116 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2117 { 2118 struct rtw_hal *hal = &rtwdev->hal; 2119 int max_tx_headroom = 0; 2120 int ret; 2121 2122 /* TODO: USB & SDIO may need extra room? */ 2123 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz; 2124 2125 hw->extra_tx_headroom = max_tx_headroom; 2126 hw->queues = IEEE80211_NUM_ACS; 2127 hw->txq_data_size = sizeof(struct rtw_txq); 2128 hw->sta_data_size = sizeof(struct rtw_sta_info); 2129 hw->vif_data_size = sizeof(struct rtw_vif); 2130 2131 ieee80211_hw_set(hw, SIGNAL_DBM); 2132 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 2133 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 2134 ieee80211_hw_set(hw, MFP_CAPABLE); 2135 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 2136 ieee80211_hw_set(hw, SUPPORTS_PS); 2137 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 2138 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 2139 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 2140 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 2141 ieee80211_hw_set(hw, TX_AMSDU); 2142 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 2143 2144 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 2145 BIT(NL80211_IFTYPE_AP) | 2146 BIT(NL80211_IFTYPE_ADHOC) | 2147 BIT(NL80211_IFTYPE_MESH_POINT); 2148 hw->wiphy->available_antennas_tx = hal->antenna_tx; 2149 hw->wiphy->available_antennas_rx = hal->antenna_rx; 2150 2151 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 2152 WIPHY_FLAG_TDLS_EXTERNAL_SETUP; 2153 2154 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 2155 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS; 2156 hw->wiphy->max_scan_ie_len = RTW_SCAN_MAX_IE_LEN; 2157 2158 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 2159 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 2160 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 2161 2162 #ifdef CONFIG_PM 2163 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 2164 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids; 2165 #endif 2166 rtw_set_supported_band(hw, rtwdev->chip); 2167 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr); 2168 2169 hw->wiphy->sar_capa = &rtw_sar_capa; 2170 2171 ret = rtw_regd_init(rtwdev); 2172 if (ret) { 2173 rtw_err(rtwdev, "failed to init regd\n"); 2174 return ret; 2175 } 2176 2177 ret = ieee80211_register_hw(hw); 2178 if (ret) { 2179 rtw_err(rtwdev, "failed to register hw\n"); 2180 return ret; 2181 } 2182 2183 ret = rtw_regd_hint(rtwdev); 2184 if (ret) { 2185 rtw_err(rtwdev, "failed to hint regd\n"); 2186 return ret; 2187 } 2188 2189 rtw_debugfs_init(rtwdev); 2190 2191 rtwdev->bf_info.bfer_mu_cnt = 0; 2192 rtwdev->bf_info.bfer_su_cnt = 0; 2193 2194 return 0; 2195 } 2196 EXPORT_SYMBOL(rtw_register_hw); 2197 2198 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw) 2199 { 2200 struct rtw_chip_info *chip = rtwdev->chip; 2201 2202 ieee80211_unregister_hw(hw); 2203 rtw_unset_supported_band(hw, chip); 2204 } 2205 EXPORT_SYMBOL(rtw_unregister_hw); 2206 2207 MODULE_AUTHOR("Realtek Corporation"); 2208 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module"); 2209 MODULE_LICENSE("Dual BSD/GPL");
Cache object: 0eff575c60916c5154b316542d94fabd
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