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sys/contrib/dev/rtw88/rtw8723d.c
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1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/module.h> 6 #include "main.h" 7 #include "coex.h" 8 #include "fw.h" 9 #include "tx.h" 10 #include "rx.h" 11 #include "phy.h" 12 #include "rtw8723d.h" 13 #include "rtw8723d_table.h" 14 #include "mac.h" 15 #include "reg.h" 16 #include "debug.h" 17 18 static const struct rtw_hw_reg rtw8723d_txagc[] = { 19 [DESC_RATE1M] = { .addr = 0xe08, .mask = 0x0000ff00 }, 20 [DESC_RATE2M] = { .addr = 0x86c, .mask = 0x0000ff00 }, 21 [DESC_RATE5_5M] = { .addr = 0x86c, .mask = 0x00ff0000 }, 22 [DESC_RATE11M] = { .addr = 0x86c, .mask = 0xff000000 }, 23 [DESC_RATE6M] = { .addr = 0xe00, .mask = 0x000000ff }, 24 [DESC_RATE9M] = { .addr = 0xe00, .mask = 0x0000ff00 }, 25 [DESC_RATE12M] = { .addr = 0xe00, .mask = 0x00ff0000 }, 26 [DESC_RATE18M] = { .addr = 0xe00, .mask = 0xff000000 }, 27 [DESC_RATE24M] = { .addr = 0xe04, .mask = 0x000000ff }, 28 [DESC_RATE36M] = { .addr = 0xe04, .mask = 0x0000ff00 }, 29 [DESC_RATE48M] = { .addr = 0xe04, .mask = 0x00ff0000 }, 30 [DESC_RATE54M] = { .addr = 0xe04, .mask = 0xff000000 }, 31 [DESC_RATEMCS0] = { .addr = 0xe10, .mask = 0x000000ff }, 32 [DESC_RATEMCS1] = { .addr = 0xe10, .mask = 0x0000ff00 }, 33 [DESC_RATEMCS2] = { .addr = 0xe10, .mask = 0x00ff0000 }, 34 [DESC_RATEMCS3] = { .addr = 0xe10, .mask = 0xff000000 }, 35 [DESC_RATEMCS4] = { .addr = 0xe14, .mask = 0x000000ff }, 36 [DESC_RATEMCS5] = { .addr = 0xe14, .mask = 0x0000ff00 }, 37 [DESC_RATEMCS6] = { .addr = 0xe14, .mask = 0x00ff0000 }, 38 [DESC_RATEMCS7] = { .addr = 0xe14, .mask = 0xff000000 }, 39 }; 40 41 #define WLAN_TXQ_RPT_EN 0x1F 42 #define WLAN_SLOT_TIME 0x09 43 #define WLAN_RL_VAL 0x3030 44 #define WLAN_BAR_VAL 0x0201ffff 45 #define BIT_MASK_TBTT_HOLD 0x00000fff 46 #define BIT_SHIFT_TBTT_HOLD 8 47 #define BIT_MASK_TBTT_SETUP 0x000000ff 48 #define BIT_SHIFT_TBTT_SETUP 0 49 #define BIT_MASK_TBTT_MASK ((BIT_MASK_TBTT_HOLD << BIT_SHIFT_TBTT_HOLD) | \ 50 (BIT_MASK_TBTT_SETUP << BIT_SHIFT_TBTT_SETUP)) 51 #define TBTT_TIME(s, h)((((s) & BIT_MASK_TBTT_SETUP) << BIT_SHIFT_TBTT_SETUP) |\ 52 (((h) & BIT_MASK_TBTT_HOLD) << BIT_SHIFT_TBTT_HOLD)) 53 #define WLAN_TBTT_TIME_NORMAL TBTT_TIME(0x04, 0x80) 54 #define WLAN_TBTT_TIME_STOP_BCN TBTT_TIME(0x04, 0x64) 55 #define WLAN_PIFS_VAL 0 56 #define WLAN_AGG_BRK_TIME 0x16 57 #define WLAN_NAV_PROT_LEN 0x0040 58 #define WLAN_SPEC_SIFS 0x100a 59 #define WLAN_RX_PKT_LIMIT 0x17 60 #define WLAN_MAX_AGG_NR 0x0A 61 #define WLAN_AMPDU_MAX_TIME 0x1C 62 #define WLAN_ANT_SEL 0x82 63 #define WLAN_LTR_IDLE_LAT 0x90039003 64 #define WLAN_LTR_ACT_LAT 0x883c883c 65 #define WLAN_LTR_CTRL1 0xCB004010 66 #define WLAN_LTR_CTRL2 0x01233425 67 68 static void rtw8723d_lck(struct rtw_dev *rtwdev) 69 { 70 u32 lc_cal; 71 u8 val_ctx, rf_val; 72 int ret; 73 74 val_ctx = rtw_read8(rtwdev, REG_CTX); 75 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) 76 rtw_write8(rtwdev, REG_CTX, val_ctx & ~BIT_MASK_CTX_TYPE); 77 else 78 rtw_write8(rtwdev, REG_TXPAUSE, 0xFF); 79 lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 80 81 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal | BIT_LCK); 82 83 ret = read_poll_timeout(rtw_read_rf, rf_val, rf_val != 0x1, 84 10000, 1000000, false, 85 rtwdev, RF_PATH_A, RF_CFGCH, BIT_LCK); 86 if (ret) 87 rtw_warn(rtwdev, "failed to poll LCK status bit\n"); 88 89 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal); 90 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) 91 rtw_write8(rtwdev, REG_CTX, val_ctx); 92 else 93 rtw_write8(rtwdev, REG_TXPAUSE, 0x00); 94 } 95 96 static const u32 rtw8723d_ofdm_swing_table[] = { 97 0x0b40002d, 0x0c000030, 0x0cc00033, 0x0d800036, 0x0e400039, 0x0f00003c, 98 0x10000040, 0x11000044, 0x12000048, 0x1300004c, 0x14400051, 0x15800056, 99 0x16c0005b, 0x18000060, 0x19800066, 0x1b00006c, 0x1c800072, 0x1e400079, 100 0x20000080, 0x22000088, 0x24000090, 0x26000098, 0x288000a2, 0x2ac000ab, 101 0x2d4000b5, 0x300000c0, 0x32c000cb, 0x35c000d7, 0x390000e4, 0x3c8000f2, 102 0x40000100, 0x43c0010f, 0x47c0011f, 0x4c000130, 0x50800142, 0x55400155, 103 0x5a400169, 0x5fc0017f, 0x65400195, 0x6b8001ae, 0x71c001c7, 0x788001e2, 104 0x7f8001fe, 105 }; 106 107 static const u32 rtw8723d_cck_swing_table[] = { 108 0x0CD, 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158, 109 0x16C, 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263, 110 0x287, 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F, 111 0x47F, 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C, 112 0x7FF, 113 }; 114 115 #define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8723d_ofdm_swing_table) 116 #define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8723d_cck_swing_table) 117 118 static void rtw8723d_pwrtrack_init(struct rtw_dev *rtwdev) 119 { 120 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 121 u8 path; 122 123 dm_info->default_ofdm_index = RTW_DEF_OFDM_SWING_INDEX; 124 125 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 126 ewma_thermal_init(&dm_info->avg_thermal[path]); 127 dm_info->delta_power_index[path] = 0; 128 } 129 dm_info->pwr_trk_triggered = false; 130 dm_info->pwr_trk_init_trigger = true; 131 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 132 dm_info->txagc_remnant_cck = 0; 133 dm_info->txagc_remnant_ofdm = 0; 134 } 135 136 static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev) 137 { 138 u8 xtal_cap; 139 u32 val32; 140 141 /* power on BB/RF domain */ 142 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, 143 BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 144 rtw_write8_set(rtwdev, REG_RF_CTRL, 145 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 146 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80); 147 148 rtw_phy_load_tables(rtwdev); 149 150 /* post init after header files config */ 151 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF); 152 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, BIT_HIQ_NO_LMT_EN_ROOT); 153 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN); 154 155 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; 156 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, 157 xtal_cap | (xtal_cap << 6)); 158 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN); 159 if ((rtwdev->efuse.afe >> 4) == 14) { 160 rtw_write32_set(rtwdev, REG_AFE_CTRL3, BIT_XTAL_GMP_BIT4); 161 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BITS_PLL); 162 rtw_write32_set(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA1); 163 rtw_write32_clr(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA0); 164 } 165 166 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 167 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 168 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL); 169 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL); 170 rtw_write8(rtwdev, REG_ATIMWND, 0x2); 171 rtw_write8(rtwdev, REG_BCN_CTRL, 172 BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT); 173 val32 = rtw_read32(rtwdev, REG_TBTT_PROHIBIT); 174 val32 &= ~BIT_MASK_TBTT_MASK; 175 val32 |= WLAN_TBTT_TIME_STOP_BCN; 176 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, val32); 177 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL); 178 rtw_write8(rtwdev, REG_AGGR_BREAK_TIME, WLAN_AGG_BRK_TIME); 179 rtw_write16(rtwdev, REG_NAV_PROT_LEN, WLAN_NAV_PROT_LEN); 180 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS); 181 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS); 182 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS); 183 rtw_write8(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU); 184 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT); 185 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR); 186 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME); 187 rtw_write8(rtwdev, REG_LEDCFG2, WLAN_ANT_SEL); 188 189 rtw_write32(rtwdev, REG_LTR_IDLE_LATENCY, WLAN_LTR_IDLE_LAT); 190 rtw_write32(rtwdev, REG_LTR_ACTIVE_LATENCY, WLAN_LTR_ACT_LAT); 191 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC, WLAN_LTR_CTRL1); 192 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC + 4, WLAN_LTR_CTRL2); 193 194 rtw_phy_init(rtwdev); 195 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; 196 197 rtw_write16_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN); 198 199 rtw8723d_lck(rtwdev); 200 201 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); 202 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); 203 204 rtw8723d_pwrtrack_init(rtwdev); 205 } 206 207 static void rtw8723de_efuse_parsing(struct rtw_efuse *efuse, 208 struct rtw8723d_efuse *map) 209 { 210 ether_addr_copy(efuse->addr, map->e.mac_addr); 211 } 212 213 static int rtw8723d_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 214 { 215 struct rtw_efuse *efuse = &rtwdev->efuse; 216 struct rtw8723d_efuse *map; 217 int i; 218 219 map = (struct rtw8723d_efuse *)log_map; 220 221 efuse->rfe_option = 0; 222 efuse->rf_board_option = map->rf_board_option; 223 efuse->crystal_cap = map->xtal_k; 224 efuse->pa_type_2g = map->pa_type; 225 efuse->lna_type_2g = map->lna_type_2g[0]; 226 efuse->channel_plan = map->channel_plan; 227 efuse->country_code[0] = map->country_code[0]; 228 efuse->country_code[1] = map->country_code[1]; 229 efuse->bt_setting = map->rf_bt_setting; 230 efuse->regd = map->rf_board_option & 0x7; 231 efuse->thermal_meter[0] = map->thermal_meter; 232 efuse->thermal_meter_k = map->thermal_meter; 233 efuse->afe = map->afe; 234 235 for (i = 0; i < 4; i++) 236 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 237 238 switch (rtw_hci_type(rtwdev)) { 239 case RTW_HCI_TYPE_PCIE: 240 rtw8723de_efuse_parsing(efuse, map); 241 break; 242 default: 243 /* unsupported now */ 244 return -ENOTSUPP; 245 } 246 247 return 0; 248 } 249 250 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 251 struct rtw_rx_pkt_stat *pkt_stat) 252 { 253 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 254 s8 min_rx_power = -120; 255 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status); 256 257 pkt_stat->rx_power[RF_PATH_A] = pwdb - 97; 258 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 259 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 260 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 261 min_rx_power); 262 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 263 } 264 265 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 266 struct rtw_rx_pkt_stat *pkt_stat) 267 { 268 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 269 u8 rxsc, bw; 270 s8 min_rx_power = -120; 271 s8 rx_evm; 272 273 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 274 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 275 else 276 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 277 278 if (GET_PHY_STAT_P1_RF_MODE(phy_status) == 0) 279 bw = RTW_CHANNEL_WIDTH_20; 280 else if ((rxsc == 1) || (rxsc == 2)) 281 bw = RTW_CHANNEL_WIDTH_20; 282 else 283 bw = RTW_CHANNEL_WIDTH_40; 284 285 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 286 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 287 pkt_stat->bw = bw; 288 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 289 min_rx_power); 290 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 291 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 292 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 293 294 dm_info->curr_rx_rate = pkt_stat->rate; 295 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 296 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1; 297 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1; 298 299 rx_evm = clamp_t(s8, -pkt_stat->rx_evm[RF_PATH_A] >> 1, 0, 64); 300 rx_evm &= 0x3F; /* 64->0: second path of 1SS rate is 64 */ 301 dm_info->rx_evm_dbm[RF_PATH_A] = rx_evm; 302 } 303 304 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 305 struct rtw_rx_pkt_stat *pkt_stat) 306 { 307 u8 page; 308 309 page = *phy_status & 0xf; 310 311 switch (page) { 312 case 0: 313 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 314 break; 315 case 1: 316 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 317 break; 318 default: 319 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 320 return; 321 } 322 } 323 324 static void rtw8723d_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 325 struct rtw_rx_pkt_stat *pkt_stat, 326 struct ieee80211_rx_status *rx_status) 327 { 328 struct ieee80211_hdr *hdr; 329 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 330 u8 *phy_status = NULL; 331 332 memset(pkt_stat, 0, sizeof(*pkt_stat)); 333 334 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 335 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 336 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 337 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 338 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 339 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 340 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 341 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 342 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 343 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 344 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 345 pkt_stat->ppdu_cnt = 0; 346 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 347 348 /* drv_info_sz is in unit of 8-bytes */ 349 pkt_stat->drv_info_sz *= 8; 350 351 /* c2h cmd pkt's rx/phy status is not interested */ 352 if (pkt_stat->is_c2h) 353 return; 354 355 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 356 pkt_stat->drv_info_sz); 357 if (pkt_stat->phy_status) { 358 phy_status = rx_desc + desc_sz + pkt_stat->shift; 359 query_phy_status(rtwdev, phy_status, pkt_stat); 360 } 361 362 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 363 } 364 365 static bool rtw8723d_check_spur_ov_thres(struct rtw_dev *rtwdev, 366 u8 channel, u32 thres) 367 { 368 u32 freq; 369 bool ret = false; 370 371 if (channel == 13) 372 freq = FREQ_CH13; 373 else if (channel == 14) 374 freq = FREQ_CH14; 375 else 376 return false; 377 378 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE); 379 rtw_write32(rtwdev, REG_PSDFN, freq); 380 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq); 381 382 msleep(30); 383 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres) 384 ret = true; 385 386 rtw_write32(rtwdev, REG_PSDFN, freq); 387 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE); 388 389 return ret; 390 } 391 392 static void rtw8723d_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch) 393 { 394 if (!notch) { 395 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); 396 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 397 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 398 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 399 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 400 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 401 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 402 return; 403 } 404 405 switch (channel) { 406 case 13: 407 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); 408 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 409 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x04000000); 410 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 411 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 412 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 413 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 414 break; 415 case 14: 416 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5); 417 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 418 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 419 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 420 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 421 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00080000); 422 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 423 break; 424 default: 425 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 426 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 427 break; 428 } 429 } 430 431 static void rtw8723d_spur_cal(struct rtw_dev *rtwdev, u8 channel) 432 { 433 bool notch; 434 435 if (channel < 13) { 436 rtw8723d_cfg_notch(rtwdev, channel, false); 437 return; 438 } 439 440 notch = rtw8723d_check_spur_ov_thres(rtwdev, channel, SPUR_THRES); 441 rtw8723d_cfg_notch(rtwdev, channel, notch); 442 } 443 444 static void rtw8723d_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 445 { 446 u32 rf_cfgch_a, rf_cfgch_b; 447 448 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 449 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK); 450 451 rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK; 452 rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK; 453 rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK); 454 rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK); 455 456 rf_cfgch_a &= ~RFCFGCH_BW_MASK; 457 switch (bw) { 458 case RTW_CHANNEL_WIDTH_20: 459 rf_cfgch_a |= RFCFGCH_BW_20M; 460 break; 461 case RTW_CHANNEL_WIDTH_40: 462 rf_cfgch_a |= RFCFGCH_BW_40M; 463 break; 464 default: 465 break; 466 } 467 468 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a); 469 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b); 470 471 rtw8723d_spur_cal(rtwdev, channel); 472 } 473 474 static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR] = { 475 [0] = { 476 { .len = 4, .reg = 0xA24, .val = 0x64B80C1C }, 477 { .len = 4, .reg = 0xA28, .val = 0x00008810 }, 478 { .len = 4, .reg = 0xAAC, .val = 0x01235667 }, 479 }, 480 [1] = { 481 { .len = 4, .reg = 0xA24, .val = 0x0000B81C }, 482 { .len = 4, .reg = 0xA28, .val = 0x00000000 }, 483 { .len = 4, .reg = 0xAAC, .val = 0x00003667 }, 484 }, 485 }; 486 487 static void rtw8723d_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 488 u8 primary_ch_idx) 489 { 490 const struct rtw_backup_info *cck_dfir; 491 int i; 492 493 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1]; 494 495 for (i = 0; i < CCK_DFIR_NR; i++, cck_dfir++) 496 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val); 497 498 switch (bw) { 499 case RTW_CHANNEL_WIDTH_20: 500 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0); 501 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0); 502 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 1); 503 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa); 504 break; 505 case RTW_CHANNEL_WIDTH_40: 506 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1); 507 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1); 508 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0); 509 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND, 510 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); 511 break; 512 default: 513 break; 514 } 515 } 516 517 static void rtw8723d_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 518 u8 primary_chan_idx) 519 { 520 rtw8723d_set_channel_rf(rtwdev, channel, bw); 521 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 522 rtw8723d_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 523 } 524 525 #define BIT_CFENDFORM BIT(9) 526 #define BIT_WMAC_TCR_ERR0 BIT(12) 527 #define BIT_WMAC_TCR_ERR1 BIT(13) 528 #define BIT_TCR_CFG (BIT_CFENDFORM | BIT_WMAC_TCR_ERR0 | \ 529 BIT_WMAC_TCR_ERR1) 530 #define WLAN_RX_FILTER0 0xFFFF 531 #define WLAN_RX_FILTER1 0x400 532 #define WLAN_RX_FILTER2 0xFFFF 533 #define WLAN_RCR_CFG 0x700060CE 534 535 static int rtw8723d_mac_init(struct rtw_dev *rtwdev) 536 { 537 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 538 rtw_write32(rtwdev, REG_TCR, BIT_TCR_CFG); 539 540 rtw_write16(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 541 rtw_write16(rtwdev, REG_RXFLTMAP1, WLAN_RX_FILTER1); 542 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 543 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 544 545 rtw_write32(rtwdev, REG_INT_MIG, 0); 546 rtw_write32(rtwdev, REG_MCUTST_1, 0x0); 547 548 rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA); 549 rtw_write8(rtwdev, REG_2ND_CCA_CTRL, 0); 550 551 return 0; 552 } 553 554 static void rtw8723d_shutdown(struct rtw_dev *rtwdev) 555 { 556 rtw_write16_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS); 557 } 558 559 static void rtw8723d_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 560 { 561 u8 ldo_pwr; 562 563 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 564 if (enable) { 565 ldo_pwr &= ~BIT_MASK_LDO25_VOLTAGE; 566 ldo_pwr |= (BIT_LDO25_VOLTAGE_V25 << 4) | BIT_LDO25_EN; 567 } else { 568 ldo_pwr &= ~BIT_LDO25_EN; 569 } 570 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 571 } 572 573 static void 574 rtw8723d_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 575 { 576 struct rtw_hal *hal = &rtwdev->hal; 577 const struct rtw_hw_reg *txagc; 578 u8 rate, pwr_index; 579 int j; 580 581 for (j = 0; j < rtw_rate_size[rs]; j++) { 582 rate = rtw_rate_section[rs][j]; 583 pwr_index = hal->tx_pwr_tbl[path][rate]; 584 585 if (rate >= ARRAY_SIZE(rtw8723d_txagc)) { 586 rtw_warn(rtwdev, "rate 0x%x isn't supported\n", rate); 587 continue; 588 } 589 txagc = &rtw8723d_txagc[rate]; 590 if (!txagc->addr) { 591 rtw_warn(rtwdev, "rate 0x%x isn't defined\n", rate); 592 continue; 593 } 594 595 rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index); 596 } 597 } 598 599 static void rtw8723d_set_tx_power_index(struct rtw_dev *rtwdev) 600 { 601 struct rtw_hal *hal = &rtwdev->hal; 602 int rs, path; 603 604 for (path = 0; path < hal->rf_path_num; path++) { 605 for (rs = 0; rs <= RTW_RATE_SECTION_HT_1S; rs++) 606 rtw8723d_set_tx_power_index_by_rate(rtwdev, path, rs); 607 } 608 } 609 610 static void rtw8723d_efuse_grant(struct rtw_dev *rtwdev, bool on) 611 { 612 if (on) { 613 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); 614 615 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR); 616 rtw_write16_set(rtwdev, REG_SYS_CLKR, BIT_LOADER_CLK_EN | BIT_ANA8M); 617 } else { 618 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); 619 } 620 } 621 622 static void rtw8723d_false_alarm_statistics(struct rtw_dev *rtwdev) 623 { 624 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 625 u32 cck_fa_cnt; 626 u32 ofdm_fa_cnt; 627 u32 crc32_cnt; 628 u32 val32; 629 630 /* hold counter */ 631 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1); 632 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1); 633 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1); 634 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1); 635 636 cck_fa_cnt = rtw_read32_mask(rtwdev, REG_CCK_FA_LSB_11N, MASKBYTE0); 637 cck_fa_cnt += rtw_read32_mask(rtwdev, REG_CCK_FA_MSB_11N, MASKBYTE3) << 8; 638 639 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE1_11N); 640 ofdm_fa_cnt = u32_get_bits(val32, BIT_MASK_OFDM_FF_CNT); 641 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_SF_CNT); 642 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE2_11N); 643 dm_info->ofdm_cca_cnt = u32_get_bits(val32, BIT_MASK_OFDM_CCA_CNT); 644 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_PF_CNT); 645 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE3_11N); 646 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_RI_CNT); 647 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_CRC_CNT); 648 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE4_11N); 649 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_MNS_CNT); 650 651 dm_info->cck_fa_cnt = cck_fa_cnt; 652 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 653 dm_info->total_fa_cnt = cck_fa_cnt + ofdm_fa_cnt; 654 655 dm_info->cck_err_cnt = rtw_read32(rtwdev, REG_IGI_C_11N); 656 dm_info->cck_ok_cnt = rtw_read32(rtwdev, REG_IGI_D_11N); 657 crc32_cnt = rtw_read32(rtwdev, REG_OFDM_CRC32_CNT_11N); 658 dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_ERR); 659 dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_OK); 660 crc32_cnt = rtw_read32(rtwdev, REG_HT_CRC32_CNT_11N); 661 dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_ERR); 662 dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_OK); 663 dm_info->vht_err_cnt = 0; 664 dm_info->vht_ok_cnt = 0; 665 666 val32 = rtw_read32(rtwdev, REG_CCK_CCA_CNT_11N); 667 dm_info->cck_cca_cnt = (u32_get_bits(val32, BIT_MASK_CCK_FA_MSB) << 8) | 668 u32_get_bits(val32, BIT_MASK_CCK_FA_LSB); 669 dm_info->total_cca_cnt = dm_info->cck_cca_cnt + dm_info->ofdm_cca_cnt; 670 671 /* reset counter */ 672 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1); 673 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0); 674 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1); 675 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0); 676 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0); 677 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0); 678 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0); 679 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 2); 680 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0); 681 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 2); 682 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 1); 683 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0); 684 } 685 686 static const u32 iqk_adda_regs[] = { 687 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 688 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec 689 }; 690 691 static const u32 iqk_mac8_regs[] = {0x522, 0x550, 0x551}; 692 static const u32 iqk_mac32_regs[] = {0x40}; 693 694 static const u32 iqk_bb_regs[] = { 695 0xc04, 0xc08, 0x874, 0xb68, 0xb6c, 0x870, 0x860, 0x864, 0xa04 696 }; 697 698 #define IQK_ADDA_REG_NUM ARRAY_SIZE(iqk_adda_regs) 699 #define IQK_MAC8_REG_NUM ARRAY_SIZE(iqk_mac8_regs) 700 #define IQK_MAC32_REG_NUM ARRAY_SIZE(iqk_mac32_regs) 701 #define IQK_BB_REG_NUM ARRAY_SIZE(iqk_bb_regs) 702 703 struct iqk_backup_regs { 704 u32 adda[IQK_ADDA_REG_NUM]; 705 u8 mac8[IQK_MAC8_REG_NUM]; 706 u32 mac32[IQK_MAC32_REG_NUM]; 707 u32 bb[IQK_BB_REG_NUM]; 708 709 u32 lte_path; 710 u32 lte_gnt; 711 712 u32 bb_sel_btg; 713 u8 btg_sel; 714 715 u8 igia; 716 u8 igib; 717 }; 718 719 static void rtw8723d_iqk_backup_regs(struct rtw_dev *rtwdev, 720 struct iqk_backup_regs *backup) 721 { 722 int i; 723 724 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 725 backup->adda[i] = rtw_read32(rtwdev, iqk_adda_regs[i]); 726 727 for (i = 0; i < IQK_MAC8_REG_NUM; i++) 728 backup->mac8[i] = rtw_read8(rtwdev, iqk_mac8_regs[i]); 729 for (i = 0; i < IQK_MAC32_REG_NUM; i++) 730 backup->mac32[i] = rtw_read32(rtwdev, iqk_mac32_regs[i]); 731 732 for (i = 0; i < IQK_BB_REG_NUM; i++) 733 backup->bb[i] = rtw_read32(rtwdev, iqk_bb_regs[i]); 734 735 backup->igia = rtw_read32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0); 736 backup->igib = rtw_read32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0); 737 738 backup->bb_sel_btg = rtw_read32(rtwdev, REG_BB_SEL_BTG); 739 } 740 741 static void rtw8723d_iqk_restore_regs(struct rtw_dev *rtwdev, 742 const struct iqk_backup_regs *backup) 743 { 744 int i; 745 746 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 747 rtw_write32(rtwdev, iqk_adda_regs[i], backup->adda[i]); 748 749 for (i = 0; i < IQK_MAC8_REG_NUM; i++) 750 rtw_write8(rtwdev, iqk_mac8_regs[i], backup->mac8[i]); 751 for (i = 0; i < IQK_MAC32_REG_NUM; i++) 752 rtw_write32(rtwdev, iqk_mac32_regs[i], backup->mac32[i]); 753 754 for (i = 0; i < IQK_BB_REG_NUM; i++) 755 rtw_write32(rtwdev, iqk_bb_regs[i], backup->bb[i]); 756 757 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); 758 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, backup->igia); 759 760 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, 0x50); 761 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, backup->igib); 762 763 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x01008c00); 764 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x01008c00); 765 } 766 767 static void rtw8723d_iqk_backup_path_ctrl(struct rtw_dev *rtwdev, 768 struct iqk_backup_regs *backup) 769 { 770 backup->btg_sel = rtw_read8(rtwdev, REG_BTG_SEL); 771 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] original 0x67 = 0x%x\n", 772 backup->btg_sel); 773 } 774 775 static void rtw8723d_iqk_config_path_ctrl(struct rtw_dev *rtwdev) 776 { 777 rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1); 778 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] set 0x67 = 0x%x\n", 779 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 780 } 781 782 static void rtw8723d_iqk_restore_path_ctrl(struct rtw_dev *rtwdev, 783 const struct iqk_backup_regs *backup) 784 { 785 rtw_write8(rtwdev, REG_BTG_SEL, backup->btg_sel); 786 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] restore 0x67 = 0x%x\n", 787 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 788 } 789 790 static void rtw8723d_iqk_backup_lte_path_gnt(struct rtw_dev *rtwdev, 791 struct iqk_backup_regs *backup) 792 { 793 backup->lte_path = rtw_read32(rtwdev, REG_LTECOEX_PATH_CONTROL); 794 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0038); 795 mdelay(1); 796 backup->lte_gnt = rtw_read32(rtwdev, REG_LTECOEX_READ_DATA); 797 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] OriginalGNT = 0x%x\n", 798 backup->lte_gnt); 799 } 800 801 static void rtw8723d_iqk_config_lte_path_gnt(struct rtw_dev *rtwdev) 802 { 803 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, 0x0000ff00); 804 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc0020038); 805 rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL, BIT_LTE_MUX_CTRL_PATH, 0x1); 806 } 807 808 static void rtw8723d_iqk_restore_lte_path_gnt(struct rtw_dev *rtwdev, 809 const struct iqk_backup_regs *bak) 810 { 811 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, bak->lte_gnt); 812 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc00f0038); 813 rtw_write32(rtwdev, REG_LTECOEX_PATH_CONTROL, bak->lte_path); 814 } 815 816 struct rtw_8723d_iqk_cfg { 817 const char *name; 818 u32 val_bb_sel_btg; 819 u32 reg_lutwe; 820 u32 val_txiqk_pi; 821 u32 reg_padlut; 822 u32 reg_gaintx; 823 u32 reg_bspad; 824 u32 val_wlint; 825 u32 val_wlsel; 826 u32 val_iqkpts; 827 }; 828 829 static const struct rtw_8723d_iqk_cfg iqk_tx_cfg[PATH_NR] = { 830 [PATH_S1] = { 831 .name = "S1", 832 .val_bb_sel_btg = 0x99000000, 833 .reg_lutwe = RF_LUTWE, 834 .val_txiqk_pi = 0x8214019f, 835 .reg_padlut = RF_LUTDBG, 836 .reg_gaintx = RF_GAINTX, 837 .reg_bspad = RF_BSPAD, 838 .val_wlint = 0xe0d, 839 .val_wlsel = 0x60d, 840 .val_iqkpts = 0xfa000000, 841 }, 842 [PATH_S0] = { 843 .name = "S0", 844 .val_bb_sel_btg = 0x99000280, 845 .reg_lutwe = RF_LUTWE2, 846 .val_txiqk_pi = 0x8214018a, 847 .reg_padlut = RF_TXADBG, 848 .reg_gaintx = RF_TRXIQ, 849 .reg_bspad = RF_TXATANK, 850 .val_wlint = 0xe6d, 851 .val_wlsel = 0x66d, 852 .val_iqkpts = 0xf9000000, 853 }, 854 }; 855 856 static u8 rtw8723d_iqk_check_tx_failed(struct rtw_dev *rtwdev, 857 const struct rtw_8723d_iqk_cfg *iqk_cfg) 858 { 859 s32 tx_x, tx_y; 860 u32 tx_fail; 861 862 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n", 863 rtw_read32(rtwdev, REG_IQK_RES_RY)); 864 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", 865 rtw_read32(rtwdev, REG_IQK_RES_TX), 866 rtw_read32(rtwdev, REG_IQK_RES_TY)); 867 rtw_dbg(rtwdev, RTW_DBG_RFK, 868 "[IQK] 0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", 869 rtw_read32(rtwdev, 0xe90), 870 rtw_read32(rtwdev, 0xe98)); 871 872 tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL); 873 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 874 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 875 876 if (!tx_fail && tx_x != IQK_TX_X_ERR && tx_y != IQK_TX_Y_ERR) 877 return IQK_TX_OK; 878 879 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s TXIQK is failed\n", 880 iqk_cfg->name); 881 882 return 0; 883 } 884 885 static u8 rtw8723d_iqk_check_rx_failed(struct rtw_dev *rtwdev, 886 const struct rtw_8723d_iqk_cfg *iqk_cfg) 887 { 888 s32 rx_x, rx_y; 889 u32 rx_fail; 890 891 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n", 892 rtw_read32(rtwdev, REG_IQK_RES_RX), 893 rtw_read32(rtwdev, REG_IQK_RES_RY)); 894 895 rtw_dbg(rtwdev, RTW_DBG_RFK, 896 "[IQK] 0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", 897 rtw_read32(rtwdev, 0xea0), 898 rtw_read32(rtwdev, 0xea8)); 899 900 rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL); 901 rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 902 rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 903 rx_y = abs(iqkxy_to_s32(rx_y)); 904 905 if (!rx_fail && rx_x < IQK_RX_X_UPPER && rx_x > IQK_RX_X_LOWER && 906 rx_y < IQK_RX_Y_LMT) 907 return IQK_RX_OK; 908 909 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s RXIQK STEP2 is failed\n", 910 iqk_cfg->name); 911 912 return 0; 913 } 914 915 static void rtw8723d_iqk_one_shot(struct rtw_dev *rtwdev, bool tx, 916 const struct rtw_8723d_iqk_cfg *iqk_cfg) 917 { 918 u32 pts = (tx ? iqk_cfg->val_iqkpts : 0xf9000000); 919 920 /* enter IQK mode */ 921 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 922 rtw8723d_iqk_config_lte_path_gnt(rtwdev); 923 924 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0054); 925 mdelay(1); 926 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] GNT_BT @%s %sIQK1 = 0x%x\n", 927 iqk_cfg->name, tx ? "TX" : "RX", 928 rtw_read32(rtwdev, REG_LTECOEX_READ_DATA)); 929 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x948 @%s %sIQK1 = 0x%x\n", 930 iqk_cfg->name, tx ? "TX" : "RX", 931 rtw_read32(rtwdev, REG_BB_SEL_BTG)); 932 933 /* One shot, LOK & IQK */ 934 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, pts); 935 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000); 936 937 if (!check_hw_ready(rtwdev, REG_IQK_RES_RY, BIT_IQK_DONE, 1)) 938 rtw_warn(rtwdev, "%s %s IQK isn't done\n", iqk_cfg->name, 939 tx ? "TX" : "RX"); 940 } 941 942 static void rtw8723d_iqk_txrx_path_post(struct rtw_dev *rtwdev, 943 const struct rtw_8723d_iqk_cfg *iqk_cfg, 944 const struct iqk_backup_regs *backup) 945 { 946 rtw8723d_iqk_restore_lte_path_gnt(rtwdev, backup); 947 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg); 948 949 /* leave IQK mode */ 950 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 951 mdelay(1); 952 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x0); 953 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, BIT(0), 0x0); 954 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, BIT(0), 0x0); 955 } 956 957 static u8 rtw8723d_iqk_tx_path(struct rtw_dev *rtwdev, 958 const struct rtw_8723d_iqk_cfg *iqk_cfg, 959 const struct iqk_backup_regs *backup) 960 { 961 u8 status; 962 963 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s TXIQK!!\n", iqk_cfg->name); 964 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s TXIQK = 0x%x\n", 965 iqk_cfg->name, 966 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 967 968 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg); 969 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 970 mdelay(1); 971 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000); 972 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00004); 973 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005d); 974 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xBFFE0); 975 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); 976 977 /* IQK setting */ 978 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x08008c0c); 979 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 980 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, iqk_cfg->val_txiqk_pi); 981 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160200); 982 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 983 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 984 985 /* LOK setting */ 986 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911); 987 988 /* PA, PAD setting */ 989 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1); 990 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0); 991 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x1E0, 0x3); 992 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXIQGEN, 0x1F, 0xf); 993 994 /* LOK setting for 8723D */ 995 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x10, 0x1); 996 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_bspad, 0x1, 0x1); 997 998 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint); 999 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel); 1000 1001 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s TXIQK = 0x%x\n", 1002 iqk_cfg->name, 1003 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); 1004 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s TXIQK = 0x%x\n", 1005 iqk_cfg->name, 1006 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); 1007 1008 rtw8723d_iqk_one_shot(rtwdev, true, iqk_cfg); 1009 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg); 1010 1011 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup); 1012 1013 return status; 1014 } 1015 1016 static u8 rtw8723d_iqk_rx_path(struct rtw_dev *rtwdev, 1017 const struct rtw_8723d_iqk_cfg *iqk_cfg, 1018 const struct iqk_backup_regs *backup) 1019 { 1020 u32 tx_x, tx_y; 1021 u8 status; 1022 1023 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK Step1!!\n", 1024 iqk_cfg->name); 1025 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK1 = 0x%x\n", 1026 iqk_cfg->name, 1027 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 1028 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg); 1029 1030 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1031 1032 /* IQK setting */ 1033 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 1034 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1035 1036 /* path IQK setting */ 1037 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); 1038 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 1039 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1040 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1041 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82160000); 1042 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160000); 1043 1044 /* LOK setting */ 1045 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911); 1046 1047 /* RXIQK mode */ 1048 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000); 1049 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00006); 1050 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f); 1051 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xa7ffb); 1052 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); 1053 1054 /* PA/PAD=0 */ 1055 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1); 1056 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0); 1057 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint); 1058 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel); 1059 1060 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1@ path %s RXIQK1 = 0x%x\n", 1061 iqk_cfg->name, 1062 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); 1063 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2@ path %s RXIQK1 = 0x%x\n", 1064 iqk_cfg->name, 1065 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); 1066 1067 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg); 1068 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg); 1069 1070 if (!status) 1071 goto restore; 1072 1073 /* second round */ 1074 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1075 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1076 1077 rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y)); 1078 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n", 1079 rtw_read32(rtwdev, REG_TXIQK_11N), 1080 BIT_SET_TXIQK_11N(tx_x, tx_y)); 1081 1082 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK STEP2!!\n", 1083 iqk_cfg->name); 1084 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK2 = 0x%x\n", 1085 iqk_cfg->name, 1086 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 1087 1088 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1089 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c); 1090 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c); 1091 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1092 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1093 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82170000); 1094 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28171400); 1095 1096 /* LOK setting */ 1097 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1); 1098 1099 /* RXIQK mode */ 1100 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1101 mdelay(1); 1102 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x80000, 0x1); 1103 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00007); 1104 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f); 1105 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xb3fdb); 1106 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); 1107 1108 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s RXIQK2 = 0x%x\n", 1109 iqk_cfg->name, 1110 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); 1111 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s RXIQK2 = 0x%x\n", 1112 iqk_cfg->name, 1113 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); 1114 1115 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg); 1116 status |= rtw8723d_iqk_check_rx_failed(rtwdev, iqk_cfg); 1117 1118 restore: 1119 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup); 1120 1121 return status; 1122 } 1123 1124 static 1125 void rtw8723d_iqk_fill_s1_matrix(struct rtw_dev *rtwdev, const s32 result[]) 1126 { 1127 s32 oldval_1; 1128 s32 x, y; 1129 s32 tx1_a, tx1_a_ext; 1130 s32 tx1_c, tx1_c_ext; 1131 1132 if (result[IQK_S1_TX_X] == 0) 1133 return; 1134 1135 oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1136 BIT_MASK_TXIQ_ELM_D); 1137 1138 x = iqkxy_to_s32(result[IQK_S1_TX_X]); 1139 tx1_a = iqk_mult(x, oldval_1, &tx1_a_ext); 1140 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1141 BIT_MASK_TXIQ_ELM_A, tx1_a); 1142 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 1143 BIT_MASK_OFDM0_EXT_A, tx1_a_ext); 1144 1145 y = iqkxy_to_s32(result[IQK_S1_TX_Y]); 1146 tx1_c = iqk_mult(y, oldval_1, &tx1_c_ext); 1147 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1148 BIT_SET_TXIQ_ELM_C1(tx1_c)); 1149 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1150 BIT_MASK_TXIQ_ELM_C, BIT_SET_TXIQ_ELM_C2(tx1_c)); 1151 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 1152 BIT_MASK_OFDM0_EXT_C, tx1_c_ext); 1153 1154 rtw_dbg(rtwdev, RTW_DBG_RFK, 1155 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n", 1156 x, tx1_a, oldval_1); 1157 rtw_dbg(rtwdev, RTW_DBG_RFK, 1158 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c); 1159 1160 if (result[IQK_S1_RX_X] == 0) 1161 return; 1162 1163 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_X, 1164 result[IQK_S1_RX_X]); 1165 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_Y1, 1166 BIT_SET_RXIQ_S1_Y1(result[IQK_S1_RX_Y])); 1167 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2, 1168 BIT_SET_RXIQ_S1_Y2(result[IQK_S1_RX_Y])); 1169 } 1170 1171 static 1172 void rtw8723d_iqk_fill_s0_matrix(struct rtw_dev *rtwdev, const s32 result[]) 1173 { 1174 s32 oldval_0; 1175 s32 x, y; 1176 s32 tx0_a, tx0_a_ext; 1177 s32 tx0_c, tx0_c_ext; 1178 1179 if (result[IQK_S0_TX_X] == 0) 1180 return; 1181 1182 oldval_0 = rtw_read32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0); 1183 1184 x = iqkxy_to_s32(result[IQK_S0_TX_X]); 1185 tx0_a = iqk_mult(x, oldval_0, &tx0_a_ext); 1186 1187 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, tx0_a); 1188 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, tx0_a_ext); 1189 1190 y = iqkxy_to_s32(result[IQK_S0_TX_Y]); 1191 tx0_c = iqk_mult(y, oldval_0, &tx0_c_ext); 1192 1193 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, tx0_c); 1194 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, tx0_c_ext); 1195 1196 if (result[IQK_S0_RX_X] == 0) 1197 return; 1198 1199 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_X_S0, 1200 result[IQK_S0_RX_X]); 1201 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_Y_S0, 1202 result[IQK_S0_RX_Y]); 1203 } 1204 1205 static void rtw8723d_iqk_path_adda_on(struct rtw_dev *rtwdev) 1206 { 1207 int i; 1208 1209 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 1210 rtw_write32(rtwdev, iqk_adda_regs[i], 0x03c00016); 1211 } 1212 1213 static void rtw8723d_iqk_config_mac(struct rtw_dev *rtwdev) 1214 { 1215 rtw_write8(rtwdev, REG_TXPAUSE, 0xff); 1216 } 1217 1218 static 1219 void rtw8723d_iqk_rf_standby(struct rtw_dev *rtwdev, enum rtw_rf_path path) 1220 { 1221 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path-%s standby mode!\n", 1222 path == RF_PATH_A ? "S1" : "S0"); 1223 1224 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1225 mdelay(1); 1226 rtw_write_rf(rtwdev, path, RF_MODE, RFREG_MASK, 0x10000); 1227 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 1228 } 1229 1230 static 1231 bool rtw8723d_iqk_similarity_cmp(struct rtw_dev *rtwdev, s32 result[][IQK_NR], 1232 u8 c1, u8 c2) 1233 { 1234 u32 i, j, diff; 1235 u32 bitmap = 0; 1236 u8 candidate[PATH_NR] = {IQK_ROUND_INVALID, IQK_ROUND_INVALID}; 1237 bool ret = true; 1238 1239 s32 tmp1, tmp2; 1240 1241 for (i = 0; i < IQK_NR; i++) { 1242 tmp1 = iqkxy_to_s32(result[c1][i]); 1243 tmp2 = iqkxy_to_s32(result[c2][i]); 1244 1245 diff = abs(tmp1 - tmp2); 1246 1247 if (diff <= MAX_TOLERANCE) 1248 continue; 1249 1250 if ((i == IQK_S1_RX_X || i == IQK_S0_RX_X) && !bitmap) { 1251 if (result[c1][i] + result[c1][i + 1] == 0) 1252 candidate[i / IQK_SX_NR] = c2; 1253 else if (result[c2][i] + result[c2][i + 1] == 0) 1254 candidate[i / IQK_SX_NR] = c1; 1255 else 1256 bitmap |= BIT(i); 1257 } else { 1258 bitmap |= BIT(i); 1259 } 1260 } 1261 1262 if (bitmap != 0) 1263 goto check_sim; 1264 1265 for (i = 0; i < PATH_NR; i++) { 1266 if (candidate[i] == IQK_ROUND_INVALID) 1267 continue; 1268 1269 for (j = i * IQK_SX_NR; j < i * IQK_SX_NR + 2; j++) 1270 result[IQK_ROUND_HYBRID][j] = result[candidate[i]][j]; 1271 ret = false; 1272 } 1273 1274 return ret; 1275 1276 check_sim: 1277 for (i = 0; i < IQK_NR; i++) { 1278 j = i & ~1; /* 2 bits are a pair for IQ[X, Y] */ 1279 if (bitmap & GENMASK(j + 1, j)) 1280 continue; 1281 1282 result[IQK_ROUND_HYBRID][i] = result[c1][i]; 1283 } 1284 1285 return false; 1286 } 1287 1288 static 1289 void rtw8723d_iqk_precfg_path(struct rtw_dev *rtwdev, enum rtw8723d_path path) 1290 { 1291 if (path == PATH_S0) { 1292 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_A); 1293 rtw8723d_iqk_path_adda_on(rtwdev); 1294 } 1295 1296 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 1297 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 1298 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1299 1300 if (path == PATH_S1) { 1301 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_B); 1302 rtw8723d_iqk_path_adda_on(rtwdev); 1303 } 1304 } 1305 1306 static 1307 void rtw8723d_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t, 1308 const struct iqk_backup_regs *backup) 1309 { 1310 u32 i; 1311 u8 s1_ok, s0_ok; 1312 1313 rtw_dbg(rtwdev, RTW_DBG_RFK, 1314 "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t); 1315 1316 rtw8723d_iqk_path_adda_on(rtwdev); 1317 rtw8723d_iqk_config_mac(rtwdev); 1318 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf); 1319 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05611); 1320 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4); 1321 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204200); 1322 rtw8723d_iqk_precfg_path(rtwdev, PATH_S1); 1323 1324 for (i = 0; i < PATH_IQK_RETRY; i++) { 1325 s1_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup); 1326 if (s1_ok == IQK_TX_OK) { 1327 rtw_dbg(rtwdev, RTW_DBG_RFK, 1328 "[IQK] path S1 Tx IQK Success!!\n"); 1329 result[t][IQK_S1_TX_X] = 1330 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1331 result[t][IQK_S1_TX_Y] = 1332 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1333 break; 1334 } 1335 1336 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Tx IQK Fail!!\n"); 1337 result[t][IQK_S1_TX_X] = 0x100; 1338 result[t][IQK_S1_TX_Y] = 0x0; 1339 } 1340 1341 for (i = 0; i < PATH_IQK_RETRY; i++) { 1342 s1_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup); 1343 if (s1_ok == (IQK_TX_OK | IQK_RX_OK)) { 1344 rtw_dbg(rtwdev, RTW_DBG_RFK, 1345 "[IQK] path S1 Rx IQK Success!!\n"); 1346 result[t][IQK_S1_RX_X] = 1347 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 1348 result[t][IQK_S1_RX_Y] = 1349 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 1350 break; 1351 } 1352 1353 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Rx IQK Fail!!\n"); 1354 result[t][IQK_S1_RX_X] = 0x100; 1355 result[t][IQK_S1_RX_Y] = 0x0; 1356 } 1357 1358 if (s1_ok == 0x0) 1359 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 IQK is failed!!\n"); 1360 1361 rtw8723d_iqk_precfg_path(rtwdev, PATH_S0); 1362 1363 for (i = 0; i < PATH_IQK_RETRY; i++) { 1364 s0_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup); 1365 if (s0_ok == IQK_TX_OK) { 1366 rtw_dbg(rtwdev, RTW_DBG_RFK, 1367 "[IQK] path S0 Tx IQK Success!!\n"); 1368 result[t][IQK_S0_TX_X] = 1369 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1370 result[t][IQK_S0_TX_Y] = 1371 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1372 break; 1373 } 1374 1375 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Tx IQK Fail!!\n"); 1376 result[t][IQK_S0_TX_X] = 0x100; 1377 result[t][IQK_S0_TX_Y] = 0x0; 1378 } 1379 1380 for (i = 0; i < PATH_IQK_RETRY; i++) { 1381 s0_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup); 1382 if (s0_ok == (IQK_TX_OK | IQK_RX_OK)) { 1383 rtw_dbg(rtwdev, RTW_DBG_RFK, 1384 "[IQK] path S0 Rx IQK Success!!\n"); 1385 1386 result[t][IQK_S0_RX_X] = 1387 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 1388 result[t][IQK_S0_RX_Y] = 1389 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 1390 break; 1391 } 1392 1393 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Rx IQK Fail!!\n"); 1394 result[t][IQK_S0_RX_X] = 0x100; 1395 result[t][IQK_S0_RX_Y] = 0x0; 1396 } 1397 1398 if (s0_ok == 0x0) 1399 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 IQK is failed!!\n"); 1400 1401 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1402 mdelay(1); 1403 1404 rtw_dbg(rtwdev, RTW_DBG_RFK, 1405 "[IQK] back to BB mode, load original value!\n"); 1406 } 1407 1408 static void rtw8723d_phy_calibration(struct rtw_dev *rtwdev) 1409 { 1410 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1411 s32 result[IQK_ROUND_SIZE][IQK_NR]; 1412 struct iqk_backup_regs backup; 1413 u8 i, j; 1414 u8 final_candidate = IQK_ROUND_INVALID; 1415 bool good; 1416 1417 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!!!\n"); 1418 1419 memset(result, 0, sizeof(result)); 1420 1421 rtw8723d_iqk_backup_path_ctrl(rtwdev, &backup); 1422 rtw8723d_iqk_backup_lte_path_gnt(rtwdev, &backup); 1423 rtw8723d_iqk_backup_regs(rtwdev, &backup); 1424 1425 for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) { 1426 rtw8723d_iqk_config_path_ctrl(rtwdev); 1427 rtw8723d_iqk_config_lte_path_gnt(rtwdev); 1428 1429 rtw8723d_iqk_one_round(rtwdev, result, i, &backup); 1430 1431 if (i > IQK_ROUND_0) 1432 rtw8723d_iqk_restore_regs(rtwdev, &backup); 1433 rtw8723d_iqk_restore_lte_path_gnt(rtwdev, &backup); 1434 rtw8723d_iqk_restore_path_ctrl(rtwdev, &backup); 1435 1436 for (j = IQK_ROUND_0; j < i; j++) { 1437 good = rtw8723d_iqk_similarity_cmp(rtwdev, result, j, i); 1438 1439 if (good) { 1440 final_candidate = j; 1441 rtw_dbg(rtwdev, RTW_DBG_RFK, 1442 "[IQK] cmp %d:%d final_candidate is %x\n", 1443 j, i, final_candidate); 1444 goto iqk_done; 1445 } 1446 } 1447 } 1448 1449 if (final_candidate == IQK_ROUND_INVALID) { 1450 s32 reg_tmp = 0; 1451 1452 for (i = 0; i < IQK_NR; i++) 1453 reg_tmp += result[IQK_ROUND_HYBRID][i]; 1454 1455 if (reg_tmp != 0) { 1456 final_candidate = IQK_ROUND_HYBRID; 1457 } else { 1458 WARN(1, "IQK is failed\n"); 1459 goto out; 1460 } 1461 } 1462 1463 iqk_done: 1464 rtw8723d_iqk_fill_s1_matrix(rtwdev, result[final_candidate]); 1465 rtw8723d_iqk_fill_s0_matrix(rtwdev, result[final_candidate]); 1466 1467 dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X]; 1468 dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y]; 1469 dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X]; 1470 dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y]; 1471 dm_info->iqk.done = true; 1472 1473 out: 1474 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg); 1475 1476 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n", 1477 final_candidate); 1478 1479 for (i = IQK_ROUND_0; i < IQK_ROUND_SIZE; i++) 1480 rtw_dbg(rtwdev, RTW_DBG_RFK, 1481 "[IQK] Result %u: rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x %s\n", 1482 i, 1483 result[i][0], result[i][1], result[i][2], result[i][3], 1484 result[i][4], result[i][5], result[i][6], result[i][7], 1485 final_candidate == i ? "(final candidate)" : ""); 1486 1487 rtw_dbg(rtwdev, RTW_DBG_RFK, 1488 "[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n", 1489 rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE), 1490 rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N), 1491 rtw_read32(rtwdev, REG_A_RXIQI), 1492 rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N)); 1493 rtw_dbg(rtwdev, RTW_DBG_RFK, 1494 "[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n", 1495 rtw_read32(rtwdev, REG_TXIQ_AB_S0), 1496 rtw_read32(rtwdev, REG_TXIQ_CD_S0), 1497 rtw_read32(rtwdev, REG_RXIQ_AB_S0)); 1498 1499 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] finished\n"); 1500 } 1501 1502 static void rtw8723d_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 1503 { 1504 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1505 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13}; 1506 u8 cck_n_rx; 1507 1508 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", 1509 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); 1510 1511 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) 1512 return; 1513 1514 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) && 1515 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1; 1516 rtw_dbg(rtwdev, RTW_DBG_PHY, 1517 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", 1518 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx, 1519 dm_info->cck_pd_default + new_lvl * 2, 1520 pd[new_lvl], dm_info->cck_fa_avg); 1521 1522 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 1523 1524 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; 1525 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); 1526 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, 1527 dm_info->cck_pd_default + new_lvl * 2); 1528 } 1529 1530 /* for coex */ 1531 static void rtw8723d_coex_cfg_init(struct rtw_dev *rtwdev) 1532 { 1533 /* enable TBTT nterrupt */ 1534 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1535 1536 /* BT report packet sample rate */ 1537 /* 0x790[5:0]=0x5 */ 1538 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 1539 1540 /* enable BT counter statistics */ 1541 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 1542 1543 /* enable PTA (3-wire function form BT side) */ 1544 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 1545 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 1546 1547 /* enable PTA (tx/rx signal form WiFi side) */ 1548 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 1549 } 1550 1551 static void rtw8723d_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 1552 { 1553 } 1554 1555 static void rtw8723d_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 1556 { 1557 rtw_write8_mask(rtwdev, REG_LEDCFG2, BIT(6), 0); 1558 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0); 1559 rtw_write8_mask(rtwdev, REG_GPIO_INTM + 2, BIT(4), 0); 1560 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT(1), 0); 1561 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0); 1562 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0); 1563 rtw_write8_mask(rtwdev, REG_SYS_CLKR + 1, BIT(1), 0); 1564 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT(3), 0); 1565 } 1566 1567 static void rtw8723d_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 1568 { 1569 struct rtw_efuse *efuse = &rtwdev->efuse; 1570 struct rtw_coex *coex = &rtwdev->coex; 1571 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1572 bool aux = efuse->bt_setting & BIT(6); 1573 1574 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 1575 coex_rfe->ant_switch_polarity = 0; 1576 coex_rfe->ant_switch_exist = false; 1577 coex_rfe->ant_switch_with_bt = false; 1578 coex_rfe->ant_switch_diversity = false; 1579 coex_rfe->wlg_at_btg = true; 1580 1581 /* decide antenna at main or aux */ 1582 if (efuse->share_ant) { 1583 if (aux) 1584 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x80); 1585 else 1586 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x200); 1587 } else { 1588 if (aux) 1589 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x280); 1590 else 1591 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x0); 1592 } 1593 1594 /* disable LTE coex in wifi side */ 1595 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); 1596 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 1597 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 1598 } 1599 1600 static void rtw8723d_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1601 { 1602 struct rtw_coex *coex = &rtwdev->coex; 1603 struct rtw_coex_dm *coex_dm = &coex->dm; 1604 static const u8 wl_tx_power[] = {0xb2, 0x90}; 1605 u8 pwr; 1606 1607 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 1608 return; 1609 1610 coex_dm->cur_wl_pwr_lvl = wl_pwr; 1611 1612 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power)) 1613 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1; 1614 1615 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl]; 1616 1617 rtw_write8(rtwdev, REG_ANA_PARAM1 + 3, pwr); 1618 } 1619 1620 static void rtw8723d_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1621 { 1622 struct rtw_coex *coex = &rtwdev->coex; 1623 struct rtw_coex_dm *coex_dm = &coex->dm; 1624 /* WL Rx Low gain on */ 1625 static const u32 wl_rx_low_gain_on[] = { 1626 0xec120101, 0xeb130101, 0xce140101, 0xcd150101, 0xcc160101, 1627 0xcb170101, 0xca180101, 0x8d190101, 0x8c1a0101, 0x8b1b0101, 1628 0x4f1c0101, 0x4e1d0101, 0x4d1e0101, 0x4c1f0101, 0x0e200101, 1629 0x0d210101, 0x0c220101, 0x0b230101, 0xcf240001, 0xce250001, 1630 0xcd260001, 0xcc270001, 0x8f280001 1631 }; 1632 /* WL Rx Low gain off */ 1633 static const u32 wl_rx_low_gain_off[] = { 1634 0xec120101, 0xeb130101, 0xea140101, 0xe9150101, 0xe8160101, 1635 0xe7170101, 0xe6180101, 0xe5190101, 0xe41a0101, 0xe31b0101, 1636 0xe21c0101, 0xe11d0101, 0xe01e0101, 0x861f0101, 0x85200101, 1637 0x84210101, 0x83220101, 0x82230101, 0x81240101, 0x80250101, 1638 0x44260101, 0x43270101, 0x42280101 1639 }; 1640 u8 i; 1641 1642 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 1643 return; 1644 1645 coex_dm->cur_wl_rx_low_gain_en = low_gain; 1646 1647 if (coex_dm->cur_wl_rx_low_gain_en) { 1648 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) 1649 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_on[i]); 1650 } else { 1651 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) 1652 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_off[i]); 1653 } 1654 } 1655 1656 static u8 rtw8723d_pwrtrack_get_limit_ofdm(struct rtw_dev *rtwdev) 1657 { 1658 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1659 u8 tx_rate = dm_info->tx_rate; 1660 u8 limit_ofdm = 30; 1661 1662 switch (tx_rate) { 1663 case DESC_RATE1M...DESC_RATE5_5M: 1664 case DESC_RATE11M: 1665 break; 1666 case DESC_RATE6M...DESC_RATE48M: 1667 limit_ofdm = 36; 1668 break; 1669 case DESC_RATE54M: 1670 limit_ofdm = 34; 1671 break; 1672 case DESC_RATEMCS0...DESC_RATEMCS2: 1673 limit_ofdm = 38; 1674 break; 1675 case DESC_RATEMCS3...DESC_RATEMCS4: 1676 limit_ofdm = 36; 1677 break; 1678 case DESC_RATEMCS5...DESC_RATEMCS7: 1679 limit_ofdm = 34; 1680 break; 1681 default: 1682 rtw_warn(rtwdev, "pwrtrack unhandled tx_rate 0x%x\n", tx_rate); 1683 break; 1684 } 1685 1686 return limit_ofdm; 1687 } 1688 1689 static void rtw8723d_set_iqk_matrix_by_result(struct rtw_dev *rtwdev, 1690 u32 ofdm_swing, u8 rf_path) 1691 { 1692 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1693 s32 ele_A, ele_D, ele_C; 1694 s32 ele_A_ext, ele_C_ext, ele_D_ext; 1695 s32 iqk_result_x; 1696 s32 iqk_result_y; 1697 s32 value32; 1698 1699 switch (rf_path) { 1700 default: 1701 case RF_PATH_A: 1702 iqk_result_x = dm_info->iqk.result.s1_x; 1703 iqk_result_y = dm_info->iqk.result.s1_y; 1704 break; 1705 case RF_PATH_B: 1706 iqk_result_x = dm_info->iqk.result.s0_x; 1707 iqk_result_y = dm_info->iqk.result.s0_y; 1708 break; 1709 } 1710 1711 /* new element D */ 1712 ele_D = OFDM_SWING_D(ofdm_swing); 1713 iqk_mult(iqk_result_x, ele_D, &ele_D_ext); 1714 /* new element A */ 1715 iqk_result_x = iqkxy_to_s32(iqk_result_x); 1716 ele_A = iqk_mult(iqk_result_x, ele_D, &ele_A_ext); 1717 /* new element C */ 1718 iqk_result_y = iqkxy_to_s32(iqk_result_y); 1719 ele_C = iqk_mult(iqk_result_y, ele_D, &ele_C_ext); 1720 1721 switch (rf_path) { 1722 case RF_PATH_A: 1723 default: 1724 /* write new elements A, C, D, and element B is always 0 */ 1725 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D); 1726 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32); 1727 value32 = BIT_SET_TXIQ_ELM_C1(ele_C); 1728 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1729 value32); 1730 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1731 value32 &= ~BIT_MASK_OFDM0_EXTS; 1732 value32 |= BIT_SET_OFDM0_EXTS(ele_A_ext, ele_C_ext, ele_D_ext); 1733 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1734 break; 1735 1736 case RF_PATH_B: 1737 /* write new elements A, C, D, and element B is always 0 */ 1738 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, ele_D); 1739 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, ele_C); 1740 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, ele_A); 1741 1742 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 1743 ele_D_ext); 1744 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 1745 ele_A_ext); 1746 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 1747 ele_C_ext); 1748 break; 1749 } 1750 } 1751 1752 static void rtw8723d_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index, 1753 u8 rf_path) 1754 { 1755 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1756 s32 value32; 1757 u32 ofdm_swing; 1758 1759 if (ofdm_index >= RTW_OFDM_SWING_TABLE_SIZE) 1760 ofdm_index = RTW_OFDM_SWING_TABLE_SIZE - 1; 1761 else if (ofdm_index < 0) 1762 ofdm_index = 0; 1763 1764 ofdm_swing = rtw8723d_ofdm_swing_table[ofdm_index]; 1765 1766 if (dm_info->iqk.done) { 1767 rtw8723d_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path); 1768 return; 1769 } 1770 1771 switch (rf_path) { 1772 case RF_PATH_A: 1773 default: 1774 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing); 1775 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1776 0x00); 1777 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1778 value32 &= ~BIT_MASK_OFDM0_EXTS; 1779 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1780 break; 1781 1782 case RF_PATH_B: 1783 /* image S1:c80 to S0:Cd0 and Cd4 */ 1784 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, 1785 OFDM_SWING_A(ofdm_swing)); 1786 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_B_S0, 1787 OFDM_SWING_B(ofdm_swing)); 1788 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, 1789 OFDM_SWING_C(ofdm_swing)); 1790 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, 1791 OFDM_SWING_D(ofdm_swing)); 1792 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 0x0); 1793 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 0x0); 1794 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 0x0); 1795 break; 1796 } 1797 } 1798 1799 static void rtw8723d_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1800 s8 txagc_idx) 1801 { 1802 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1803 1804 dm_info->txagc_remnant_ofdm = txagc_idx; 1805 1806 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A); 1807 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_B); 1808 } 1809 1810 static void rtw8723d_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1811 s8 txagc_idx) 1812 { 1813 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1814 1815 dm_info->txagc_remnant_cck = txagc_idx; 1816 1817 rtw_write32_mask(rtwdev, 0xab4, 0x000007FF, 1818 rtw8723d_cck_swing_table[swing_idx]); 1819 } 1820 1821 static void rtw8723d_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) 1822 { 1823 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1824 struct rtw_hal *hal = &rtwdev->hal; 1825 u8 limit_ofdm; 1826 u8 limit_cck = 40; 1827 s8 final_ofdm_swing_index; 1828 s8 final_cck_swing_index; 1829 1830 limit_ofdm = rtw8723d_pwrtrack_get_limit_ofdm(rtwdev); 1831 1832 final_ofdm_swing_index = RTW_DEF_OFDM_SWING_INDEX + 1833 dm_info->delta_power_index[path]; 1834 final_cck_swing_index = RTW_DEF_CCK_SWING_INDEX + 1835 dm_info->delta_power_index[path]; 1836 1837 if (final_ofdm_swing_index > limit_ofdm) 1838 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm, 1839 final_ofdm_swing_index - limit_ofdm); 1840 else if (final_ofdm_swing_index < 0) 1841 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, 0, 1842 final_ofdm_swing_index); 1843 else 1844 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0); 1845 1846 if (final_cck_swing_index > limit_cck) 1847 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, limit_cck, 1848 final_cck_swing_index - limit_cck); 1849 else if (final_cck_swing_index < 0) 1850 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, 0, 1851 final_cck_swing_index); 1852 else 1853 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0); 1854 1855 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel); 1856 } 1857 1858 static void rtw8723d_pwrtrack_set_xtal(struct rtw_dev *rtwdev, u8 therm_path, 1859 u8 delta) 1860 { 1861 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1862 const struct rtw_pwr_track_tbl *tbl = rtwdev->chip->pwr_track_tbl; 1863 const s8 *pwrtrk_xtal; 1864 s8 xtal_cap; 1865 1866 if (dm_info->thermal_avg[therm_path] > 1867 rtwdev->efuse.thermal_meter[therm_path]) 1868 pwrtrk_xtal = tbl->pwrtrk_xtal_p; 1869 else 1870 pwrtrk_xtal = tbl->pwrtrk_xtal_n; 1871 1872 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; 1873 xtal_cap = clamp_t(s8, xtal_cap + pwrtrk_xtal[delta], 0, 0x3F); 1874 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, 1875 xtal_cap | (xtal_cap << 6)); 1876 } 1877 1878 static void rtw8723d_phy_pwrtrack(struct rtw_dev *rtwdev) 1879 { 1880 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1881 struct rtw_swing_table swing_table; 1882 u8 thermal_value, delta, path; 1883 bool do_iqk = false; 1884 1885 rtw_phy_config_swing_table(rtwdev, &swing_table); 1886 1887 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1888 return; 1889 1890 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1891 1892 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1893 1894 do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev); 1895 1896 if (do_iqk) 1897 rtw8723d_lck(rtwdev); 1898 1899 if (dm_info->pwr_trk_init_trigger) 1900 dm_info->pwr_trk_init_trigger = false; 1901 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1902 RF_PATH_A)) 1903 goto iqk; 1904 1905 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1906 1907 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1908 1909 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1910 s8 delta_cur, delta_last; 1911 1912 delta_last = dm_info->delta_power_index[path]; 1913 delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, 1914 path, RF_PATH_A, delta); 1915 if (delta_last == delta_cur) 1916 continue; 1917 1918 dm_info->delta_power_index[path] = delta_cur; 1919 rtw8723d_pwrtrack_set(rtwdev, path); 1920 } 1921 1922 rtw8723d_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta); 1923 1924 iqk: 1925 if (do_iqk) 1926 rtw8723d_phy_calibration(rtwdev); 1927 } 1928 1929 static void rtw8723d_pwr_track(struct rtw_dev *rtwdev) 1930 { 1931 struct rtw_efuse *efuse = &rtwdev->efuse; 1932 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1933 1934 if (efuse->power_track_type != 0) 1935 return; 1936 1937 if (!dm_info->pwr_trk_triggered) { 1938 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1939 GENMASK(17, 16), 0x03); 1940 dm_info->pwr_trk_triggered = true; 1941 return; 1942 } 1943 1944 rtw8723d_phy_pwrtrack(rtwdev); 1945 dm_info->pwr_trk_triggered = false; 1946 } 1947 1948 static struct rtw_chip_ops rtw8723d_ops = { 1949 .phy_set_param = rtw8723d_phy_set_param, 1950 .read_efuse = rtw8723d_read_efuse, 1951 .query_rx_desc = rtw8723d_query_rx_desc, 1952 .set_channel = rtw8723d_set_channel, 1953 .mac_init = rtw8723d_mac_init, 1954 .shutdown = rtw8723d_shutdown, 1955 .read_rf = rtw_phy_read_rf_sipi, 1956 .write_rf = rtw_phy_write_rf_reg_sipi, 1957 .set_tx_power_index = rtw8723d_set_tx_power_index, 1958 .set_antenna = NULL, 1959 .cfg_ldo25 = rtw8723d_cfg_ldo25, 1960 .efuse_grant = rtw8723d_efuse_grant, 1961 .false_alarm_statistics = rtw8723d_false_alarm_statistics, 1962 .phy_calibration = rtw8723d_phy_calibration, 1963 .cck_pd_set = rtw8723d_phy_cck_pd_set, 1964 .pwr_track = rtw8723d_pwr_track, 1965 .config_bfee = NULL, 1966 .set_gid_table = NULL, 1967 .cfg_csi_rate = NULL, 1968 1969 .coex_set_init = rtw8723d_coex_cfg_init, 1970 .coex_set_ant_switch = NULL, 1971 .coex_set_gnt_fix = rtw8723d_coex_cfg_gnt_fix, 1972 .coex_set_gnt_debug = rtw8723d_coex_cfg_gnt_debug, 1973 .coex_set_rfe_type = rtw8723d_coex_cfg_rfe_type, 1974 .coex_set_wl_tx_power = rtw8723d_coex_cfg_wl_tx_power, 1975 .coex_set_wl_rx_gain = rtw8723d_coex_cfg_wl_rx_gain, 1976 }; 1977 1978 /* Shared-Antenna Coex Table */ 1979 static const struct coex_table_para table_sant_8723d[] = { 1980 {0xffffffff, 0xffffffff}, /* case-0 */ 1981 {0x55555555, 0x55555555}, 1982 {0x66555555, 0x66555555}, 1983 {0xaaaaaaaa, 0xaaaaaaaa}, 1984 {0x5a5a5a5a, 0x5a5a5a5a}, 1985 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1986 {0x6a5a5555, 0xaaaaaaaa}, 1987 {0x6a5a56aa, 0x6a5a56aa}, 1988 {0x6a5a5a5a, 0x6a5a5a5a}, 1989 {0x66555555, 0x5a5a5a5a}, 1990 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1991 {0x66555555, 0x6a5a5aaa}, 1992 {0x66555555, 0x5a5a5aaa}, 1993 {0x66555555, 0x6aaa5aaa}, 1994 {0x66555555, 0xaaaa5aaa}, 1995 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1996 {0xffff55ff, 0xfafafafa}, 1997 {0xffff55ff, 0x6afa5afa}, 1998 {0xaaffffaa, 0xfafafafa}, 1999 {0xaa5555aa, 0x5a5a5a5a}, 2000 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 2001 {0xaa5555aa, 0xaaaaaaaa}, 2002 {0xffffffff, 0x5a5a5a5a}, 2003 {0xffffffff, 0x5a5a5a5a}, 2004 {0xffffffff, 0x55555555}, 2005 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 2006 {0x55555555, 0x5a5a5a5a}, 2007 {0x55555555, 0xaaaaaaaa}, 2008 {0x55555555, 0x6a5a6a5a}, 2009 {0x66556655, 0x66556655}, 2010 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 2011 {0xffffffff, 0x5aaa5aaa}, 2012 {0x56555555, 0x5a5a5aaa}, 2013 }; 2014 2015 /* Non-Shared-Antenna Coex Table */ 2016 static const struct coex_table_para table_nsant_8723d[] = { 2017 {0xffffffff, 0xffffffff}, /* case-100 */ 2018 {0x55555555, 0x55555555}, 2019 {0x66555555, 0x66555555}, 2020 {0xaaaaaaaa, 0xaaaaaaaa}, 2021 {0x5a5a5a5a, 0x5a5a5a5a}, 2022 {0xfafafafa, 0xfafafafa}, /* case-105 */ 2023 {0x5afa5afa, 0x5afa5afa}, 2024 {0x55555555, 0xfafafafa}, 2025 {0x66555555, 0xfafafafa}, 2026 {0x66555555, 0x5a5a5a5a}, 2027 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 2028 {0x66555555, 0xaaaaaaaa}, 2029 {0xffff55ff, 0xfafafafa}, 2030 {0xffff55ff, 0x5afa5afa}, 2031 {0xffff55ff, 0xaaaaaaaa}, 2032 {0xffff55ff, 0xffff55ff}, /* case-115 */ 2033 {0xaaffffaa, 0x5afa5afa}, 2034 {0xaaffffaa, 0xaaaaaaaa}, 2035 {0xffffffff, 0xfafafafa}, 2036 {0xffffffff, 0x5afa5afa}, 2037 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 2038 {0x55ff55ff, 0x5afa5afa}, 2039 {0x55ff55ff, 0xaaaaaaaa}, 2040 {0x55ff55ff, 0x55ff55ff} 2041 }; 2042 2043 /* Shared-Antenna TDMA */ 2044 static const struct coex_tdma_para tdma_sant_8723d[] = { 2045 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 2046 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 2047 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2048 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2049 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2050 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 2051 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2052 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2053 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2054 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2055 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 2056 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2057 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2058 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2059 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2060 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 2061 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 2062 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2063 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2064 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2065 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 2066 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 2067 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 2068 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 2069 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 2070 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 2071 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 2072 { {0x61, 0x08, 0x03, 0x11, 0x11} } 2073 }; 2074 2075 /* Non-Shared-Antenna TDMA */ 2076 static const struct coex_tdma_para tdma_nsant_8723d[] = { 2077 { {0x00, 0x00, 0x00, 0x00, 0x01} }, /* case-100 */ 2078 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */ 2079 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2080 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2081 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2082 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 2083 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2084 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2085 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2086 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2087 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 2088 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2089 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2090 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2091 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2092 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 2093 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 2094 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2095 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2096 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2097 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */ 2098 { {0x51, 0x08, 0x03, 0x10, 0x50} } 2099 }; 2100 2101 /* rssi in percentage % (dbm = % - 100) */ 2102 static const u8 wl_rssi_step_8723d[] = {60, 50, 44, 30}; 2103 static const u8 bt_rssi_step_8723d[] = {30, 30, 30, 30}; 2104 static const struct coex_5g_afh_map afh_5g_8723d[] = { {0, 0, 0} }; 2105 2106 static const struct rtw_hw_reg btg_reg_8723d = { 2107 .addr = REG_BTG_SEL, .mask = BIT_MASK_BTG_WL, 2108 }; 2109 2110 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 2111 static const struct coex_rf_para rf_para_tx_8723d[] = { 2112 {0, 0, false, 7}, /* for normal */ 2113 {0, 10, false, 7}, /* for WL-CPT */ 2114 {1, 0, true, 4}, 2115 {1, 2, true, 4}, 2116 {1, 10, true, 4}, 2117 {1, 15, true, 4} 2118 }; 2119 2120 static const struct coex_rf_para rf_para_rx_8723d[] = { 2121 {0, 0, false, 7}, /* for normal */ 2122 {0, 10, false, 7}, /* for WL-CPT */ 2123 {1, 0, true, 5}, 2124 {1, 2, true, 5}, 2125 {1, 10, true, 5}, 2126 {1, 15, true, 5} 2127 }; 2128 2129 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8723d[] = { 2130 {0x0005, 2131 RTW_PWR_CUT_ALL_MSK, 2132 RTW_PWR_INTF_ALL_MSK, 2133 RTW_PWR_ADDR_MAC, 2134 RTW_PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, 2135 {0x0086, 2136 RTW_PWR_CUT_ALL_MSK, 2137 RTW_PWR_INTF_SDIO_MSK, 2138 RTW_PWR_ADDR_SDIO, 2139 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2140 {0x0086, 2141 RTW_PWR_CUT_ALL_MSK, 2142 RTW_PWR_INTF_SDIO_MSK, 2143 RTW_PWR_ADDR_SDIO, 2144 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 2145 {0x004A, 2146 RTW_PWR_CUT_ALL_MSK, 2147 RTW_PWR_INTF_USB_MSK, 2148 RTW_PWR_ADDR_MAC, 2149 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2150 {0x0005, 2151 RTW_PWR_CUT_ALL_MSK, 2152 RTW_PWR_INTF_ALL_MSK, 2153 RTW_PWR_ADDR_MAC, 2154 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, 2155 {0x0023, 2156 RTW_PWR_CUT_ALL_MSK, 2157 RTW_PWR_INTF_SDIO_MSK, 2158 RTW_PWR_ADDR_MAC, 2159 RTW_PWR_CMD_WRITE, BIT(4), 0}, 2160 {0x0301, 2161 RTW_PWR_CUT_ALL_MSK, 2162 RTW_PWR_INTF_PCI_MSK, 2163 RTW_PWR_ADDR_MAC, 2164 RTW_PWR_CMD_WRITE, 0xFF, 0}, 2165 {0xFFFF, 2166 RTW_PWR_CUT_ALL_MSK, 2167 RTW_PWR_INTF_ALL_MSK, 2168 0, 2169 RTW_PWR_CMD_END, 0, 0}, 2170 }; 2171 2172 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8723d[] = { 2173 {0x0020, 2174 RTW_PWR_CUT_ALL_MSK, 2175 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2176 RTW_PWR_ADDR_MAC, 2177 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2178 {0x0001, 2179 RTW_PWR_CUT_ALL_MSK, 2180 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2181 RTW_PWR_ADDR_MAC, 2182 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 2183 {0x0000, 2184 RTW_PWR_CUT_ALL_MSK, 2185 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2186 RTW_PWR_ADDR_MAC, 2187 RTW_PWR_CMD_WRITE, BIT(5), 0}, 2188 {0x0005, 2189 RTW_PWR_CUT_ALL_MSK, 2190 RTW_PWR_INTF_ALL_MSK, 2191 RTW_PWR_ADDR_MAC, 2192 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 2193 {0x0075, 2194 RTW_PWR_CUT_ALL_MSK, 2195 RTW_PWR_INTF_PCI_MSK, 2196 RTW_PWR_ADDR_MAC, 2197 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2198 {0x0006, 2199 RTW_PWR_CUT_ALL_MSK, 2200 RTW_PWR_INTF_ALL_MSK, 2201 RTW_PWR_ADDR_MAC, 2202 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 2203 {0x0075, 2204 RTW_PWR_CUT_ALL_MSK, 2205 RTW_PWR_INTF_PCI_MSK, 2206 RTW_PWR_ADDR_MAC, 2207 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2208 {0x0006, 2209 RTW_PWR_CUT_ALL_MSK, 2210 RTW_PWR_INTF_ALL_MSK, 2211 RTW_PWR_ADDR_MAC, 2212 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2213 {0x0005, 2214 RTW_PWR_CUT_ALL_MSK, 2215 RTW_PWR_INTF_ALL_MSK, 2216 RTW_PWR_ADDR_MAC, 2217 RTW_PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0}, 2218 {0x0005, 2219 RTW_PWR_CUT_ALL_MSK, 2220 RTW_PWR_INTF_ALL_MSK, 2221 RTW_PWR_ADDR_MAC, 2222 RTW_PWR_CMD_WRITE, BIT(7), 0}, 2223 {0x0005, 2224 RTW_PWR_CUT_ALL_MSK, 2225 RTW_PWR_INTF_ALL_MSK, 2226 RTW_PWR_ADDR_MAC, 2227 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 2228 {0x0005, 2229 RTW_PWR_CUT_ALL_MSK, 2230 RTW_PWR_INTF_ALL_MSK, 2231 RTW_PWR_ADDR_MAC, 2232 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2233 {0x0005, 2234 RTW_PWR_CUT_ALL_MSK, 2235 RTW_PWR_INTF_ALL_MSK, 2236 RTW_PWR_ADDR_MAC, 2237 RTW_PWR_CMD_POLLING, BIT(0), 0}, 2238 {0x0010, 2239 RTW_PWR_CUT_ALL_MSK, 2240 RTW_PWR_INTF_ALL_MSK, 2241 RTW_PWR_ADDR_MAC, 2242 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 2243 {0x0049, 2244 RTW_PWR_CUT_ALL_MSK, 2245 RTW_PWR_INTF_ALL_MSK, 2246 RTW_PWR_ADDR_MAC, 2247 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 2248 {0x0063, 2249 RTW_PWR_CUT_ALL_MSK, 2250 RTW_PWR_INTF_ALL_MSK, 2251 RTW_PWR_ADDR_MAC, 2252 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 2253 {0x0062, 2254 RTW_PWR_CUT_ALL_MSK, 2255 RTW_PWR_INTF_ALL_MSK, 2256 RTW_PWR_ADDR_MAC, 2257 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2258 {0x0058, 2259 RTW_PWR_CUT_ALL_MSK, 2260 RTW_PWR_INTF_ALL_MSK, 2261 RTW_PWR_ADDR_MAC, 2262 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2263 {0x005A, 2264 RTW_PWR_CUT_ALL_MSK, 2265 RTW_PWR_INTF_ALL_MSK, 2266 RTW_PWR_ADDR_MAC, 2267 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 2268 {0x0068, 2269 RTW_PWR_CUT_TEST_MSK, 2270 RTW_PWR_INTF_ALL_MSK, 2271 RTW_PWR_ADDR_MAC, 2272 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 2273 {0x0069, 2274 RTW_PWR_CUT_ALL_MSK, 2275 RTW_PWR_INTF_ALL_MSK, 2276 RTW_PWR_ADDR_MAC, 2277 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 2278 {0x001f, 2279 RTW_PWR_CUT_ALL_MSK, 2280 RTW_PWR_INTF_ALL_MSK, 2281 RTW_PWR_ADDR_MAC, 2282 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 2283 {0x0077, 2284 RTW_PWR_CUT_ALL_MSK, 2285 RTW_PWR_INTF_ALL_MSK, 2286 RTW_PWR_ADDR_MAC, 2287 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 2288 {0x001f, 2289 RTW_PWR_CUT_ALL_MSK, 2290 RTW_PWR_INTF_ALL_MSK, 2291 RTW_PWR_ADDR_MAC, 2292 RTW_PWR_CMD_WRITE, 0xFF, 0x07}, 2293 {0x0077, 2294 RTW_PWR_CUT_ALL_MSK, 2295 RTW_PWR_INTF_ALL_MSK, 2296 RTW_PWR_ADDR_MAC, 2297 RTW_PWR_CMD_WRITE, 0xFF, 0x07}, 2298 {0xFFFF, 2299 RTW_PWR_CUT_ALL_MSK, 2300 RTW_PWR_INTF_ALL_MSK, 2301 0, 2302 RTW_PWR_CMD_END, 0, 0}, 2303 }; 2304 2305 static const struct rtw_pwr_seq_cmd *card_enable_flow_8723d[] = { 2306 trans_carddis_to_cardemu_8723d, 2307 trans_cardemu_to_act_8723d, 2308 NULL 2309 }; 2310 2311 static const struct rtw_pwr_seq_cmd trans_act_to_lps_8723d[] = { 2312 {0x0301, 2313 RTW_PWR_CUT_ALL_MSK, 2314 RTW_PWR_INTF_PCI_MSK, 2315 RTW_PWR_ADDR_MAC, 2316 RTW_PWR_CMD_WRITE, 0xFF, 0xFF}, 2317 {0x0522, 2318 RTW_PWR_CUT_ALL_MSK, 2319 RTW_PWR_INTF_ALL_MSK, 2320 RTW_PWR_ADDR_MAC, 2321 RTW_PWR_CMD_WRITE, 0xFF, 0xFF}, 2322 {0x05F8, 2323 RTW_PWR_CUT_ALL_MSK, 2324 RTW_PWR_INTF_ALL_MSK, 2325 RTW_PWR_ADDR_MAC, 2326 RTW_PWR_CMD_POLLING, 0xFF, 0}, 2327 {0x05F9, 2328 RTW_PWR_CUT_ALL_MSK, 2329 RTW_PWR_INTF_ALL_MSK, 2330 RTW_PWR_ADDR_MAC, 2331 RTW_PWR_CMD_POLLING, 0xFF, 0}, 2332 {0x05FA, 2333 RTW_PWR_CUT_ALL_MSK, 2334 RTW_PWR_INTF_ALL_MSK, 2335 RTW_PWR_ADDR_MAC, 2336 RTW_PWR_CMD_POLLING, 0xFF, 0}, 2337 {0x05FB, 2338 RTW_PWR_CUT_ALL_MSK, 2339 RTW_PWR_INTF_ALL_MSK, 2340 RTW_PWR_ADDR_MAC, 2341 RTW_PWR_CMD_POLLING, 0xFF, 0}, 2342 {0x0002, 2343 RTW_PWR_CUT_ALL_MSK, 2344 RTW_PWR_INTF_ALL_MSK, 2345 RTW_PWR_ADDR_MAC, 2346 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2347 {0x0002, 2348 RTW_PWR_CUT_ALL_MSK, 2349 RTW_PWR_INTF_ALL_MSK, 2350 RTW_PWR_ADDR_MAC, 2351 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US}, 2352 {0x0002, 2353 RTW_PWR_CUT_ALL_MSK, 2354 RTW_PWR_INTF_ALL_MSK, 2355 RTW_PWR_ADDR_MAC, 2356 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2357 {0x0100, 2358 RTW_PWR_CUT_ALL_MSK, 2359 RTW_PWR_INTF_ALL_MSK, 2360 RTW_PWR_ADDR_MAC, 2361 RTW_PWR_CMD_WRITE, 0xFF, 0x03}, 2362 {0x0101, 2363 RTW_PWR_CUT_ALL_MSK, 2364 RTW_PWR_INTF_ALL_MSK, 2365 RTW_PWR_ADDR_MAC, 2366 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2367 {0x0093, 2368 RTW_PWR_CUT_ALL_MSK, 2369 RTW_PWR_INTF_SDIO_MSK, 2370 RTW_PWR_ADDR_MAC, 2371 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 2372 {0x0553, 2373 RTW_PWR_CUT_ALL_MSK, 2374 RTW_PWR_INTF_ALL_MSK, 2375 RTW_PWR_ADDR_MAC, 2376 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 2377 {0xFFFF, 2378 RTW_PWR_CUT_ALL_MSK, 2379 RTW_PWR_INTF_ALL_MSK, 2380 0, 2381 RTW_PWR_CMD_END, 0, 0}, 2382 }; 2383 2384 static const struct rtw_pwr_seq_cmd trans_act_to_pre_carddis_8723d[] = { 2385 {0x0003, 2386 RTW_PWR_CUT_ALL_MSK, 2387 RTW_PWR_INTF_ALL_MSK, 2388 RTW_PWR_ADDR_MAC, 2389 RTW_PWR_CMD_WRITE, BIT(2), 0}, 2390 {0x0080, 2391 RTW_PWR_CUT_ALL_MSK, 2392 RTW_PWR_INTF_ALL_MSK, 2393 RTW_PWR_ADDR_MAC, 2394 RTW_PWR_CMD_WRITE, 0xFF, 0}, 2395 {0xFFFF, 2396 RTW_PWR_CUT_ALL_MSK, 2397 RTW_PWR_INTF_ALL_MSK, 2398 0, 2399 RTW_PWR_CMD_END, 0, 0}, 2400 }; 2401 2402 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8723d[] = { 2403 {0x0002, 2404 RTW_PWR_CUT_ALL_MSK, 2405 RTW_PWR_INTF_ALL_MSK, 2406 RTW_PWR_ADDR_MAC, 2407 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2408 {0x0049, 2409 RTW_PWR_CUT_ALL_MSK, 2410 RTW_PWR_INTF_ALL_MSK, 2411 RTW_PWR_ADDR_MAC, 2412 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2413 {0x0006, 2414 RTW_PWR_CUT_ALL_MSK, 2415 RTW_PWR_INTF_ALL_MSK, 2416 RTW_PWR_ADDR_MAC, 2417 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2418 {0x0005, 2419 RTW_PWR_CUT_ALL_MSK, 2420 RTW_PWR_INTF_ALL_MSK, 2421 RTW_PWR_ADDR_MAC, 2422 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 2423 {0x0005, 2424 RTW_PWR_CUT_ALL_MSK, 2425 RTW_PWR_INTF_ALL_MSK, 2426 RTW_PWR_ADDR_MAC, 2427 RTW_PWR_CMD_POLLING, BIT(1), 0}, 2428 {0x0010, 2429 RTW_PWR_CUT_ALL_MSK, 2430 RTW_PWR_INTF_ALL_MSK, 2431 RTW_PWR_ADDR_MAC, 2432 RTW_PWR_CMD_WRITE, BIT(6), 0}, 2433 {0x0000, 2434 RTW_PWR_CUT_ALL_MSK, 2435 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2436 RTW_PWR_ADDR_MAC, 2437 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 2438 {0x0020, 2439 RTW_PWR_CUT_ALL_MSK, 2440 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2441 RTW_PWR_ADDR_MAC, 2442 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2443 {0xFFFF, 2444 RTW_PWR_CUT_ALL_MSK, 2445 RTW_PWR_INTF_ALL_MSK, 2446 0, 2447 RTW_PWR_CMD_END, 0, 0}, 2448 }; 2449 2450 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8723d[] = { 2451 {0x0007, 2452 RTW_PWR_CUT_ALL_MSK, 2453 RTW_PWR_INTF_SDIO_MSK, 2454 RTW_PWR_ADDR_MAC, 2455 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 2456 {0x0005, 2457 RTW_PWR_CUT_ALL_MSK, 2458 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2459 RTW_PWR_ADDR_MAC, 2460 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 2461 {0x0005, 2462 RTW_PWR_CUT_ALL_MSK, 2463 RTW_PWR_INTF_PCI_MSK, 2464 RTW_PWR_ADDR_MAC, 2465 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 2466 {0x0005, 2467 RTW_PWR_CUT_ALL_MSK, 2468 RTW_PWR_INTF_PCI_MSK, 2469 RTW_PWR_ADDR_MAC, 2470 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, 2471 {0x004A, 2472 RTW_PWR_CUT_ALL_MSK, 2473 RTW_PWR_INTF_USB_MSK, 2474 RTW_PWR_ADDR_MAC, 2475 RTW_PWR_CMD_WRITE, BIT(0), 1}, 2476 {0x0023, 2477 RTW_PWR_CUT_ALL_MSK, 2478 RTW_PWR_INTF_SDIO_MSK, 2479 RTW_PWR_ADDR_MAC, 2480 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 2481 {0x0086, 2482 RTW_PWR_CUT_ALL_MSK, 2483 RTW_PWR_INTF_SDIO_MSK, 2484 RTW_PWR_ADDR_SDIO, 2485 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2486 {0x0086, 2487 RTW_PWR_CUT_ALL_MSK, 2488 RTW_PWR_INTF_SDIO_MSK, 2489 RTW_PWR_ADDR_SDIO, 2490 RTW_PWR_CMD_POLLING, BIT(1), 0}, 2491 {0xFFFF, 2492 RTW_PWR_CUT_ALL_MSK, 2493 RTW_PWR_INTF_ALL_MSK, 2494 0, 2495 RTW_PWR_CMD_END, 0, 0}, 2496 }; 2497 2498 static const struct rtw_pwr_seq_cmd trans_act_to_post_carddis_8723d[] = { 2499 {0x001D, 2500 RTW_PWR_CUT_ALL_MSK, 2501 RTW_PWR_INTF_ALL_MSK, 2502 RTW_PWR_ADDR_MAC, 2503 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2504 {0x001D, 2505 RTW_PWR_CUT_ALL_MSK, 2506 RTW_PWR_INTF_ALL_MSK, 2507 RTW_PWR_ADDR_MAC, 2508 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2509 {0x001C, 2510 RTW_PWR_CUT_ALL_MSK, 2511 RTW_PWR_INTF_ALL_MSK, 2512 RTW_PWR_ADDR_MAC, 2513 RTW_PWR_CMD_WRITE, 0xFF, 0x0E}, 2514 {0xFFFF, 2515 RTW_PWR_CUT_ALL_MSK, 2516 RTW_PWR_INTF_ALL_MSK, 2517 0, 2518 RTW_PWR_CMD_END, 0, 0}, 2519 }; 2520 2521 static const struct rtw_pwr_seq_cmd *card_disable_flow_8723d[] = { 2522 trans_act_to_lps_8723d, 2523 trans_act_to_pre_carddis_8723d, 2524 trans_act_to_cardemu_8723d, 2525 trans_cardemu_to_carddis_8723d, 2526 trans_act_to_post_carddis_8723d, 2527 NULL 2528 }; 2529 2530 static const struct rtw_page_table page_table_8723d[] = { 2531 {12, 2, 2, 0, 1}, 2532 {12, 2, 2, 0, 1}, 2533 {12, 2, 2, 0, 1}, 2534 {12, 2, 2, 0, 1}, 2535 {12, 2, 2, 0, 1}, 2536 }; 2537 2538 static const struct rtw_rqpn rqpn_table_8723d[] = { 2539 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2540 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2541 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2542 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2543 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2544 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2545 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2546 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 2547 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2548 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2549 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2550 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2551 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2552 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2553 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2554 }; 2555 2556 static const struct rtw_prioq_addrs prioq_addrs_8723d = { 2557 .prio[RTW_DMA_MAPPING_EXTRA] = { 2558 .rsvd = REG_RQPN_NPQ + 2, .avail = REG_RQPN_NPQ + 3, 2559 }, 2560 .prio[RTW_DMA_MAPPING_LOW] = { 2561 .rsvd = REG_RQPN + 1, .avail = REG_FIFOPAGE_CTRL_2 + 1, 2562 }, 2563 .prio[RTW_DMA_MAPPING_NORMAL] = { 2564 .rsvd = REG_RQPN_NPQ, .avail = REG_RQPN_NPQ + 1, 2565 }, 2566 .prio[RTW_DMA_MAPPING_HIGH] = { 2567 .rsvd = REG_RQPN, .avail = REG_FIFOPAGE_CTRL_2, 2568 }, 2569 .wsize = false, 2570 }; 2571 2572 static const struct rtw_intf_phy_para pcie_gen1_param_8723d[] = { 2573 {0x0008, 0x4a22, 2574 RTW_IP_SEL_PHY, 2575 RTW_INTF_PHY_CUT_ALL, 2576 RTW_INTF_PHY_PLATFORM_ALL}, 2577 {0x0009, 0x1000, 2578 RTW_IP_SEL_PHY, 2579 ~(RTW_INTF_PHY_CUT_A | RTW_INTF_PHY_CUT_B), 2580 RTW_INTF_PHY_PLATFORM_ALL}, 2581 {0xFFFF, 0x0000, 2582 RTW_IP_SEL_PHY, 2583 RTW_INTF_PHY_CUT_ALL, 2584 RTW_INTF_PHY_PLATFORM_ALL}, 2585 }; 2586 2587 static const struct rtw_intf_phy_para_table phy_para_table_8723d = { 2588 .gen1_para = pcie_gen1_param_8723d, 2589 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8723d), 2590 }; 2591 2592 static const struct rtw_hw_reg rtw8723d_dig[] = { 2593 [0] = { .addr = 0xc50, .mask = 0x7f }, 2594 [1] = { .addr = 0xc50, .mask = 0x7f }, 2595 }; 2596 2597 static const struct rtw_hw_reg rtw8723d_dig_cck[] = { 2598 [0] = { .addr = 0xa0c, .mask = 0x3f00 }, 2599 }; 2600 2601 static const struct rtw_rf_sipi_addr rtw8723d_rf_sipi_addr[] = { 2602 [RF_PATH_A] = { .hssi_1 = 0x820, .lssi_read = 0x8a0, 2603 .hssi_2 = 0x824, .lssi_read_pi = 0x8b8}, 2604 [RF_PATH_B] = { .hssi_1 = 0x828, .lssi_read = 0x8a4, 2605 .hssi_2 = 0x82c, .lssi_read_pi = 0x8bc}, 2606 }; 2607 2608 static const struct rtw_ltecoex_addr rtw8723d_ltecoex_addr = { 2609 .ctrl = REG_LTECOEX_CTRL, 2610 .wdata = REG_LTECOEX_WRITE_DATA, 2611 .rdata = REG_LTECOEX_READ_DATA, 2612 }; 2613 2614 static const struct rtw_rfe_def rtw8723d_rfe_defs[] = { 2615 [0] = { .phy_pg_tbl = &rtw8723d_bb_pg_tbl, 2616 .txpwr_lmt_tbl = &rtw8723d_txpwr_lmt_tbl,}, 2617 }; 2618 2619 static const u8 rtw8723d_pwrtrk_2gb_n[] = { 2620 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 2621 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10 2622 }; 2623 2624 static const u8 rtw8723d_pwrtrk_2gb_p[] = { 2625 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 2626 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10 2627 }; 2628 2629 static const u8 rtw8723d_pwrtrk_2ga_n[] = { 2630 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 2631 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10 2632 }; 2633 2634 static const u8 rtw8723d_pwrtrk_2ga_p[] = { 2635 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 2636 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10 2637 }; 2638 2639 static const u8 rtw8723d_pwrtrk_2g_cck_b_n[] = { 2640 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 2641 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11 2642 }; 2643 2644 static const u8 rtw8723d_pwrtrk_2g_cck_b_p[] = { 2645 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 2646 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11 2647 }; 2648 2649 static const u8 rtw8723d_pwrtrk_2g_cck_a_n[] = { 2650 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 2651 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11 2652 }; 2653 2654 static const u8 rtw8723d_pwrtrk_2g_cck_a_p[] = { 2655 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 2656 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11 2657 }; 2658 2659 static const s8 rtw8723d_pwrtrk_xtal_n[] = { 2660 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2661 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 2662 }; 2663 2664 static const s8 rtw8723d_pwrtrk_xtal_p[] = { 2665 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2666 0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16 2667 }; 2668 2669 static const struct rtw_pwr_track_tbl rtw8723d_rtw_pwr_track_tbl = { 2670 .pwrtrk_2gb_n = rtw8723d_pwrtrk_2gb_n, 2671 .pwrtrk_2gb_p = rtw8723d_pwrtrk_2gb_p, 2672 .pwrtrk_2ga_n = rtw8723d_pwrtrk_2ga_n, 2673 .pwrtrk_2ga_p = rtw8723d_pwrtrk_2ga_p, 2674 .pwrtrk_2g_cckb_n = rtw8723d_pwrtrk_2g_cck_b_n, 2675 .pwrtrk_2g_cckb_p = rtw8723d_pwrtrk_2g_cck_b_p, 2676 .pwrtrk_2g_ccka_n = rtw8723d_pwrtrk_2g_cck_a_n, 2677 .pwrtrk_2g_ccka_p = rtw8723d_pwrtrk_2g_cck_a_p, 2678 .pwrtrk_xtal_p = rtw8723d_pwrtrk_xtal_p, 2679 .pwrtrk_xtal_n = rtw8723d_pwrtrk_xtal_n, 2680 }; 2681 2682 static const struct rtw_reg_domain coex_info_hw_regs_8723d[] = { 2683 {0x948, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2684 {0x67, BIT(7), RTW_REG_DOMAIN_MAC8}, 2685 {0, 0, RTW_REG_DOMAIN_NL}, 2686 {0x964, BIT(1), RTW_REG_DOMAIN_MAC8}, 2687 {0x864, BIT(0), RTW_REG_DOMAIN_MAC8}, 2688 {0xab7, BIT(5), RTW_REG_DOMAIN_MAC8}, 2689 {0xa01, BIT(7), RTW_REG_DOMAIN_MAC8}, 2690 {0, 0, RTW_REG_DOMAIN_NL}, 2691 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2692 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2693 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 2694 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2695 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 2696 {0, 0, RTW_REG_DOMAIN_NL}, 2697 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 2698 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 2699 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2700 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2701 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 2702 }; 2703 2704 const struct rtw_chip_info rtw8723d_hw_spec = { 2705 .ops = &rtw8723d_ops, 2706 .id = RTW_CHIP_TYPE_8723D, 2707 .fw_name = "rtw88/rtw8723d_fw.bin", 2708 .wlan_cpu = RTW_WCPU_11N, 2709 .tx_pkt_desc_sz = 40, 2710 .tx_buf_desc_sz = 16, 2711 .rx_pkt_desc_sz = 24, 2712 .rx_buf_desc_sz = 8, 2713 .phy_efuse_size = 512, 2714 .log_efuse_size = 512, 2715 .ptct_efuse_size = 96 + 1, 2716 .txff_size = 32768, 2717 .rxff_size = 16384, 2718 .txgi_factor = 1, 2719 .is_pwr_by_rate_dec = true, 2720 .max_power_index = 0x3f, 2721 .csi_buf_pg_num = 0, 2722 .band = RTW_BAND_2G, 2723 .page_size = 128, 2724 .dig_min = 0x20, 2725 .ht_supported = true, 2726 .vht_supported = false, 2727 .lps_deep_mode_supported = 0, 2728 .sys_func_en = 0xFD, 2729 .pwr_on_seq = card_enable_flow_8723d, 2730 .pwr_off_seq = card_disable_flow_8723d, 2731 .page_table = page_table_8723d, 2732 .rqpn_table = rqpn_table_8723d, 2733 .prioq_addrs = &prioq_addrs_8723d, 2734 .intf_table = &phy_para_table_8723d, 2735 .dig = rtw8723d_dig, 2736 .dig_cck = rtw8723d_dig_cck, 2737 .rf_sipi_addr = {0x840, 0x844}, 2738 .rf_sipi_read_addr = rtw8723d_rf_sipi_addr, 2739 .fix_rf_phy_num = 2, 2740 .ltecoex_addr = &rtw8723d_ltecoex_addr, 2741 .mac_tbl = &rtw8723d_mac_tbl, 2742 .agc_tbl = &rtw8723d_agc_tbl, 2743 .bb_tbl = &rtw8723d_bb_tbl, 2744 .rf_tbl = {&rtw8723d_rf_a_tbl}, 2745 .rfe_defs = rtw8723d_rfe_defs, 2746 .rfe_defs_size = ARRAY_SIZE(rtw8723d_rfe_defs), 2747 .rx_ldpc = false, 2748 .pwr_track_tbl = &rtw8723d_rtw_pwr_track_tbl, 2749 .iqk_threshold = 8, 2750 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 2751 2752 .coex_para_ver = 0x2007022f, 2753 .bt_desired_ver = 0x2f, 2754 .scbd_support = true, 2755 .new_scbd10_def = true, 2756 .ble_hid_profile_support = false, 2757 .wl_mimo_ps_support = false, 2758 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2759 .bt_rssi_type = COEX_BTRSSI_RATIO, 2760 .ant_isolation = 15, 2761 .rssi_tolerance = 2, 2762 .wl_rssi_step = wl_rssi_step_8723d, 2763 .bt_rssi_step = bt_rssi_step_8723d, 2764 .table_sant_num = ARRAY_SIZE(table_sant_8723d), 2765 .table_sant = table_sant_8723d, 2766 .table_nsant_num = ARRAY_SIZE(table_nsant_8723d), 2767 .table_nsant = table_nsant_8723d, 2768 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8723d), 2769 .tdma_sant = tdma_sant_8723d, 2770 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8723d), 2771 .tdma_nsant = tdma_nsant_8723d, 2772 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8723d), 2773 .wl_rf_para_tx = rf_para_tx_8723d, 2774 .wl_rf_para_rx = rf_para_rx_8723d, 2775 .bt_afh_span_bw20 = 0x20, 2776 .bt_afh_span_bw40 = 0x30, 2777 .afh_5g_num = ARRAY_SIZE(afh_5g_8723d), 2778 .afh_5g = afh_5g_8723d, 2779 .btg_reg = &btg_reg_8723d, 2780 2781 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8723d), 2782 .coex_info_hw_regs = coex_info_hw_regs_8723d, 2783 }; 2784 EXPORT_SYMBOL(rtw8723d_hw_spec); 2785 2786 MODULE_FIRMWARE("rtw88/rtw8723d_fw.bin"); 2787 2788 MODULE_AUTHOR("Realtek Corporation"); 2789 MODULE_DESCRIPTION("Realtek 802.11n wireless 8723d driver"); 2790 MODULE_LICENSE("Dual BSD/GPL");
Cache object: 021626be6377f7edb43d43c306b1cd69
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