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sys/contrib/dev/rtw89/core.h
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1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 #if defined(__FreeBSD__) 15 #include <linux/seq_file.h> 16 #include <linux/lockdep.h> 17 #include <linux/interrupt.h> 18 #include <linux/pm.h> 19 #endif 20 21 struct rtw89_dev; 22 struct rtw89_pci_info; 23 24 extern const struct ieee80211_ops rtw89_ops; 25 26 #define MASKBYTE0 0xff 27 #define MASKBYTE1 0xff00 28 #define MASKBYTE2 0xff0000 29 #define MASKBYTE3 0xff000000 30 #define MASKBYTE4 0xff00000000ULL 31 #define MASKHWORD 0xffff0000 32 #define MASKLWORD 0x0000ffff 33 #define MASKDWORD 0xffffffff 34 #define RFREG_MASK 0xfffff 35 #define INV_RF_DATA 0xffffffff 36 37 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 38 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 39 #define CFO_TRACK_MAX_USER 64 40 #define MAX_RSSI 110 41 #define RSSI_FACTOR 1 42 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 43 44 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 45 #define RTW89_HTC_VARIANT_HE 3 46 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 47 #define RTW89_HTC_VARIANT_HE_CID_OM 1 48 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 49 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 50 51 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 52 enum htc_om_channel_width { 53 HTC_OM_CHANNEL_WIDTH_20 = 0, 54 HTC_OM_CHANNEL_WIDTH_40 = 1, 55 HTC_OM_CHANNEL_WIDTH_80 = 2, 56 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 57 }; 58 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 59 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 60 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 61 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 62 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 63 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 64 65 #define RTW89_TF_PAD GENMASK(11, 0) 66 #define RTW89_TF_BASIC_USER_INFO_SZ 6 67 68 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 69 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 70 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 71 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 72 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 73 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 74 75 enum rtw89_subband { 76 RTW89_CH_2G = 0, 77 RTW89_CH_5G_BAND_1 = 1, 78 /* RTW89_CH_5G_BAND_2 = 2, unused */ 79 RTW89_CH_5G_BAND_3 = 3, 80 RTW89_CH_5G_BAND_4 = 4, 81 82 RTW89_CH_6G_BAND_IDX0, /* Low */ 83 RTW89_CH_6G_BAND_IDX1, /* Low */ 84 RTW89_CH_6G_BAND_IDX2, /* Mid */ 85 RTW89_CH_6G_BAND_IDX3, /* Mid */ 86 RTW89_CH_6G_BAND_IDX4, /* High */ 87 RTW89_CH_6G_BAND_IDX5, /* High */ 88 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 89 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 90 91 RTW89_SUBBAND_NR, 92 }; 93 94 enum rtw89_gain_offset { 95 RTW89_GAIN_OFFSET_2G_CCK, 96 RTW89_GAIN_OFFSET_2G_OFDM, 97 RTW89_GAIN_OFFSET_5G_LOW, 98 RTW89_GAIN_OFFSET_5G_MID, 99 RTW89_GAIN_OFFSET_5G_HIGH, 100 101 RTW89_GAIN_OFFSET_NR, 102 }; 103 104 enum rtw89_hci_type { 105 RTW89_HCI_TYPE_PCIE, 106 RTW89_HCI_TYPE_USB, 107 RTW89_HCI_TYPE_SDIO, 108 }; 109 110 enum rtw89_core_chip_id { 111 RTL8852A, 112 RTL8852B, 113 RTL8852C, 114 }; 115 116 enum rtw89_cv { 117 CHIP_CAV, 118 CHIP_CBV, 119 CHIP_CCV, 120 CHIP_CDV, 121 CHIP_CEV, 122 CHIP_CFV, 123 CHIP_CV_MAX, 124 CHIP_CV_INVALID = CHIP_CV_MAX, 125 }; 126 127 enum rtw89_core_tx_type { 128 RTW89_CORE_TX_TYPE_DATA, 129 RTW89_CORE_TX_TYPE_MGMT, 130 RTW89_CORE_TX_TYPE_FWCMD, 131 }; 132 133 enum rtw89_core_rx_type { 134 RTW89_CORE_RX_TYPE_WIFI = 0, 135 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 136 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 137 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 138 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 139 RTW89_CORE_RX_TYPE_SS2FW = 5, 140 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 141 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 142 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 143 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 144 RTW89_CORE_RX_TYPE_C2H = 10, 145 RTW89_CORE_RX_TYPE_CSI = 11, 146 RTW89_CORE_RX_TYPE_CQI = 12, 147 RTW89_CORE_RX_TYPE_H2C = 13, 148 RTW89_CORE_RX_TYPE_FWDL = 14, 149 }; 150 151 enum rtw89_txq_flags { 152 RTW89_TXQ_F_AMPDU = 0, 153 RTW89_TXQ_F_BLOCK_BA = 1, 154 RTW89_TXQ_F_FORBID_BA = 2, 155 }; 156 157 enum rtw89_net_type { 158 RTW89_NET_TYPE_NO_LINK = 0, 159 RTW89_NET_TYPE_AD_HOC = 1, 160 RTW89_NET_TYPE_INFRA = 2, 161 RTW89_NET_TYPE_AP_MODE = 3, 162 }; 163 164 enum rtw89_wifi_role { 165 RTW89_WIFI_ROLE_NONE, 166 RTW89_WIFI_ROLE_STATION, 167 RTW89_WIFI_ROLE_AP, 168 RTW89_WIFI_ROLE_AP_VLAN, 169 RTW89_WIFI_ROLE_ADHOC, 170 RTW89_WIFI_ROLE_ADHOC_MASTER, 171 RTW89_WIFI_ROLE_MESH_POINT, 172 RTW89_WIFI_ROLE_MONITOR, 173 RTW89_WIFI_ROLE_P2P_DEVICE, 174 RTW89_WIFI_ROLE_P2P_CLIENT, 175 RTW89_WIFI_ROLE_P2P_GO, 176 RTW89_WIFI_ROLE_NAN, 177 RTW89_WIFI_ROLE_MLME_MAX 178 }; 179 180 enum rtw89_upd_mode { 181 RTW89_ROLE_CREATE, 182 RTW89_ROLE_REMOVE, 183 RTW89_ROLE_TYPE_CHANGE, 184 RTW89_ROLE_INFO_CHANGE, 185 RTW89_ROLE_CON_DISCONN 186 }; 187 188 enum rtw89_self_role { 189 RTW89_SELF_ROLE_CLIENT, 190 RTW89_SELF_ROLE_AP, 191 RTW89_SELF_ROLE_AP_CLIENT 192 }; 193 194 enum rtw89_msk_sO_el { 195 RTW89_NO_MSK, 196 RTW89_SMA, 197 RTW89_TMA, 198 RTW89_BSSID 199 }; 200 201 enum rtw89_sch_tx_sel { 202 RTW89_SCH_TX_SEL_ALL, 203 RTW89_SCH_TX_SEL_HIQ, 204 RTW89_SCH_TX_SEL_MG0, 205 RTW89_SCH_TX_SEL_MACID, 206 }; 207 208 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 209 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 210 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 211 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 212 */ 213 enum rtw89_add_cam_sec_mode { 214 RTW89_ADDR_CAM_SEC_NONE = 0, 215 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 216 RTW89_ADDR_CAM_SEC_NORMAL = 2, 217 RTW89_ADDR_CAM_SEC_4GROUP = 3, 218 }; 219 220 enum rtw89_sec_key_type { 221 RTW89_SEC_KEY_TYPE_NONE = 0, 222 RTW89_SEC_KEY_TYPE_WEP40 = 1, 223 RTW89_SEC_KEY_TYPE_WEP104 = 2, 224 RTW89_SEC_KEY_TYPE_TKIP = 3, 225 RTW89_SEC_KEY_TYPE_WAPI = 4, 226 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 227 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 228 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 229 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 230 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 231 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 232 }; 233 234 enum rtw89_port { 235 RTW89_PORT_0 = 0, 236 RTW89_PORT_1 = 1, 237 RTW89_PORT_2 = 2, 238 RTW89_PORT_3 = 3, 239 RTW89_PORT_4 = 4, 240 RTW89_PORT_NUM 241 }; 242 243 enum rtw89_band { 244 RTW89_BAND_2G = 0, 245 RTW89_BAND_5G = 1, 246 RTW89_BAND_6G = 2, 247 RTW89_BAND_MAX, 248 }; 249 250 enum rtw89_hw_rate { 251 RTW89_HW_RATE_CCK1 = 0x0, 252 RTW89_HW_RATE_CCK2 = 0x1, 253 RTW89_HW_RATE_CCK5_5 = 0x2, 254 RTW89_HW_RATE_CCK11 = 0x3, 255 RTW89_HW_RATE_OFDM6 = 0x4, 256 RTW89_HW_RATE_OFDM9 = 0x5, 257 RTW89_HW_RATE_OFDM12 = 0x6, 258 RTW89_HW_RATE_OFDM18 = 0x7, 259 RTW89_HW_RATE_OFDM24 = 0x8, 260 RTW89_HW_RATE_OFDM36 = 0x9, 261 RTW89_HW_RATE_OFDM48 = 0xA, 262 RTW89_HW_RATE_OFDM54 = 0xB, 263 RTW89_HW_RATE_MCS0 = 0x80, 264 RTW89_HW_RATE_MCS1 = 0x81, 265 RTW89_HW_RATE_MCS2 = 0x82, 266 RTW89_HW_RATE_MCS3 = 0x83, 267 RTW89_HW_RATE_MCS4 = 0x84, 268 RTW89_HW_RATE_MCS5 = 0x85, 269 RTW89_HW_RATE_MCS6 = 0x86, 270 RTW89_HW_RATE_MCS7 = 0x87, 271 RTW89_HW_RATE_MCS8 = 0x88, 272 RTW89_HW_RATE_MCS9 = 0x89, 273 RTW89_HW_RATE_MCS10 = 0x8A, 274 RTW89_HW_RATE_MCS11 = 0x8B, 275 RTW89_HW_RATE_MCS12 = 0x8C, 276 RTW89_HW_RATE_MCS13 = 0x8D, 277 RTW89_HW_RATE_MCS14 = 0x8E, 278 RTW89_HW_RATE_MCS15 = 0x8F, 279 RTW89_HW_RATE_MCS16 = 0x90, 280 RTW89_HW_RATE_MCS17 = 0x91, 281 RTW89_HW_RATE_MCS18 = 0x92, 282 RTW89_HW_RATE_MCS19 = 0x93, 283 RTW89_HW_RATE_MCS20 = 0x94, 284 RTW89_HW_RATE_MCS21 = 0x95, 285 RTW89_HW_RATE_MCS22 = 0x96, 286 RTW89_HW_RATE_MCS23 = 0x97, 287 RTW89_HW_RATE_MCS24 = 0x98, 288 RTW89_HW_RATE_MCS25 = 0x99, 289 RTW89_HW_RATE_MCS26 = 0x9A, 290 RTW89_HW_RATE_MCS27 = 0x9B, 291 RTW89_HW_RATE_MCS28 = 0x9C, 292 RTW89_HW_RATE_MCS29 = 0x9D, 293 RTW89_HW_RATE_MCS30 = 0x9E, 294 RTW89_HW_RATE_MCS31 = 0x9F, 295 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 296 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 297 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 298 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 299 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 300 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 301 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 302 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 303 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 304 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 305 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 306 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 307 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 308 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 309 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 310 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 311 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 312 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 313 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 314 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 315 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 316 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 317 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 318 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 319 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 320 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 321 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 322 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 323 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 324 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 325 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 326 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 327 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 328 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 329 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 330 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 331 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 332 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 333 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 334 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 335 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 336 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 337 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 338 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 339 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 340 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 341 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 342 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 343 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 344 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 345 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 346 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 347 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 348 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 349 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 350 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 351 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 352 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 353 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 354 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 355 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 356 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 357 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 358 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 359 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 360 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 361 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 362 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 363 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 364 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 365 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 366 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 367 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 368 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 369 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 370 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 371 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 372 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 373 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 374 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 375 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 376 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 377 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 378 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 379 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 380 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 381 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 382 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 383 RTW89_HW_RATE_NR, 384 385 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 386 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 387 }; 388 389 /* 2G channels, 390 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 391 */ 392 #define RTW89_2G_CH_NUM 14 393 394 /* 5G channels, 395 * 36, 38, 40, 42, 44, 46, 48, 50, 396 * 52, 54, 56, 58, 60, 62, 64, 397 * 100, 102, 104, 106, 108, 110, 112, 114, 398 * 116, 118, 120, 122, 124, 126, 128, 130, 399 * 132, 134, 136, 138, 140, 142, 144, 400 * 149, 151, 153, 155, 157, 159, 161, 163, 401 * 165, 167, 169, 171, 173, 175, 177 402 */ 403 #define RTW89_5G_CH_NUM 53 404 405 /* 6G channels, 406 * 1, 3, 5, 7, 9, 11, 13, 15, 407 * 17, 19, 21, 23, 25, 27, 29, 33, 408 * 35, 37, 39, 41, 43, 45, 47, 49, 409 * 51, 53, 55, 57, 59, 61, 65, 67, 410 * 69, 71, 73, 75, 77, 79, 81, 83, 411 * 85, 87, 89, 91, 93, 97, 99, 101, 412 * 103, 105, 107, 109, 111, 113, 115, 117, 413 * 119, 121, 123, 125, 129, 131, 133, 135, 414 * 137, 139, 141, 143, 145, 147, 149, 151, 415 * 153, 155, 157, 161, 163, 165, 167, 169, 416 * 171, 173, 175, 177, 179, 181, 183, 185, 417 * 187, 189, 193, 195, 197, 199, 201, 203, 418 * 205, 207, 209, 211, 213, 215, 217, 219, 419 * 221, 225, 227, 229, 231, 233, 235, 237, 420 * 239, 241, 243, 245, 247, 249, 251, 253, 421 */ 422 #define RTW89_6G_CH_NUM 120 423 424 enum rtw89_rate_section { 425 RTW89_RS_CCK, 426 RTW89_RS_OFDM, 427 RTW89_RS_MCS, /* for HT/VHT/HE */ 428 RTW89_RS_HEDCM, 429 RTW89_RS_OFFSET, 430 RTW89_RS_MAX, 431 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 432 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 433 }; 434 435 enum rtw89_rate_max { 436 RTW89_RATE_CCK_MAX = 4, 437 RTW89_RATE_OFDM_MAX = 8, 438 RTW89_RATE_MCS_MAX = 12, 439 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ 440 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 441 }; 442 443 enum rtw89_nss { 444 RTW89_NSS_1 = 0, 445 RTW89_NSS_2 = 1, 446 /* HE DCM only support 1ss and 2ss */ 447 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, 448 RTW89_NSS_3 = 2, 449 RTW89_NSS_4 = 3, 450 RTW89_NSS_MAX, 451 }; 452 453 enum rtw89_ntx { 454 RTW89_1TX = 0, 455 RTW89_2TX = 1, 456 RTW89_NTX_NUM, 457 }; 458 459 enum rtw89_beamforming_type { 460 RTW89_NONBF = 0, 461 RTW89_BF = 1, 462 RTW89_BF_NUM, 463 }; 464 465 enum rtw89_regulation_type { 466 RTW89_WW = 0, 467 RTW89_ETSI = 1, 468 RTW89_FCC = 2, 469 RTW89_MKK = 3, 470 RTW89_NA = 4, 471 RTW89_IC = 5, 472 RTW89_KCC = 6, 473 RTW89_ACMA = 7, 474 RTW89_NCC = 8, 475 RTW89_MEXICO = 9, 476 RTW89_CHILE = 10, 477 RTW89_UKRAINE = 11, 478 RTW89_CN = 12, 479 RTW89_QATAR = 13, 480 RTW89_UK = 14, 481 RTW89_REGD_NUM, 482 }; 483 484 struct rtw89_txpwr_byrate { 485 s8 cck[RTW89_RATE_CCK_MAX]; 486 s8 ofdm[RTW89_RATE_OFDM_MAX]; 487 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; 488 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; 489 s8 offset[RTW89_RATE_OFFSET_MAX]; 490 }; 491 492 enum rtw89_bandwidth_section_num { 493 RTW89_BW20_SEC_NUM = 8, 494 RTW89_BW40_SEC_NUM = 4, 495 RTW89_BW80_SEC_NUM = 2, 496 }; 497 498 struct rtw89_txpwr_limit { 499 s8 cck_20m[RTW89_BF_NUM]; 500 s8 cck_40m[RTW89_BF_NUM]; 501 s8 ofdm[RTW89_BF_NUM]; 502 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 503 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 504 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 505 s8 mcs_160m[RTW89_BF_NUM]; 506 s8 mcs_40m_0p5[RTW89_BF_NUM]; 507 s8 mcs_40m_2p5[RTW89_BF_NUM]; 508 }; 509 510 #define RTW89_RU_SEC_NUM 8 511 512 struct rtw89_txpwr_limit_ru { 513 s8 ru26[RTW89_RU_SEC_NUM]; 514 s8 ru52[RTW89_RU_SEC_NUM]; 515 s8 ru106[RTW89_RU_SEC_NUM]; 516 }; 517 518 struct rtw89_rate_desc { 519 enum rtw89_nss nss; 520 enum rtw89_rate_section rs; 521 u8 idx; 522 }; 523 524 #define PHY_STS_HDR_LEN 8 525 #define RF_PATH_MAX 4 526 #define RTW89_MAX_PPDU_CNT 8 527 struct rtw89_rx_phy_ppdu { 528 u8 *buf; 529 u32 len; 530 u8 rssi_avg; 531 s8 rssi[RF_PATH_MAX]; 532 u8 mac_id; 533 u8 chan_idx; 534 u8 ie; 535 u16 rate; 536 bool to_self; 537 bool valid; 538 }; 539 540 enum rtw89_mac_idx { 541 RTW89_MAC_0 = 0, 542 RTW89_MAC_1 = 1, 543 }; 544 545 enum rtw89_phy_idx { 546 RTW89_PHY_0 = 0, 547 RTW89_PHY_1 = 1, 548 RTW89_PHY_MAX 549 }; 550 551 enum rtw89_sub_entity_idx { 552 RTW89_SUB_ENTITY_0 = 0, 553 554 NUM_OF_RTW89_SUB_ENTITY, 555 }; 556 557 enum rtw89_rf_path { 558 RF_PATH_A = 0, 559 RF_PATH_B = 1, 560 RF_PATH_C = 2, 561 RF_PATH_D = 3, 562 RF_PATH_AB, 563 RF_PATH_AC, 564 RF_PATH_AD, 565 RF_PATH_BC, 566 RF_PATH_BD, 567 RF_PATH_CD, 568 RF_PATH_ABC, 569 RF_PATH_ABD, 570 RF_PATH_ACD, 571 RF_PATH_BCD, 572 RF_PATH_ABCD, 573 }; 574 575 enum rtw89_rf_path_bit { 576 RF_A = BIT(0), 577 RF_B = BIT(1), 578 RF_C = BIT(2), 579 RF_D = BIT(3), 580 581 RF_AB = (RF_A | RF_B), 582 RF_AC = (RF_A | RF_C), 583 RF_AD = (RF_A | RF_D), 584 RF_BC = (RF_B | RF_C), 585 RF_BD = (RF_B | RF_D), 586 RF_CD = (RF_C | RF_D), 587 588 RF_ABC = (RF_A | RF_B | RF_C), 589 RF_ABD = (RF_A | RF_B | RF_D), 590 RF_ACD = (RF_A | RF_C | RF_D), 591 RF_BCD = (RF_B | RF_C | RF_D), 592 593 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 594 }; 595 596 enum rtw89_bandwidth { 597 RTW89_CHANNEL_WIDTH_20 = 0, 598 RTW89_CHANNEL_WIDTH_40 = 1, 599 RTW89_CHANNEL_WIDTH_80 = 2, 600 RTW89_CHANNEL_WIDTH_160 = 3, 601 RTW89_CHANNEL_WIDTH_80_80 = 4, 602 RTW89_CHANNEL_WIDTH_5 = 5, 603 RTW89_CHANNEL_WIDTH_10 = 6, 604 }; 605 606 enum rtw89_ps_mode { 607 RTW89_PS_MODE_NONE = 0, 608 RTW89_PS_MODE_RFOFF = 1, 609 RTW89_PS_MODE_CLK_GATED = 2, 610 RTW89_PS_MODE_PWR_GATED = 3, 611 }; 612 613 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 614 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 615 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 616 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 617 618 enum rtw89_ru_bandwidth { 619 RTW89_RU26 = 0, 620 RTW89_RU52 = 1, 621 RTW89_RU106 = 2, 622 RTW89_RU_NUM, 623 }; 624 625 enum rtw89_sc_offset { 626 RTW89_SC_DONT_CARE = 0, 627 RTW89_SC_20_UPPER = 1, 628 RTW89_SC_20_LOWER = 2, 629 RTW89_SC_20_UPMOST = 3, 630 RTW89_SC_20_LOWEST = 4, 631 RTW89_SC_20_UP2X = 5, 632 RTW89_SC_20_LOW2X = 6, 633 RTW89_SC_20_UP3X = 7, 634 RTW89_SC_20_LOW3X = 8, 635 RTW89_SC_40_UPPER = 9, 636 RTW89_SC_40_LOWER = 10, 637 }; 638 639 struct rtw89_chan { 640 u8 channel; 641 u8 primary_channel; 642 enum rtw89_band band_type; 643 enum rtw89_bandwidth band_width; 644 645 /* The follow-up are derived from the above. We must ensure that it 646 * is assigned correctly in rtw89_chan_create() if new one is added. 647 */ 648 u32 freq; 649 enum rtw89_subband subband_type; 650 enum rtw89_sc_offset pri_ch_idx; 651 }; 652 653 struct rtw89_chan_rcd { 654 u8 prev_primary_channel; 655 enum rtw89_band prev_band_type; 656 }; 657 658 struct rtw89_channel_help_params { 659 u32 tx_en; 660 }; 661 662 struct rtw89_port_reg { 663 u32 port_cfg; 664 u32 tbtt_prohib; 665 u32 bcn_area; 666 u32 bcn_early; 667 u32 tbtt_early; 668 u32 tbtt_agg; 669 u32 bcn_space; 670 u32 bcn_forcetx; 671 u32 bcn_err_cnt; 672 u32 bcn_err_flag; 673 u32 dtim_ctrl; 674 u32 tbtt_shift; 675 u32 bcn_cnt_tmr; 676 u32 tsftr_l; 677 u32 tsftr_h; 678 }; 679 680 struct rtw89_txwd_body { 681 __le32 dword0; 682 __le32 dword1; 683 __le32 dword2; 684 __le32 dword3; 685 __le32 dword4; 686 __le32 dword5; 687 } __packed; 688 689 struct rtw89_txwd_body_v1 { 690 __le32 dword0; 691 __le32 dword1; 692 __le32 dword2; 693 __le32 dword3; 694 __le32 dword4; 695 __le32 dword5; 696 __le32 dword6; 697 __le32 dword7; 698 } __packed; 699 700 struct rtw89_txwd_info { 701 __le32 dword0; 702 __le32 dword1; 703 __le32 dword2; 704 __le32 dword3; 705 __le32 dword4; 706 __le32 dword5; 707 } __packed; 708 709 struct rtw89_rx_desc_info { 710 u16 pkt_size; 711 u8 pkt_type; 712 u8 drv_info_size; 713 u8 shift; 714 u8 wl_hd_iv_len; 715 bool long_rxdesc; 716 bool bb_sel; 717 bool mac_info_valid; 718 u16 data_rate; 719 u8 gi_ltf; 720 u8 bw; 721 u32 free_run_cnt; 722 u8 user_id; 723 bool sr_en; 724 u8 ppdu_cnt; 725 u8 ppdu_type; 726 bool icv_err; 727 bool crc32_err; 728 bool hw_dec; 729 bool sw_dec; 730 bool addr1_match; 731 u8 frag; 732 u16 seq; 733 u8 frame_type; 734 u8 rx_pl_id; 735 bool addr_cam_valid; 736 u8 addr_cam_id; 737 u8 sec_cam_id; 738 u8 mac_id; 739 u16 offset; 740 bool ready; 741 }; 742 743 struct rtw89_rxdesc_short { 744 __le32 dword0; 745 __le32 dword1; 746 __le32 dword2; 747 __le32 dword3; 748 } __packed; 749 750 struct rtw89_rxdesc_long { 751 __le32 dword0; 752 __le32 dword1; 753 __le32 dword2; 754 __le32 dword3; 755 __le32 dword4; 756 __le32 dword5; 757 __le32 dword6; 758 __le32 dword7; 759 } __packed; 760 761 struct rtw89_tx_desc_info { 762 u16 pkt_size; 763 u8 wp_offset; 764 u8 mac_id; 765 u8 qsel; 766 u8 ch_dma; 767 u8 hdr_llc_len; 768 bool is_bmc; 769 bool en_wd_info; 770 bool wd_page; 771 bool use_rate; 772 bool dis_data_fb; 773 bool tid_indicate; 774 bool agg_en; 775 bool bk; 776 u8 ampdu_density; 777 u8 ampdu_num; 778 bool sec_en; 779 u8 addr_info_nr; 780 u8 sec_keyid; 781 u8 sec_type; 782 u8 sec_cam_idx; 783 u8 sec_seq[6]; 784 u16 data_rate; 785 u16 data_retry_lowest_rate; 786 bool fw_dl; 787 u16 seq; 788 bool a_ctrl_bsr; 789 u8 hw_ssn_sel; 790 #define RTW89_MGMT_HW_SSN_SEL 1 791 u8 hw_seq_mode; 792 #define RTW89_MGMT_HW_SEQ_MODE 1 793 bool hiq; 794 u8 port; 795 }; 796 797 struct rtw89_core_tx_request { 798 enum rtw89_core_tx_type tx_type; 799 800 struct sk_buff *skb; 801 struct ieee80211_vif *vif; 802 struct ieee80211_sta *sta; 803 struct rtw89_tx_desc_info desc_info; 804 }; 805 806 struct rtw89_txq { 807 struct list_head list; 808 unsigned long flags; 809 int wait_cnt; 810 }; 811 812 struct rtw89_mac_ax_gnt { 813 u8 gnt_bt_sw_en; 814 u8 gnt_bt; 815 u8 gnt_wl_sw_en; 816 u8 gnt_wl; 817 } __packed; 818 819 #define RTW89_MAC_AX_COEX_GNT_NR 2 820 struct rtw89_mac_ax_coex_gnt { 821 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 822 }; 823 824 enum rtw89_btc_ncnt { 825 BTC_NCNT_POWER_ON = 0x0, 826 BTC_NCNT_POWER_OFF, 827 BTC_NCNT_INIT_COEX, 828 BTC_NCNT_SCAN_START, 829 BTC_NCNT_SCAN_FINISH, 830 BTC_NCNT_SPECIAL_PACKET, 831 BTC_NCNT_SWITCH_BAND, 832 BTC_NCNT_RFK_TIMEOUT, 833 BTC_NCNT_SHOW_COEX_INFO, 834 BTC_NCNT_ROLE_INFO, 835 BTC_NCNT_CONTROL, 836 BTC_NCNT_RADIO_STATE, 837 BTC_NCNT_CUSTOMERIZE, 838 BTC_NCNT_WL_RFK, 839 BTC_NCNT_WL_STA, 840 BTC_NCNT_FWINFO, 841 BTC_NCNT_TIMER, 842 BTC_NCNT_NUM 843 }; 844 845 enum rtw89_btc_btinfo { 846 BTC_BTINFO_L0 = 0, 847 BTC_BTINFO_L1, 848 BTC_BTINFO_L2, 849 BTC_BTINFO_L3, 850 BTC_BTINFO_H0, 851 BTC_BTINFO_H1, 852 BTC_BTINFO_H2, 853 BTC_BTINFO_H3, 854 BTC_BTINFO_MAX 855 }; 856 857 enum rtw89_btc_dcnt { 858 BTC_DCNT_RUN = 0x0, 859 BTC_DCNT_CX_RUNINFO, 860 BTC_DCNT_RPT, 861 BTC_DCNT_RPT_FREEZE, 862 BTC_DCNT_CYCLE, 863 BTC_DCNT_CYCLE_FREEZE, 864 BTC_DCNT_W1, 865 BTC_DCNT_W1_FREEZE, 866 BTC_DCNT_B1, 867 BTC_DCNT_B1_FREEZE, 868 BTC_DCNT_TDMA_NONSYNC, 869 BTC_DCNT_SLOT_NONSYNC, 870 BTC_DCNT_BTCNT_FREEZE, 871 BTC_DCNT_WL_SLOT_DRIFT, 872 BTC_DCNT_BT_SLOT_DRIFT, 873 BTC_DCNT_WL_STA_LAST, 874 BTC_DCNT_NUM, 875 }; 876 877 enum rtw89_btc_wl_state_cnt { 878 BTC_WCNT_SCANAP = 0x0, 879 BTC_WCNT_DHCP, 880 BTC_WCNT_EAPOL, 881 BTC_WCNT_ARP, 882 BTC_WCNT_SCBDUPDATE, 883 BTC_WCNT_RFK_REQ, 884 BTC_WCNT_RFK_GO, 885 BTC_WCNT_RFK_REJECT, 886 BTC_WCNT_RFK_TIMEOUT, 887 BTC_WCNT_CH_UPDATE, 888 BTC_WCNT_NUM 889 }; 890 891 enum rtw89_btc_bt_state_cnt { 892 BTC_BCNT_RETRY = 0x0, 893 BTC_BCNT_REINIT, 894 BTC_BCNT_REENABLE, 895 BTC_BCNT_SCBDREAD, 896 BTC_BCNT_RELINK, 897 BTC_BCNT_IGNOWL, 898 BTC_BCNT_INQPAG, 899 BTC_BCNT_INQ, 900 BTC_BCNT_PAGE, 901 BTC_BCNT_ROLESW, 902 BTC_BCNT_AFH, 903 BTC_BCNT_INFOUPDATE, 904 BTC_BCNT_INFOSAME, 905 BTC_BCNT_SCBDUPDATE, 906 BTC_BCNT_HIPRI_TX, 907 BTC_BCNT_HIPRI_RX, 908 BTC_BCNT_LOPRI_TX, 909 BTC_BCNT_LOPRI_RX, 910 BTC_BCNT_POLUT, 911 BTC_BCNT_RATECHG, 912 BTC_BCNT_NUM 913 }; 914 915 enum rtw89_btc_bt_profile { 916 BTC_BT_NOPROFILE = 0, 917 BTC_BT_HFP = BIT(0), 918 BTC_BT_HID = BIT(1), 919 BTC_BT_A2DP = BIT(2), 920 BTC_BT_PAN = BIT(3), 921 BTC_PROFILE_MAX = 4, 922 }; 923 924 struct rtw89_btc_ant_info { 925 u8 type; /* shared, dedicated */ 926 u8 num; 927 u8 isolation; 928 929 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 930 u8 diversity: 1; 931 }; 932 933 enum rtw89_tfc_dir { 934 RTW89_TFC_UL, 935 RTW89_TFC_DL, 936 }; 937 938 struct rtw89_btc_wl_smap { 939 u32 busy: 1; 940 u32 scan: 1; 941 u32 connecting: 1; 942 u32 roaming: 1; 943 u32 _4way: 1; 944 u32 rf_off: 1; 945 u32 lps: 2; 946 u32 ips: 1; 947 u32 init_ok: 1; 948 u32 traffic_dir : 2; 949 u32 rf_off_pre: 1; 950 u32 lps_pre: 2; 951 }; 952 953 enum rtw89_tfc_lv { 954 RTW89_TFC_IDLE, 955 RTW89_TFC_ULTRA_LOW, 956 RTW89_TFC_LOW, 957 RTW89_TFC_MID, 958 RTW89_TFC_HIGH, 959 }; 960 961 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 962 DECLARE_EWMA(tp, 10, 2); 963 964 struct rtw89_traffic_stats { 965 /* units in bytes */ 966 u64 tx_unicast; 967 u64 rx_unicast; 968 u32 tx_avg_len; 969 u32 rx_avg_len; 970 971 /* count for packets */ 972 u64 tx_cnt; 973 u64 rx_cnt; 974 975 /* units in Mbps */ 976 u32 tx_throughput; 977 u32 rx_throughput; 978 u32 tx_throughput_raw; 979 u32 rx_throughput_raw; 980 981 u32 rx_tf_acc; 982 u32 rx_tf_periodic; 983 984 enum rtw89_tfc_lv tx_tfc_lv; 985 enum rtw89_tfc_lv rx_tfc_lv; 986 struct ewma_tp tx_ewma_tp; 987 struct ewma_tp rx_ewma_tp; 988 989 u16 tx_rate; 990 u16 rx_rate; 991 }; 992 993 struct rtw89_btc_statistic { 994 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 995 struct rtw89_traffic_stats traffic; 996 }; 997 998 #define BTC_WL_RSSI_THMAX 4 999 1000 struct rtw89_btc_wl_link_info { 1001 struct rtw89_btc_statistic stat; 1002 enum rtw89_tfc_dir dir; 1003 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1004 u8 mac_addr[ETH_ALEN]; 1005 u8 busy; 1006 u8 ch; 1007 u8 bw; 1008 u8 band; 1009 u8 role; 1010 u8 pid; 1011 u8 phy; 1012 u8 dtim_period; 1013 u8 mode; 1014 1015 u8 mac_id; 1016 u8 tx_retry; 1017 1018 u32 bcn_period; 1019 u32 busy_t; 1020 u32 tx_time; 1021 u32 client_cnt; 1022 u32 rx_rate_drop_cnt; 1023 1024 u32 active: 1; 1025 u32 noa: 1; 1026 u32 client_ps: 1; 1027 u32 connected: 2; 1028 }; 1029 1030 union rtw89_btc_wl_state_map { 1031 u32 val; 1032 struct rtw89_btc_wl_smap map; 1033 }; 1034 1035 struct rtw89_btc_bt_hfp_desc { 1036 u32 exist: 1; 1037 u32 type: 2; 1038 u32 rsvd: 29; 1039 }; 1040 1041 struct rtw89_btc_bt_hid_desc { 1042 u32 exist: 1; 1043 u32 slot_info: 2; 1044 u32 pair_cnt: 2; 1045 u32 type: 8; 1046 u32 rsvd: 19; 1047 }; 1048 1049 struct rtw89_btc_bt_a2dp_desc { 1050 u8 exist: 1; 1051 u8 exist_last: 1; 1052 u8 play_latency: 1; 1053 u8 type: 3; 1054 u8 active: 1; 1055 u8 sink: 1; 1056 1057 u8 bitpool; 1058 u16 vendor_id; 1059 u32 device_name; 1060 u32 flush_time; 1061 }; 1062 1063 struct rtw89_btc_bt_pan_desc { 1064 u32 exist: 1; 1065 u32 type: 1; 1066 u32 active: 1; 1067 u32 rsvd: 29; 1068 }; 1069 1070 struct rtw89_btc_bt_rfk_info { 1071 u32 run: 1; 1072 u32 req: 1; 1073 u32 timeout: 1; 1074 u32 rsvd: 29; 1075 }; 1076 1077 union rtw89_btc_bt_rfk_info_map { 1078 u32 val; 1079 struct rtw89_btc_bt_rfk_info map; 1080 }; 1081 1082 struct rtw89_btc_bt_ver_info { 1083 u32 fw_coex; /* match with which coex_ver */ 1084 u32 fw; 1085 }; 1086 1087 struct rtw89_btc_bool_sta_chg { 1088 u32 now: 1; 1089 u32 last: 1; 1090 u32 remain: 1; 1091 u32 srvd: 29; 1092 }; 1093 1094 struct rtw89_btc_u8_sta_chg { 1095 u8 now; 1096 u8 last; 1097 u8 remain; 1098 u8 rsvd; 1099 }; 1100 1101 struct rtw89_btc_wl_scan_info { 1102 u8 band[RTW89_PHY_MAX]; 1103 u8 phy_map; 1104 u8 rsvd; 1105 }; 1106 1107 struct rtw89_btc_wl_dbcc_info { 1108 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1109 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1110 u8 real_band[RTW89_PHY_MAX]; 1111 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1112 }; 1113 1114 struct rtw89_btc_wl_active_role { 1115 u8 connected: 1; 1116 u8 pid: 3; 1117 u8 phy: 1; 1118 u8 noa: 1; 1119 u8 band: 2; 1120 1121 u8 client_ps: 1; 1122 u8 bw: 7; 1123 1124 u8 role; 1125 u8 ch; 1126 1127 u16 tx_lvl; 1128 u16 rx_lvl; 1129 u16 tx_rate; 1130 u16 rx_rate; 1131 }; 1132 1133 struct rtw89_btc_wl_active_role_v1 { 1134 u8 connected: 1; 1135 u8 pid: 3; 1136 u8 phy: 1; 1137 u8 noa: 1; 1138 u8 band: 2; 1139 1140 u8 client_ps: 1; 1141 u8 bw: 7; 1142 1143 u8 role; 1144 u8 ch; 1145 1146 u16 tx_lvl; 1147 u16 rx_lvl; 1148 u16 tx_rate; 1149 u16 rx_rate; 1150 1151 u32 noa_duration; /* ms */ 1152 }; 1153 1154 struct rtw89_btc_wl_role_info_bpos { 1155 u16 none: 1; 1156 u16 station: 1; 1157 u16 ap: 1; 1158 u16 vap: 1; 1159 u16 adhoc: 1; 1160 u16 adhoc_master: 1; 1161 u16 mesh: 1; 1162 u16 moniter: 1; 1163 u16 p2p_device: 1; 1164 u16 p2p_gc: 1; 1165 u16 p2p_go: 1; 1166 u16 nan: 1; 1167 }; 1168 1169 struct rtw89_btc_wl_scc_ctrl { 1170 u8 null_role1; 1171 u8 null_role2; 1172 u8 ebt_null; /* if tx null at EBT slot */ 1173 }; 1174 1175 union rtw89_btc_wl_role_info_map { 1176 u16 val; 1177 struct rtw89_btc_wl_role_info_bpos role; 1178 }; 1179 1180 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1181 u8 connect_cnt; 1182 u8 link_mode; 1183 union rtw89_btc_wl_role_info_map role_map; 1184 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1185 }; 1186 1187 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1188 u8 connect_cnt; 1189 u8 link_mode; 1190 union rtw89_btc_wl_role_info_map role_map; 1191 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1192 u32 mrole_type; /* btc_wl_mrole_type */ 1193 u32 mrole_noa_duration; /* ms */ 1194 1195 u32 dbcc_en: 1; 1196 u32 dbcc_chg: 1; 1197 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1198 u32 link_mode_chg: 1; 1199 u32 rsvd: 27; 1200 }; 1201 1202 struct rtw89_btc_wl_ver_info { 1203 u32 fw_coex; /* match with which coex_ver */ 1204 u32 fw; 1205 u32 mac; 1206 u32 bb; 1207 u32 rf; 1208 }; 1209 1210 struct rtw89_btc_wl_afh_info { 1211 u8 en; 1212 u8 ch; 1213 u8 bw; 1214 u8 rsvd; 1215 } __packed; 1216 1217 struct rtw89_btc_wl_rfk_info { 1218 u32 state: 2; 1219 u32 path_map: 4; 1220 u32 phy_map: 2; 1221 u32 band: 2; 1222 u32 type: 8; 1223 u32 rsvd: 14; 1224 }; 1225 1226 struct rtw89_btc_bt_smap { 1227 u32 connect: 1; 1228 u32 ble_connect: 1; 1229 u32 acl_busy: 1; 1230 u32 sco_busy: 1; 1231 u32 mesh_busy: 1; 1232 u32 inq_pag: 1; 1233 }; 1234 1235 union rtw89_btc_bt_state_map { 1236 u32 val; 1237 struct rtw89_btc_bt_smap map; 1238 }; 1239 1240 #define BTC_BT_RSSI_THMAX 4 1241 #define BTC_BT_AFH_GROUP 12 1242 1243 struct rtw89_btc_bt_link_info { 1244 struct rtw89_btc_u8_sta_chg profile_cnt; 1245 struct rtw89_btc_bool_sta_chg multi_link; 1246 struct rtw89_btc_bool_sta_chg relink; 1247 struct rtw89_btc_bt_hfp_desc hfp_desc; 1248 struct rtw89_btc_bt_hid_desc hid_desc; 1249 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1250 struct rtw89_btc_bt_pan_desc pan_desc; 1251 union rtw89_btc_bt_state_map status; 1252 1253 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1254 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1255 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1256 u8 afh_map[BTC_BT_AFH_GROUP]; 1257 1258 u32 role_sw: 1; 1259 u32 slave_role: 1; 1260 u32 afh_update: 1; 1261 u32 cqddr: 1; 1262 u32 rssi: 8; 1263 u32 tx_3m: 1; 1264 u32 rsvd: 19; 1265 }; 1266 1267 struct rtw89_btc_3rdcx_info { 1268 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1269 u8 hw_coex; 1270 u16 rsvd; 1271 }; 1272 1273 struct rtw89_btc_dm_emap { 1274 u32 init: 1; 1275 u32 pta_owner: 1; 1276 u32 wl_rfk_timeout: 1; 1277 u32 bt_rfk_timeout: 1; 1278 1279 u32 wl_fw_hang: 1; 1280 u32 offload_mismatch: 1; 1281 u32 cycle_hang: 1; 1282 u32 w1_hang: 1; 1283 1284 u32 b1_hang: 1; 1285 u32 tdma_no_sync: 1; 1286 u32 wl_slot_drift: 1; 1287 }; 1288 1289 union rtw89_btc_dm_error_map { 1290 u32 val; 1291 struct rtw89_btc_dm_emap map; 1292 }; 1293 1294 struct rtw89_btc_rf_para { 1295 u32 tx_pwr_freerun; 1296 u32 rx_gain_freerun; 1297 u32 tx_pwr_perpkt; 1298 u32 rx_gain_perpkt; 1299 }; 1300 1301 struct rtw89_btc_wl_info { 1302 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1303 struct rtw89_btc_wl_rfk_info rfk_info; 1304 struct rtw89_btc_wl_ver_info ver_info; 1305 struct rtw89_btc_wl_afh_info afh_info; 1306 struct rtw89_btc_wl_role_info role_info; 1307 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1308 struct rtw89_btc_wl_scan_info scan_info; 1309 struct rtw89_btc_wl_dbcc_info dbcc_info; 1310 struct rtw89_btc_rf_para rf_para; 1311 union rtw89_btc_wl_state_map status; 1312 1313 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1314 u8 rssi_level; 1315 1316 u32 scbd; 1317 }; 1318 1319 struct rtw89_btc_module { 1320 struct rtw89_btc_ant_info ant; 1321 u8 rfe_type; 1322 u8 cv; 1323 1324 u8 bt_solo: 1; 1325 u8 bt_pos: 1; 1326 u8 switch_type: 1; 1327 1328 u8 rsvd; 1329 }; 1330 1331 #define RTW89_BTC_DM_MAXSTEP 30 1332 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1333 1334 struct rtw89_btc_dm_step { 1335 u16 step[RTW89_BTC_DM_MAXSTEP]; 1336 u8 step_pos; 1337 bool step_ov; 1338 }; 1339 1340 struct rtw89_btc_init_info { 1341 struct rtw89_btc_module module; 1342 u8 wl_guard_ch; 1343 1344 u8 wl_only: 1; 1345 u8 wl_init_ok: 1; 1346 u8 dbcc_en: 1; 1347 u8 cx_other: 1; 1348 u8 bt_only: 1; 1349 1350 u16 rsvd; 1351 }; 1352 1353 struct rtw89_btc_wl_tx_limit_para { 1354 u16 enable; 1355 u32 tx_time; /* unit: us */ 1356 u16 tx_retry; 1357 }; 1358 1359 struct rtw89_btc_bt_scan_info { 1360 u16 win; 1361 u16 intvl; 1362 u32 enable: 1; 1363 u32 interlace: 1; 1364 u32 rsvd: 30; 1365 }; 1366 1367 enum rtw89_btc_bt_scan_type { 1368 BTC_SCAN_INQ = 0, 1369 BTC_SCAN_PAGE, 1370 BTC_SCAN_BLE, 1371 BTC_SCAN_INIT, 1372 BTC_SCAN_TV, 1373 BTC_SCAN_ADV, 1374 BTC_SCAN_MAX1, 1375 }; 1376 1377 struct rtw89_btc_bt_info { 1378 struct rtw89_btc_bt_link_info link_info; 1379 struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1]; 1380 struct rtw89_btc_bt_ver_info ver_info; 1381 struct rtw89_btc_bool_sta_chg enable; 1382 struct rtw89_btc_bool_sta_chg inq_pag; 1383 struct rtw89_btc_rf_para rf_para; 1384 union rtw89_btc_bt_rfk_info_map rfk_info; 1385 1386 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1387 1388 u32 scbd; 1389 u32 feature; 1390 1391 u32 mbx_avl: 1; 1392 u32 whql_test: 1; 1393 u32 igno_wl: 1; 1394 u32 reinit: 1; 1395 u32 ble_scan_en: 1; 1396 u32 btg_type: 1; 1397 u32 inq: 1; 1398 u32 pag: 1; 1399 u32 run_patch_code: 1; 1400 u32 hi_lna_rx: 1; 1401 u32 rsvd: 22; 1402 }; 1403 1404 struct rtw89_btc_cx { 1405 struct rtw89_btc_wl_info wl; 1406 struct rtw89_btc_bt_info bt; 1407 struct rtw89_btc_3rdcx_info other; 1408 u32 state_map; 1409 u32 cnt_bt[BTC_BCNT_NUM]; 1410 u32 cnt_wl[BTC_WCNT_NUM]; 1411 }; 1412 1413 struct rtw89_btc_fbtc_tdma { 1414 u8 type; /* chip_info::fcxtdma_ver */ 1415 u8 rxflctrl; 1416 u8 txpause; 1417 u8 wtgle_n; 1418 u8 leak_n; 1419 u8 ext_ctrl; 1420 u8 rxflctrl_role; 1421 u8 option_ctrl; 1422 } __packed; 1423 1424 struct rtw89_btc_fbtc_tdma_v1 { 1425 u8 fver; /* chip_info::fcxtdma_ver */ 1426 u8 rsvd; 1427 __le16 rsvd1; 1428 struct rtw89_btc_fbtc_tdma tdma; 1429 } __packed; 1430 1431 #define CXMREG_MAX 30 1432 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1433 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1434 1435 enum rtw89_btc_bt_sta_counter { 1436 BTC_BCNT_RFK_REQ = 0, 1437 BTC_BCNT_RFK_GO = 1, 1438 BTC_BCNT_RFK_REJECT = 2, 1439 BTC_BCNT_RFK_FAIL = 3, 1440 BTC_BCNT_RFK_TIMEOUT = 4, 1441 BTC_BCNT_HI_TX = 5, 1442 BTC_BCNT_HI_RX = 6, 1443 BTC_BCNT_LO_TX = 7, 1444 BTC_BCNT_LO_RX = 8, 1445 BTC_BCNT_POLLUTED = 9, 1446 BTC_BCNT_STA_MAX 1447 }; 1448 1449 struct rtw89_btc_fbtc_rpt_ctrl { 1450 u16 fver; /* chip_info::fcxbtcrpt_ver */ 1451 u16 rpt_cnt; /* tmr counters */ 1452 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1453 u32 wl_fw_cx_offload; 1454 u32 wl_fw_ver; 1455 u32 rpt_enable; 1456 u32 rpt_para; /* ms */ 1457 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1458 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1459 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1460 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1461 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1462 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1463 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1464 u32 c2h_cnt; /* fw send c2h counter */ 1465 u32 h2c_cnt; /* fw recv h2c counter */ 1466 } __packed; 1467 1468 struct rtw89_btc_fbtc_rpt_ctrl_info { 1469 __le32 cnt; /* fw report counter */ 1470 __le32 en; /* report map */ 1471 __le32 para; /* not used */ 1472 1473 __le32 cnt_c2h; /* fw send c2h counter */ 1474 __le32 cnt_h2c; /* fw recv h2c counter */ 1475 __le32 len_c2h; /* The total length of the last C2H */ 1476 1477 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1478 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1479 } __packed; 1480 1481 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1482 __le32 cx_ver; /* match which driver's coex version */ 1483 __le32 cx_offload; 1484 __le32 fw_ver; 1485 } __packed; 1486 1487 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1488 __le32 cnt_empty; /* a2dp empty count */ 1489 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1490 __le32 cnt_tx; 1491 __le32 cnt_ack; 1492 __le32 cnt_nack; 1493 } __packed; 1494 1495 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1496 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1497 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1498 __le32 cnt_recv; /* fw recv mailbox counter */ 1499 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1500 } __packed; 1501 1502 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1503 u8 fver; 1504 u8 rsvd; 1505 __le16 rsvd1; 1506 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1507 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1508 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1509 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1510 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1511 } __packed; 1512 1513 enum rtw89_fbtc_ext_ctrl_type { 1514 CXECTL_OFF = 0x0, /* tdma off */ 1515 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1516 CXECTL_EXT = 0x2, 1517 CXECTL_MAX 1518 }; 1519 1520 union rtw89_btc_fbtc_rxflct { 1521 u8 val; 1522 u8 type: 3; 1523 u8 tgln_n: 5; 1524 }; 1525 1526 enum rtw89_btc_cxst_state { 1527 CXST_OFF = 0x0, 1528 CXST_B2W = 0x1, 1529 CXST_W1 = 0x2, 1530 CXST_W2 = 0x3, 1531 CXST_W2B = 0x4, 1532 CXST_B1 = 0x5, 1533 CXST_B2 = 0x6, 1534 CXST_B3 = 0x7, 1535 CXST_B4 = 0x8, 1536 CXST_LK = 0x9, 1537 CXST_BLK = 0xa, 1538 CXST_E2G = 0xb, 1539 CXST_E5G = 0xc, 1540 CXST_EBT = 0xd, 1541 CXST_ENULL = 0xe, 1542 CXST_WLK = 0xf, 1543 CXST_W1FDD = 0x10, 1544 CXST_B1FDD = 0x11, 1545 CXST_MAX = 0x12, 1546 }; 1547 1548 enum { 1549 CXBCN_ALL = 0x0, 1550 CXBCN_ALL_OK, 1551 CXBCN_BT_SLOT, 1552 CXBCN_BT_OK, 1553 CXBCN_MAX 1554 }; 1555 1556 enum btc_slot_type { 1557 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1558 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 1559 CXSTYPE_NUM, 1560 }; 1561 1562 enum { /* TIME */ 1563 CXT_BT = 0x0, 1564 CXT_WL = 0x1, 1565 CXT_MAX 1566 }; 1567 1568 enum { /* TIME-A2DP */ 1569 CXT_FLCTRL_OFF = 0x0, 1570 CXT_FLCTRL_ON = 0x1, 1571 CXT_FLCTRL_MAX 1572 }; 1573 1574 enum { /* STEP TYPE */ 1575 CXSTEP_NONE = 0x0, 1576 CXSTEP_EVNT = 0x1, 1577 CXSTEP_SLOT = 0x2, 1578 CXSTEP_MAX, 1579 }; 1580 1581 #define BTC_DBG_MAX1 32 1582 struct rtw89_btc_fbtc_gpio_dbg { 1583 u8 fver; /* chip_info::fcxgpiodbg_ver */ 1584 u8 rsvd; 1585 u16 rsvd2; 1586 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 1587 u32 pre_state; /* the debug signal is 1 or 0 */ 1588 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 1589 } __packed; 1590 1591 struct rtw89_btc_fbtc_mreg_val { 1592 u8 fver; /* chip_info::fcxmreg_ver */ 1593 u8 reg_num; 1594 __le16 rsvd; 1595 __le32 mreg_val[CXMREG_MAX]; 1596 } __packed; 1597 1598 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 1599 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 1600 .offset = cpu_to_le32(__offset), } 1601 1602 struct rtw89_btc_fbtc_mreg { 1603 __le16 type; 1604 __le16 bytes; 1605 __le32 offset; 1606 } __packed; 1607 1608 struct rtw89_btc_fbtc_slot { 1609 __le16 dur; 1610 __le32 cxtbl; 1611 __le16 cxtype; 1612 } __packed; 1613 1614 struct rtw89_btc_fbtc_slots { 1615 u8 fver; /* chip_info::fcxslots_ver */ 1616 u8 tbl_num; 1617 __le16 rsvd; 1618 __le32 update_map; 1619 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1620 } __packed; 1621 1622 struct rtw89_btc_fbtc_step { 1623 u8 type; 1624 u8 val; 1625 __le16 difft; 1626 } __packed; 1627 1628 struct rtw89_btc_fbtc_steps { 1629 u8 fver; /* chip_info::fcxstep_ver */ 1630 u8 rsvd; 1631 __le16 cnt; 1632 __le16 pos_old; 1633 __le16 pos_new; 1634 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1635 } __packed; 1636 1637 struct rtw89_btc_fbtc_cysta { /* statistics for cycles */ 1638 u8 fver; /* chip_info::fcxcysta_ver */ 1639 u8 rsvd; 1640 __le16 cycles; /* total cycle number */ 1641 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 1642 __le16 a2dpept; /* a2dp empty cnt */ 1643 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 1644 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 1645 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 1646 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1647 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 1648 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 1649 __le16 tavg_a2dpept; /* avg a2dp empty time */ 1650 __le16 tmax_a2dpept; /* max a2dp empty time */ 1651 __le16 tavg_lk; /* avg leak-slot time */ 1652 __le16 tmax_lk; /* max leak-slot time */ 1653 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1654 __le32 bcn_cnt[CXBCN_MAX]; 1655 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 1656 __le32 collision_cnt; /* counter for event/timer occur at same time */ 1657 __le32 skip_cnt; 1658 __le32 exception; 1659 __le32 except_cnt; 1660 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 1661 } __packed; 1662 1663 struct rtw89_btc_fbtc_fdd_try_info { 1664 __le16 cycles[CXT_FLCTRL_MAX]; 1665 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 1666 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 1667 } __packed; 1668 1669 struct rtw89_btc_fbtc_cycle_time_info { 1670 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 1671 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 1672 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1673 } __packed; 1674 1675 struct rtw89_btc_fbtc_a2dp_trx_stat { 1676 u8 empty_cnt; 1677 u8 retry_cnt; 1678 u8 tx_rate; 1679 u8 tx_cnt; 1680 u8 ack_cnt; 1681 u8 nack_cnt; 1682 u8 rsvd1; 1683 u8 rsvd2; 1684 } __packed; 1685 1686 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 1687 __le16 cnt; /* a2dp empty cnt */ 1688 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 1689 __le16 tavg; /* avg a2dp empty time */ 1690 __le16 tmax; /* max a2dp empty time */ 1691 } __packed; 1692 1693 struct rtw89_btc_fbtc_cycle_leak_info { 1694 __le32 cnt_rximr; /* the rximr occur at leak slot */ 1695 __le16 tavg; /* avg leak-slot time */ 1696 __le16 tmax; /* max leak-slot time */ 1697 } __packed; 1698 1699 struct rtw89_btc_fbtc_cysta_v1 { /* statistics for cycles */ 1700 u8 fver; 1701 u8 rsvd; 1702 __le16 cycles; /* total cycle number */ 1703 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 1704 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 1705 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 1706 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 1707 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 1708 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 1709 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1710 __le32 bcn_cnt[CXBCN_MAX]; 1711 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 1712 __le32 skip_cnt; 1713 __le32 except_cnt; 1714 __le32 except_map; 1715 } __packed; 1716 1717 struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */ 1718 u8 fver; /* chip_info::fcxnullsta_ver */ 1719 u8 rsvd; 1720 __le16 rsvd2; 1721 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 1722 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 1723 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 1724 } __packed; 1725 1726 struct rtw89_btc_fbtc_btver { 1727 u8 fver; /* chip_info::fcxbtver_ver */ 1728 u8 rsvd; 1729 __le16 rsvd2; 1730 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 1731 __le32 fw_ver; 1732 __le32 feature; 1733 } __packed; 1734 1735 struct rtw89_btc_fbtc_btscan { 1736 u8 fver; /* chip_info::fcxbtscan_ver */ 1737 u8 rsvd; 1738 __le16 rsvd2; 1739 u8 scan[6]; 1740 } __packed; 1741 1742 struct rtw89_btc_fbtc_btafh { 1743 u8 fver; /* chip_info::fcxbtafh_ver */ 1744 u8 rsvd; 1745 __le16 rsvd2; 1746 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 1747 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 1748 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 1749 } __packed; 1750 1751 struct rtw89_btc_fbtc_btdevinfo { 1752 u8 fver; /* chip_info::fcxbtdevinfo_ver */ 1753 u8 rsvd; 1754 __le16 vendor_id; 1755 __le32 dev_name; /* only 24 bits valid */ 1756 __le32 flush_time; 1757 } __packed; 1758 1759 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 1760 struct rtw89_btc_rf_trx_para { 1761 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1762 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 1763 u8 bt_tx_power; /* decrease Tx power (dB) */ 1764 u8 bt_rx_gain; /* LNA constrain level */ 1765 }; 1766 1767 struct rtw89_btc_dm { 1768 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1769 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 1770 struct rtw89_btc_fbtc_tdma tdma; 1771 struct rtw89_btc_fbtc_tdma tdma_now; 1772 struct rtw89_mac_ax_coex_gnt gnt; 1773 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 1774 struct rtw89_btc_rf_trx_para rf_trx_para; 1775 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 1776 struct rtw89_btc_dm_step dm_step; 1777 struct rtw89_btc_wl_scc_ctrl wl_scc; 1778 union rtw89_btc_dm_error_map error; 1779 u32 cnt_dm[BTC_DCNT_NUM]; 1780 u32 cnt_notify[BTC_NCNT_NUM]; 1781 1782 u32 update_slot_map; 1783 u32 set_ant_path; 1784 1785 u32 wl_only: 1; 1786 u32 wl_fw_cx_offload: 1; 1787 u32 freerun: 1; 1788 u32 wl_ps_ctrl: 2; 1789 u32 wl_mimo_ps: 1; 1790 u32 leak_ap: 1; 1791 u32 noisy_level: 3; 1792 u32 coex_info_map: 8; 1793 u32 bt_only: 1; 1794 u32 wl_btg_rx: 1; 1795 u32 trx_para_level: 8; 1796 u32 wl_stb_chg: 1; 1797 u32 tdma_instant_excute: 1; 1798 u32 rsvd: 2; 1799 1800 u16 slot_dur[CXST_MAX]; 1801 1802 u8 run_reason; 1803 u8 run_action; 1804 }; 1805 1806 struct rtw89_btc_ctrl { 1807 u32 manual: 1; 1808 u32 igno_bt: 1; 1809 u32 always_freerun: 1; 1810 u32 trace_step: 16; 1811 u32 rsvd: 12; 1812 }; 1813 1814 struct rtw89_btc_dbg { 1815 /* cmd "rb" */ 1816 bool rb_done; 1817 u32 rb_val; 1818 }; 1819 1820 enum rtw89_btc_btf_fw_event { 1821 BTF_EVNT_RPT = 0, 1822 BTF_EVNT_BT_INFO = 1, 1823 BTF_EVNT_BT_SCBD = 2, 1824 BTF_EVNT_BT_REG = 3, 1825 BTF_EVNT_CX_RUNINFO = 4, 1826 BTF_EVNT_BT_PSD = 5, 1827 BTF_EVNT_BUF_OVERFLOW, 1828 BTF_EVNT_C2H_LOOPBACK, 1829 BTF_EVNT_MAX, 1830 }; 1831 1832 enum btf_fw_event_report { 1833 BTC_RPT_TYPE_CTRL = 0x0, 1834 BTC_RPT_TYPE_TDMA, 1835 BTC_RPT_TYPE_SLOT, 1836 BTC_RPT_TYPE_CYSTA, 1837 BTC_RPT_TYPE_STEP, 1838 BTC_RPT_TYPE_NULLSTA, 1839 BTC_RPT_TYPE_MREG, 1840 BTC_RPT_TYPE_GPIO_DBG, 1841 BTC_RPT_TYPE_BT_VER, 1842 BTC_RPT_TYPE_BT_SCAN, 1843 BTC_RPT_TYPE_BT_AFH, 1844 BTC_RPT_TYPE_BT_DEVICE, 1845 BTC_RPT_TYPE_TEST, 1846 BTC_RPT_TYPE_MAX = 31 1847 }; 1848 1849 enum rtw_btc_btf_reg_type { 1850 REG_MAC = 0x0, 1851 REG_BB = 0x1, 1852 REG_RF = 0x2, 1853 REG_BT_RF = 0x3, 1854 REG_BT_MODEM = 0x4, 1855 REG_BT_BLUEWIZE = 0x5, 1856 REG_BT_VENDOR = 0x6, 1857 REG_BT_LE = 0x7, 1858 REG_MAX_TYPE, 1859 }; 1860 1861 struct rtw89_btc_rpt_cmn_info { 1862 u32 rx_cnt; 1863 u32 rx_len; 1864 u32 req_len; /* expected rsp len */ 1865 u8 req_fver; /* expected rsp fver */ 1866 u8 rsp_fver; /* fver from fw */ 1867 u8 valid; 1868 } __packed; 1869 1870 struct rtw89_btc_report_ctrl_state { 1871 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1872 union { 1873 struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw for 52A*/ 1874 struct rtw89_btc_fbtc_rpt_ctrl_v1 finfo_v1; /* info from fw for 52C*/ 1875 }; 1876 }; 1877 1878 struct rtw89_btc_rpt_fbtc_tdma { 1879 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1880 union { 1881 struct rtw89_btc_fbtc_tdma finfo; /* info from fw */ 1882 struct rtw89_btc_fbtc_tdma_v1 finfo_v1; /* info from fw for 52C*/ 1883 }; 1884 }; 1885 1886 struct rtw89_btc_rpt_fbtc_slots { 1887 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1888 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 1889 }; 1890 1891 struct rtw89_btc_rpt_fbtc_cysta { 1892 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1893 union { 1894 struct rtw89_btc_fbtc_cysta finfo; /* info from fw for 52A*/ 1895 struct rtw89_btc_fbtc_cysta_v1 finfo_v1; /* info from fw for 52C*/ 1896 }; 1897 }; 1898 1899 struct rtw89_btc_rpt_fbtc_step { 1900 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1901 struct rtw89_btc_fbtc_steps finfo; /* info from fw */ 1902 }; 1903 1904 struct rtw89_btc_rpt_fbtc_nullsta { 1905 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1906 struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */ 1907 }; 1908 1909 struct rtw89_btc_rpt_fbtc_mreg { 1910 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1911 struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 1912 }; 1913 1914 struct rtw89_btc_rpt_fbtc_gpio_dbg { 1915 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1916 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 1917 }; 1918 1919 struct rtw89_btc_rpt_fbtc_btver { 1920 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1921 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 1922 }; 1923 1924 struct rtw89_btc_rpt_fbtc_btscan { 1925 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1926 struct rtw89_btc_fbtc_btscan finfo; /* info from fw */ 1927 }; 1928 1929 struct rtw89_btc_rpt_fbtc_btafh { 1930 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1931 struct rtw89_btc_fbtc_btafh finfo; /* info from fw */ 1932 }; 1933 1934 struct rtw89_btc_rpt_fbtc_btdev { 1935 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1936 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 1937 }; 1938 1939 enum rtw89_btc_btfre_type { 1940 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 1941 BTFRE_UNDEF_TYPE, 1942 BTFRE_EXCEPTION, 1943 BTFRE_MAX, 1944 }; 1945 1946 struct rtw89_btc_btf_fwinfo { 1947 u32 cnt_c2h; 1948 u32 cnt_h2c; 1949 u32 cnt_h2c_fail; 1950 u32 event[BTF_EVNT_MAX]; 1951 1952 u32 err[BTFRE_MAX]; 1953 u32 len_mismch; 1954 u32 fver_mismch; 1955 u32 rpt_en_map; 1956 1957 struct rtw89_btc_report_ctrl_state rpt_ctrl; 1958 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 1959 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 1960 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 1961 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 1962 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 1963 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 1964 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 1965 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 1966 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 1967 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 1968 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 1969 }; 1970 1971 #define RTW89_BTC_POLICY_MAXLEN 512 1972 1973 struct rtw89_btc { 1974 struct rtw89_btc_cx cx; 1975 struct rtw89_btc_dm dm; 1976 struct rtw89_btc_ctrl ctrl; 1977 struct rtw89_btc_module mdinfo; 1978 struct rtw89_btc_btf_fwinfo fwinfo; 1979 struct rtw89_btc_dbg dbg; 1980 1981 struct work_struct eapol_notify_work; 1982 struct work_struct arp_notify_work; 1983 struct work_struct dhcp_notify_work; 1984 struct work_struct icmp_notify_work; 1985 1986 u32 bt_req_len; 1987 1988 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 1989 u16 policy_len; 1990 u16 policy_type; 1991 bool bt_req_en; 1992 bool update_policy_force; 1993 bool lps; 1994 }; 1995 1996 enum rtw89_ra_mode { 1997 RTW89_RA_MODE_CCK = BIT(0), 1998 RTW89_RA_MODE_OFDM = BIT(1), 1999 RTW89_RA_MODE_HT = BIT(2), 2000 RTW89_RA_MODE_VHT = BIT(3), 2001 RTW89_RA_MODE_HE = BIT(4), 2002 }; 2003 2004 enum rtw89_ra_report_mode { 2005 RTW89_RA_RPT_MODE_LEGACY, 2006 RTW89_RA_RPT_MODE_HT, 2007 RTW89_RA_RPT_MODE_VHT, 2008 RTW89_RA_RPT_MODE_HE, 2009 }; 2010 2011 enum rtw89_dig_noisy_level { 2012 RTW89_DIG_NOISY_LEVEL0 = -1, 2013 RTW89_DIG_NOISY_LEVEL1 = 0, 2014 RTW89_DIG_NOISY_LEVEL2 = 1, 2015 RTW89_DIG_NOISY_LEVEL3 = 2, 2016 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2017 }; 2018 2019 enum rtw89_gi_ltf { 2020 RTW89_GILTF_LGI_4XHE32 = 0, 2021 RTW89_GILTF_SGI_4XHE08 = 1, 2022 RTW89_GILTF_2XHE16 = 2, 2023 RTW89_GILTF_2XHE08 = 3, 2024 RTW89_GILTF_1XHE16 = 4, 2025 RTW89_GILTF_1XHE08 = 5, 2026 RTW89_GILTF_MAX 2027 }; 2028 2029 enum rtw89_rx_frame_type { 2030 RTW89_RX_TYPE_MGNT = 0, 2031 RTW89_RX_TYPE_CTRL = 1, 2032 RTW89_RX_TYPE_DATA = 2, 2033 RTW89_RX_TYPE_RSVD = 3, 2034 }; 2035 2036 struct rtw89_ra_info { 2037 u8 is_dis_ra:1; 2038 /* Bit0 : CCK 2039 * Bit1 : OFDM 2040 * Bit2 : HT 2041 * Bit3 : VHT 2042 * Bit4 : HE 2043 */ 2044 u8 mode_ctrl:5; 2045 u8 bw_cap:2; 2046 u8 macid; 2047 u8 dcm_cap:1; 2048 u8 er_cap:1; 2049 u8 init_rate_lv:2; 2050 u8 upd_all:1; 2051 u8 en_sgi:1; 2052 u8 ldpc_cap:1; 2053 u8 stbc_cap:1; 2054 u8 ss_num:3; 2055 u8 giltf:3; 2056 u8 upd_bw_nss_mask:1; 2057 u8 upd_mask:1; 2058 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2059 /* BFee CSI */ 2060 u8 band_num; 2061 u8 ra_csi_rate_en:1; 2062 u8 fixed_csi_rate_en:1; 2063 u8 cr_tbl_sel:1; 2064 u8 rsvd2:5; 2065 u8 csi_mcs_ss_idx; 2066 u8 csi_mode:2; 2067 u8 csi_gi_ltf:3; 2068 u8 csi_bw:3; 2069 }; 2070 2071 #define RTW89_PPDU_MAX_USR 4 2072 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2073 #define RTW89_PPDU_MAC_INFO_SIZE 8 2074 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2075 2076 #define RTW89_MAX_RX_AGG_NUM 64 2077 #define RTW89_MAX_TX_AGG_NUM 128 2078 2079 struct rtw89_ampdu_params { 2080 u16 agg_num; 2081 bool amsdu; 2082 }; 2083 2084 struct rtw89_ra_report { 2085 struct rate_info txrate; 2086 u32 bit_rate; 2087 u16 hw_rate; 2088 bool might_fallback_legacy; 2089 }; 2090 2091 DECLARE_EWMA(rssi, 10, 16); 2092 2093 struct rtw89_ba_cam_entry { 2094 struct list_head list; 2095 u8 tid; 2096 }; 2097 2098 #define RTW89_MAX_ADDR_CAM_NUM 128 2099 #define RTW89_MAX_BSSID_CAM_NUM 20 2100 #define RTW89_MAX_SEC_CAM_NUM 128 2101 #define RTW89_MAX_BA_CAM_NUM 8 2102 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2103 2104 struct rtw89_addr_cam_entry { 2105 u8 addr_cam_idx; 2106 u8 offset; 2107 u8 len; 2108 u8 valid : 1; 2109 u8 addr_mask : 6; 2110 u8 wapi : 1; 2111 u8 mask_sel : 2; 2112 u8 bssid_cam_idx: 6; 2113 2114 u8 sec_ent_mode; 2115 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2116 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2117 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2118 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2119 }; 2120 2121 struct rtw89_bssid_cam_entry { 2122 u8 bssid[ETH_ALEN]; 2123 u8 phy_idx; 2124 u8 bssid_cam_idx; 2125 u8 offset; 2126 u8 len; 2127 u8 valid : 1; 2128 u8 num; 2129 }; 2130 2131 struct rtw89_sec_cam_entry { 2132 u8 sec_cam_idx; 2133 u8 offset; 2134 u8 len; 2135 u8 type : 4; 2136 u8 ext_key : 1; 2137 u8 spp_mode : 1; 2138 /* 256 bits */ 2139 u8 key[32]; 2140 }; 2141 2142 struct rtw89_sta { 2143 u8 mac_id; 2144 bool disassoc; 2145 struct rtw89_vif *rtwvif; 2146 struct rtw89_ra_info ra; 2147 struct rtw89_ra_report ra_report; 2148 int max_agg_wait; 2149 u8 prev_rssi; 2150 struct ewma_rssi avg_rssi; 2151 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2152 struct ieee80211_rx_status rx_status; 2153 u16 rx_hw_rate; 2154 __le32 htc_template; 2155 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2156 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2157 struct list_head ba_cam_list; 2158 2159 bool use_cfg_mask; 2160 struct cfg80211_bitrate_mask mask; 2161 2162 bool cctl_tx_time; 2163 u32 ampdu_max_time:4; 2164 bool cctl_tx_retry_limit; 2165 u32 data_tx_cnt_lmt:6; 2166 }; 2167 2168 struct rtw89_efuse { 2169 bool valid; 2170 u8 xtal_cap; 2171 u8 addr[ETH_ALEN]; 2172 u8 rfe_type; 2173 char country_code[2]; 2174 }; 2175 2176 struct rtw89_phy_rate_pattern { 2177 u64 ra_mask; 2178 u16 rate; 2179 u8 ra_mode; 2180 bool enable; 2181 }; 2182 2183 struct rtw89_vif { 2184 struct list_head list; 2185 struct rtw89_dev *rtwdev; 2186 u8 mac_id; 2187 u8 port; 2188 u8 mac_addr[ETH_ALEN]; 2189 u8 bssid[ETH_ALEN]; 2190 u8 phy_idx; 2191 u8 mac_idx; 2192 u8 net_type; 2193 u8 wifi_role; 2194 u8 self_role; 2195 u8 wmm; 2196 u8 bcn_hit_cond; 2197 u8 hit_rule; 2198 bool trigger; 2199 bool lsig_txop; 2200 u8 tgt_ind; 2201 u8 frm_tgt_ind; 2202 bool wowlan_pattern; 2203 bool wowlan_uc; 2204 bool wowlan_magic; 2205 bool is_hesta; 2206 bool last_a_ctrl; 2207 struct work_struct update_beacon_work; 2208 struct rtw89_addr_cam_entry addr_cam; 2209 struct rtw89_bssid_cam_entry bssid_cam; 2210 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 2211 struct rtw89_traffic_stats stats; 2212 struct rtw89_phy_rate_pattern rate_pattern; 2213 struct cfg80211_scan_request *scan_req; 2214 struct ieee80211_scan_ies *scan_ies; 2215 }; 2216 2217 enum rtw89_lv1_rcvy_step { 2218 RTW89_LV1_RCVY_STEP_1, 2219 RTW89_LV1_RCVY_STEP_2, 2220 }; 2221 2222 struct rtw89_hci_ops { 2223 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 2224 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 2225 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 2226 void (*reset)(struct rtw89_dev *rtwdev); 2227 int (*start)(struct rtw89_dev *rtwdev); 2228 void (*stop)(struct rtw89_dev *rtwdev); 2229 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 2230 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 2231 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 2232 2233 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 2234 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 2235 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 2236 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 2237 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 2238 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 2239 2240 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 2241 int (*mac_post_init)(struct rtw89_dev *rtwdev); 2242 int (*deinit)(struct rtw89_dev *rtwdev); 2243 2244 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 2245 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 2246 void (*dump_err_status)(struct rtw89_dev *rtwdev); 2247 int (*napi_poll)(struct napi_struct *napi, int budget); 2248 2249 /* Deal with locks inside recovery_start and recovery_complete callbacks 2250 * by hci instance, and handle things which need to consider under SER. 2251 * e.g. turn on/off interrupts except for the one for halt notification. 2252 */ 2253 void (*recovery_start)(struct rtw89_dev *rtwdev); 2254 void (*recovery_complete)(struct rtw89_dev *rtwdev); 2255 }; 2256 2257 struct rtw89_hci_info { 2258 const struct rtw89_hci_ops *ops; 2259 enum rtw89_hci_type type; 2260 u32 rpwm_addr; 2261 u32 cpwm_addr; 2262 bool paused; 2263 }; 2264 2265 struct rtw89_chip_ops { 2266 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 2267 void (*disable_bb_rf)(struct rtw89_dev *rtwdev); 2268 void (*bb_reset)(struct rtw89_dev *rtwdev, 2269 enum rtw89_phy_idx phy_idx); 2270 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2271 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2272 u32 addr, u32 mask); 2273 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2274 u32 addr, u32 mask, u32 data); 2275 void (*set_channel)(struct rtw89_dev *rtwdev, 2276 const struct rtw89_chan *chan, 2277 enum rtw89_mac_idx mac_idx, 2278 enum rtw89_phy_idx phy_idx); 2279 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 2280 struct rtw89_channel_help_params *p, 2281 const struct rtw89_chan *chan, 2282 enum rtw89_mac_idx mac_idx, 2283 enum rtw89_phy_idx phy_idx); 2284 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 2285 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 2286 void (*fem_setup)(struct rtw89_dev *rtwdev); 2287 void (*rfk_init)(struct rtw89_dev *rtwdev); 2288 void (*rfk_channel)(struct rtw89_dev *rtwdev); 2289 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 2290 enum rtw89_phy_idx phy_idx); 2291 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 2292 void (*rfk_track)(struct rtw89_dev *rtwdev); 2293 void (*power_trim)(struct rtw89_dev *rtwdev); 2294 void (*set_txpwr)(struct rtw89_dev *rtwdev, 2295 const struct rtw89_chan *chan, 2296 enum rtw89_phy_idx phy_idx); 2297 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 2298 enum rtw89_phy_idx phy_idx); 2299 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 2300 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 2301 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 2302 void (*query_ppdu)(struct rtw89_dev *rtwdev, 2303 struct rtw89_rx_phy_ppdu *phy_ppdu, 2304 struct ieee80211_rx_status *status); 2305 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 2306 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 2307 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 2308 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 2309 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 2310 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 2311 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 2312 struct rtw89_tx_desc_info *desc_info, 2313 void *txdesc); 2314 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 2315 struct rtw89_tx_desc_info *desc_info, 2316 void *txdesc); 2317 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 2318 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 2319 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 2320 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 2321 u32 *tx_en, enum rtw89_sch_tx_sel sel); 2322 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 2323 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 2324 struct rtw89_vif *rtwvif, 2325 struct rtw89_sta *rtwsta); 2326 2327 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 2328 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 2329 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 2330 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 2331 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 2332 void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev); 2333 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 2334 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 2335 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 2336 }; 2337 2338 enum rtw89_dma_ch { 2339 RTW89_DMA_ACH0 = 0, 2340 RTW89_DMA_ACH1 = 1, 2341 RTW89_DMA_ACH2 = 2, 2342 RTW89_DMA_ACH3 = 3, 2343 RTW89_DMA_ACH4 = 4, 2344 RTW89_DMA_ACH5 = 5, 2345 RTW89_DMA_ACH6 = 6, 2346 RTW89_DMA_ACH7 = 7, 2347 RTW89_DMA_B0MG = 8, 2348 RTW89_DMA_B0HI = 9, 2349 RTW89_DMA_B1MG = 10, 2350 RTW89_DMA_B1HI = 11, 2351 RTW89_DMA_H2C = 12, 2352 RTW89_DMA_CH_NUM = 13 2353 }; 2354 2355 enum rtw89_qta_mode { 2356 RTW89_QTA_SCC, 2357 RTW89_QTA_DLFW, 2358 2359 /* keep last */ 2360 RTW89_QTA_INVALID, 2361 }; 2362 2363 struct rtw89_hfc_ch_cfg { 2364 u16 min; 2365 u16 max; 2366 #define grp_0 0 2367 #define grp_1 1 2368 #define grp_num 2 2369 u8 grp; 2370 }; 2371 2372 struct rtw89_hfc_ch_info { 2373 u16 aval; 2374 u16 used; 2375 }; 2376 2377 struct rtw89_hfc_pub_cfg { 2378 u16 grp0; 2379 u16 grp1; 2380 u16 pub_max; 2381 u16 wp_thrd; 2382 }; 2383 2384 struct rtw89_hfc_pub_info { 2385 u16 g0_used; 2386 u16 g1_used; 2387 u16 g0_aval; 2388 u16 g1_aval; 2389 u16 pub_aval; 2390 u16 wp_aval; 2391 }; 2392 2393 struct rtw89_hfc_prec_cfg { 2394 u16 ch011_prec; 2395 u16 h2c_prec; 2396 u16 wp_ch07_prec; 2397 u16 wp_ch811_prec; 2398 u8 ch011_full_cond; 2399 u8 h2c_full_cond; 2400 u8 wp_ch07_full_cond; 2401 u8 wp_ch811_full_cond; 2402 }; 2403 2404 struct rtw89_hfc_param { 2405 bool en; 2406 bool h2c_en; 2407 u8 mode; 2408 const struct rtw89_hfc_ch_cfg *ch_cfg; 2409 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 2410 struct rtw89_hfc_pub_cfg pub_cfg; 2411 struct rtw89_hfc_pub_info pub_info; 2412 struct rtw89_hfc_prec_cfg prec_cfg; 2413 }; 2414 2415 struct rtw89_hfc_param_ini { 2416 const struct rtw89_hfc_ch_cfg *ch_cfg; 2417 const struct rtw89_hfc_pub_cfg *pub_cfg; 2418 const struct rtw89_hfc_prec_cfg *prec_cfg; 2419 u8 mode; 2420 }; 2421 2422 struct rtw89_dle_size { 2423 u16 pge_size; 2424 u16 lnk_pge_num; 2425 u16 unlnk_pge_num; 2426 }; 2427 2428 struct rtw89_wde_quota { 2429 u16 hif; 2430 u16 wcpu; 2431 u16 pkt_in; 2432 u16 cpu_io; 2433 }; 2434 2435 struct rtw89_ple_quota { 2436 u16 cma0_tx; 2437 u16 cma1_tx; 2438 u16 c2h; 2439 u16 h2c; 2440 u16 wcpu; 2441 u16 mpdu_proc; 2442 u16 cma0_dma; 2443 u16 cma1_dma; 2444 u16 bb_rpt; 2445 u16 wd_rel; 2446 u16 cpu_io; 2447 u16 tx_rpt; 2448 }; 2449 2450 struct rtw89_dle_mem { 2451 enum rtw89_qta_mode mode; 2452 const struct rtw89_dle_size *wde_size; 2453 const struct rtw89_dle_size *ple_size; 2454 const struct rtw89_wde_quota *wde_min_qt; 2455 const struct rtw89_wde_quota *wde_max_qt; 2456 const struct rtw89_ple_quota *ple_min_qt; 2457 const struct rtw89_ple_quota *ple_max_qt; 2458 }; 2459 2460 struct rtw89_reg_def { 2461 u32 addr; 2462 u32 mask; 2463 }; 2464 2465 struct rtw89_reg2_def { 2466 u32 addr; 2467 u32 data; 2468 }; 2469 2470 struct rtw89_reg3_def { 2471 u32 addr; 2472 u32 mask; 2473 u32 data; 2474 }; 2475 2476 struct rtw89_reg5_def { 2477 u8 flag; /* recognized by parsers */ 2478 u8 path; 2479 u32 addr; 2480 u32 mask; 2481 u32 data; 2482 }; 2483 2484 struct rtw89_phy_table { 2485 const struct rtw89_reg2_def *regs; 2486 u32 n_regs; 2487 enum rtw89_rf_path rf_path; 2488 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 2489 enum rtw89_rf_path rf_path, void *data); 2490 }; 2491 2492 struct rtw89_txpwr_table { 2493 const void *data; 2494 u32 size; 2495 void (*load)(struct rtw89_dev *rtwdev, 2496 const struct rtw89_txpwr_table *tbl); 2497 }; 2498 2499 struct rtw89_page_regs { 2500 u32 hci_fc_ctrl; 2501 u32 ch_page_ctrl; 2502 u32 ach_page_ctrl; 2503 u32 ach_page_info; 2504 u32 pub_page_info3; 2505 u32 pub_page_ctrl1; 2506 u32 pub_page_ctrl2; 2507 u32 pub_page_info1; 2508 u32 pub_page_info2; 2509 u32 wp_page_ctrl1; 2510 u32 wp_page_ctrl2; 2511 u32 wp_page_info1; 2512 }; 2513 2514 struct rtw89_imr_info { 2515 u32 wdrls_imr_set; 2516 u32 wsec_imr_reg; 2517 u32 wsec_imr_set; 2518 u32 mpdu_tx_imr_set; 2519 u32 mpdu_rx_imr_set; 2520 u32 sta_sch_imr_set; 2521 u32 txpktctl_imr_b0_reg; 2522 u32 txpktctl_imr_b0_clr; 2523 u32 txpktctl_imr_b0_set; 2524 u32 txpktctl_imr_b1_reg; 2525 u32 txpktctl_imr_b1_clr; 2526 u32 txpktctl_imr_b1_set; 2527 u32 wde_imr_clr; 2528 u32 wde_imr_set; 2529 u32 ple_imr_clr; 2530 u32 ple_imr_set; 2531 u32 host_disp_imr_clr; 2532 u32 host_disp_imr_set; 2533 u32 cpu_disp_imr_clr; 2534 u32 cpu_disp_imr_set; 2535 u32 other_disp_imr_clr; 2536 u32 other_disp_imr_set; 2537 u32 bbrpt_chinfo_err_imr_reg; 2538 u32 bbrpt_err_imr_set; 2539 u32 bbrpt_dfs_err_imr_reg; 2540 u32 ptcl_imr_clr; 2541 u32 ptcl_imr_set; 2542 u32 cdma_imr_0_reg; 2543 u32 cdma_imr_0_clr; 2544 u32 cdma_imr_0_set; 2545 u32 cdma_imr_1_reg; 2546 u32 cdma_imr_1_clr; 2547 u32 cdma_imr_1_set; 2548 u32 phy_intf_imr_reg; 2549 u32 phy_intf_imr_clr; 2550 u32 phy_intf_imr_set; 2551 u32 rmac_imr_reg; 2552 u32 rmac_imr_clr; 2553 u32 rmac_imr_set; 2554 u32 tmac_imr_reg; 2555 u32 tmac_imr_clr; 2556 u32 tmac_imr_set; 2557 }; 2558 2559 struct rtw89_chip_info { 2560 enum rtw89_core_chip_id chip_id; 2561 const struct rtw89_chip_ops *ops; 2562 const char *fw_name; 2563 u32 fifo_size; 2564 u16 max_amsdu_limit; 2565 bool dis_2g_40m_ul_ofdma; 2566 u32 rsvd_ple_ofst; 2567 const struct rtw89_hfc_param_ini *hfc_param_ini; 2568 const struct rtw89_dle_mem *dle_mem; 2569 u32 rf_base_addr[2]; 2570 u8 support_chanctx_num; 2571 u8 support_bands; 2572 bool support_bw160; 2573 bool hw_sec_hdr; 2574 u8 rf_path_num; 2575 u8 tx_nss; 2576 u8 rx_nss; 2577 u8 acam_num; 2578 u8 bcam_num; 2579 u8 scam_num; 2580 u8 bacam_num; 2581 u8 bacam_dynamic_num; 2582 bool bacam_v1; 2583 2584 u8 sec_ctrl_efuse_size; 2585 u32 physical_efuse_size; 2586 u32 logical_efuse_size; 2587 u32 limit_efuse_size; 2588 u32 dav_phy_efuse_size; 2589 u32 dav_log_efuse_size; 2590 u32 phycap_addr; 2591 u32 phycap_size; 2592 2593 const struct rtw89_pwr_cfg * const *pwr_on_seq; 2594 const struct rtw89_pwr_cfg * const *pwr_off_seq; 2595 const struct rtw89_phy_table *bb_table; 2596 const struct rtw89_phy_table *bb_gain_table; 2597 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 2598 const struct rtw89_phy_table *nctl_table; 2599 const struct rtw89_txpwr_table *byr_table; 2600 const struct rtw89_phy_dig_gain_table *dig_table; 2601 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 2602 const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 2603 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2604 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2605 const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 2606 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2607 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2608 const s8 (*txpwr_lmt_6g)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 2609 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2610 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2611 const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2612 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2613 const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2614 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2615 const s8 (*txpwr_lmt_ru_6g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2616 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2617 2618 u8 txpwr_factor_rf; 2619 u8 txpwr_factor_mac; 2620 2621 u32 para_ver; 2622 u32 wlcx_desired; 2623 u8 btcx_desired; 2624 u8 scbd; 2625 u8 mailbox; 2626 2627 u8 fcxbtcrpt_ver; 2628 u8 fcxtdma_ver; 2629 u8 fcxslots_ver; 2630 u8 fcxcysta_ver; 2631 u8 fcxstep_ver; 2632 u8 fcxnullsta_ver; 2633 u8 fcxmreg_ver; 2634 u8 fcxgpiodbg_ver; 2635 u8 fcxbtver_ver; 2636 u8 fcxbtscan_ver; 2637 u8 fcxbtafh_ver; 2638 u8 fcxbtdevinfo_ver; 2639 2640 u8 afh_guard_ch; 2641 const u8 *wl_rssi_thres; 2642 const u8 *bt_rssi_thres; 2643 u8 rssi_tol; 2644 2645 u8 mon_reg_num; 2646 const struct rtw89_btc_fbtc_mreg *mon_reg; 2647 u8 rf_para_ulink_num; 2648 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 2649 u8 rf_para_dlink_num; 2650 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 2651 u8 ps_mode_supported; 2652 u8 low_power_hci_modes; 2653 2654 u32 h2c_cctl_func_id; 2655 u32 hci_func_en_addr; 2656 u32 h2c_desc_size; 2657 u32 txwd_body_size; 2658 u32 h2c_ctrl_reg; 2659 const u32 *h2c_regs; 2660 u32 c2h_ctrl_reg; 2661 const u32 *c2h_regs; 2662 const struct rtw89_page_regs *page_regs; 2663 const struct rtw89_reg_def *dcfo_comp; 2664 u8 dcfo_comp_sft; 2665 const struct rtw89_imr_info *imr_info; 2666 }; 2667 2668 union rtw89_bus_info { 2669 const struct rtw89_pci_info *pci; 2670 }; 2671 2672 struct rtw89_driver_info { 2673 const struct rtw89_chip_info *chip; 2674 union rtw89_bus_info bus; 2675 }; 2676 2677 enum rtw89_hcifc_mode { 2678 RTW89_HCIFC_POH = 0, 2679 RTW89_HCIFC_STF = 1, 2680 RTW89_HCIFC_SDIO = 2, 2681 2682 /* keep last */ 2683 RTW89_HCIFC_MODE_INVALID, 2684 }; 2685 2686 struct rtw89_dle_info { 2687 enum rtw89_qta_mode qta_mode; 2688 u16 wde_pg_size; 2689 u16 ple_pg_size; 2690 u16 c0_rx_qta; 2691 u16 c1_rx_qta; 2692 }; 2693 2694 enum rtw89_host_rpr_mode { 2695 RTW89_RPR_MODE_POH = 0, 2696 RTW89_RPR_MODE_STF 2697 }; 2698 2699 struct rtw89_mac_info { 2700 struct rtw89_dle_info dle_info; 2701 struct rtw89_hfc_param hfc_param; 2702 enum rtw89_qta_mode qta_mode; 2703 u8 rpwm_seq_num; 2704 u8 cpwm_seq_num; 2705 }; 2706 2707 enum rtw89_fw_type { 2708 RTW89_FW_NORMAL = 1, 2709 RTW89_FW_WOWLAN = 3, 2710 }; 2711 2712 enum rtw89_fw_feature { 2713 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 2714 RTW89_FW_FEATURE_SCAN_OFFLOAD, 2715 RTW89_FW_FEATURE_TX_WAKE, 2716 RTW89_FW_FEATURE_CRASH_TRIGGER, 2717 }; 2718 2719 struct rtw89_fw_suit { 2720 const u8 *data; 2721 u32 size; 2722 u8 major_ver; 2723 u8 minor_ver; 2724 u8 sub_ver; 2725 u8 sub_idex; 2726 u16 build_year; 2727 u16 build_mon; 2728 u16 build_date; 2729 u16 build_hour; 2730 u16 build_min; 2731 u8 cmd_ver; 2732 }; 2733 2734 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 2735 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 2736 #define RTW89_FW_SUIT_VER_CODE(s) \ 2737 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 2738 2739 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 2740 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 2741 (mfw_hdr)->ver.minor, \ 2742 (mfw_hdr)->ver.sub, \ 2743 (mfw_hdr)->ver.idx) 2744 2745 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 2746 RTW89_FW_VER_CODE(GET_FW_HDR_MAJOR_VERSION(fw_hdr), \ 2747 GET_FW_HDR_MINOR_VERSION(fw_hdr), \ 2748 GET_FW_HDR_SUBVERSION(fw_hdr), \ 2749 GET_FW_HDR_SUBINDEX(fw_hdr)) 2750 2751 struct rtw89_fw_info { 2752 const struct firmware *firmware; 2753 struct rtw89_dev *rtwdev; 2754 struct completion completion; 2755 u8 h2c_seq; 2756 u8 rec_seq; 2757 struct rtw89_fw_suit normal; 2758 struct rtw89_fw_suit wowlan; 2759 bool fw_log_enable; 2760 u32 feature_map; 2761 }; 2762 2763 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 2764 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 2765 2766 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 2767 ((_fw)->feature_map |= BIT(_fw_feature)) 2768 2769 struct rtw89_cam_info { 2770 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 2771 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 2772 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 2773 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 2774 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 2775 }; 2776 2777 enum rtw89_sar_sources { 2778 RTW89_SAR_SOURCE_NONE, 2779 RTW89_SAR_SOURCE_COMMON, 2780 2781 RTW89_SAR_SOURCE_NR, 2782 }; 2783 2784 enum rtw89_sar_subband { 2785 RTW89_SAR_2GHZ_SUBBAND, 2786 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 2787 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 2788 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 2789 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 2790 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 2791 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 2792 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 2793 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 2794 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 2795 2796 RTW89_SAR_SUBBAND_NR, 2797 }; 2798 2799 struct rtw89_sar_cfg_common { 2800 bool set[RTW89_SAR_SUBBAND_NR]; 2801 s32 cfg[RTW89_SAR_SUBBAND_NR]; 2802 }; 2803 2804 struct rtw89_sar_info { 2805 /* used to decide how to acces SAR cfg union */ 2806 enum rtw89_sar_sources src; 2807 2808 /* reserved for different knids of SAR cfg struct. 2809 * supposed that a single cfg struct cannot handle various SAR sources. 2810 */ 2811 union { 2812 struct rtw89_sar_cfg_common cfg_common; 2813 }; 2814 }; 2815 2816 struct rtw89_chanctx_cfg { 2817 enum rtw89_sub_entity_idx idx; 2818 }; 2819 2820 enum rtw89_entity_mode { 2821 RTW89_ENTITY_MODE_SCC, 2822 }; 2823 2824 struct rtw89_hal { 2825 u32 rx_fltr; 2826 u8 cv; 2827 u32 sw_amsdu_max_size; 2828 u32 antenna_tx; 2829 u32 antenna_rx; 2830 u8 tx_nss; 2831 u8 rx_nss; 2832 bool support_cckpd; 2833 bool support_igi; 2834 2835 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 2836 struct cfg80211_chan_def chandef[NUM_OF_RTW89_SUB_ENTITY]; 2837 2838 bool entity_active; 2839 enum rtw89_entity_mode entity_mode; 2840 2841 struct rtw89_chan chan[NUM_OF_RTW89_SUB_ENTITY]; 2842 struct rtw89_chan_rcd chan_rcd[NUM_OF_RTW89_SUB_ENTITY]; 2843 }; 2844 2845 #define RTW89_MAX_MAC_ID_NUM 128 2846 #define RTW89_MAX_PKT_OFLD_NUM 255 2847 2848 enum rtw89_flags { 2849 RTW89_FLAG_POWERON, 2850 RTW89_FLAG_FW_RDY, 2851 RTW89_FLAG_RUNNING, 2852 RTW89_FLAG_BFEE_MON, 2853 RTW89_FLAG_BFEE_EN, 2854 RTW89_FLAG_NAPI_RUNNING, 2855 RTW89_FLAG_LEISURE_PS, 2856 RTW89_FLAG_LOW_POWER_MODE, 2857 RTW89_FLAG_INACTIVE_PS, 2858 RTW89_FLAG_RESTART_TRIGGER, 2859 2860 NUM_OF_RTW89_FLAGS, 2861 }; 2862 2863 struct rtw89_pkt_stat { 2864 u16 beacon_nr; 2865 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 2866 }; 2867 2868 DECLARE_EWMA(thermal, 4, 4); 2869 2870 struct rtw89_phy_stat { 2871 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 2872 struct rtw89_pkt_stat cur_pkt_stat; 2873 struct rtw89_pkt_stat last_pkt_stat; 2874 }; 2875 2876 #define RTW89_DACK_PATH_NR 2 2877 #define RTW89_DACK_IDX_NR 2 2878 #define RTW89_DACK_MSBK_NR 16 2879 struct rtw89_dack_info { 2880 bool dack_done; 2881 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 2882 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2883 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2884 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2885 u32 dack_cnt; 2886 bool addck_timeout[RTW89_DACK_PATH_NR]; 2887 bool dadck_timeout[RTW89_DACK_PATH_NR]; 2888 bool msbk_timeout[RTW89_DACK_PATH_NR]; 2889 }; 2890 2891 #define RTW89_IQK_CHS_NR 2 2892 #define RTW89_IQK_PATH_NR 4 2893 2894 struct rtw89_mcc_info { 2895 u8 ch[RTW89_IQK_CHS_NR]; 2896 u8 band[RTW89_IQK_CHS_NR]; 2897 u8 table_idx; 2898 }; 2899 2900 struct rtw89_lck_info { 2901 u8 thermal[RF_PATH_MAX]; 2902 }; 2903 2904 struct rtw89_rx_dck_info { 2905 u8 thermal[RF_PATH_MAX]; 2906 }; 2907 2908 struct rtw89_iqk_info { 2909 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2910 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2911 bool lok_fail[RTW89_IQK_PATH_NR]; 2912 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2913 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2914 u32 iqk_fail_cnt; 2915 bool is_iqk_init; 2916 u32 iqk_channel[RTW89_IQK_CHS_NR]; 2917 u8 iqk_band[RTW89_IQK_PATH_NR]; 2918 u8 iqk_ch[RTW89_IQK_PATH_NR]; 2919 u8 iqk_bw[RTW89_IQK_PATH_NR]; 2920 u8 kcount; 2921 u8 iqk_times; 2922 u8 version; 2923 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 2924 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 2925 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 2926 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 2927 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 2928 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 2929 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 2930 bool is_nbiqk; 2931 bool iqk_fft_en; 2932 bool iqk_xym_en; 2933 bool iqk_sram_en; 2934 bool iqk_cfir_en; 2935 u8 thermal[RTW89_IQK_PATH_NR]; 2936 bool thermal_rek_en; 2937 u32 syn1to2; 2938 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2939 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 2940 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2941 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2942 }; 2943 2944 #define RTW89_DPK_RF_PATH 2 2945 #define RTW89_DPK_AVG_THERMAL_NUM 8 2946 #define RTW89_DPK_BKUP_NUM 2 2947 struct rtw89_dpk_bkup_para { 2948 enum rtw89_band band; 2949 enum rtw89_bandwidth bw; 2950 u8 ch; 2951 bool path_ok; 2952 u8 mdpd_en; 2953 u8 txagc_dpk; 2954 u8 ther_dpk; 2955 u8 gs; 2956 u16 pwsf; 2957 }; 2958 2959 struct rtw89_dpk_info { 2960 bool is_dpk_enable; 2961 bool is_dpk_reload_en; 2962 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2963 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2964 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2965 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2966 u8 cur_idx[RTW89_DPK_RF_PATH]; 2967 u8 cur_k_set; 2968 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2969 }; 2970 2971 struct rtw89_fem_info { 2972 bool elna_2g; 2973 bool elna_5g; 2974 bool epa_2g; 2975 bool epa_5g; 2976 bool epa_6g; 2977 }; 2978 2979 struct rtw89_phy_ch_info { 2980 u8 rssi_min; 2981 u16 rssi_min_macid; 2982 u8 pre_rssi_min; 2983 u8 rssi_max; 2984 u16 rssi_max_macid; 2985 u8 rxsc_160; 2986 u8 rxsc_80; 2987 u8 rxsc_40; 2988 u8 rxsc_20; 2989 u8 rxsc_l; 2990 u8 is_noisy; 2991 }; 2992 2993 struct rtw89_agc_gaincode_set { 2994 u8 lna_idx; 2995 u8 tia_idx; 2996 u8 rxb_idx; 2997 }; 2998 2999 #define IGI_RSSI_TH_NUM 5 3000 #define FA_TH_NUM 4 3001 #define LNA_GAIN_NUM 7 3002 #define TIA_GAIN_NUM 2 3003 struct rtw89_dig_info { 3004 struct rtw89_agc_gaincode_set cur_gaincode; 3005 bool force_gaincode_idx_en; 3006 struct rtw89_agc_gaincode_set force_gaincode; 3007 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 3008 u16 fa_th[FA_TH_NUM]; 3009 u8 igi_rssi; 3010 u8 igi_fa_rssi; 3011 u8 fa_rssi_ofst; 3012 u8 dyn_igi_max; 3013 u8 dyn_igi_min; 3014 bool dyn_pd_th_en; 3015 u8 dyn_pd_th_max; 3016 u8 pd_low_th_ofst; 3017 u8 ib_pbk; 3018 s8 ib_pkpwr; 3019 s8 lna_gain_a[LNA_GAIN_NUM]; 3020 s8 lna_gain_g[LNA_GAIN_NUM]; 3021 s8 *lna_gain; 3022 s8 tia_gain_a[TIA_GAIN_NUM]; 3023 s8 tia_gain_g[TIA_GAIN_NUM]; 3024 s8 *tia_gain; 3025 bool is_linked_pre; 3026 bool bypass_dig; 3027 }; 3028 3029 enum rtw89_multi_cfo_mode { 3030 RTW89_PKT_BASED_AVG_MODE = 0, 3031 RTW89_ENTRY_BASED_AVG_MODE = 1, 3032 RTW89_TP_BASED_AVG_MODE = 2, 3033 }; 3034 3035 enum rtw89_phy_cfo_status { 3036 RTW89_PHY_DCFO_STATE_NORMAL = 0, 3037 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 3038 RTW89_PHY_DCFO_STATE_HOLD = 2, 3039 RTW89_PHY_DCFO_STATE_MAX 3040 }; 3041 3042 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 3043 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 3044 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 3045 }; 3046 3047 struct rtw89_cfo_tracking_info { 3048 u16 cfo_timer_ms; 3049 bool cfo_trig_by_timer_en; 3050 enum rtw89_phy_cfo_status phy_cfo_status; 3051 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 3052 u8 phy_cfo_trk_cnt; 3053 bool is_adjust; 3054 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 3055 bool apply_compensation; 3056 u8 crystal_cap; 3057 u8 crystal_cap_default; 3058 u8 def_x_cap; 3059 s8 x_cap_ofst; 3060 u32 sta_cfo_tolerance; 3061 s32 cfo_tail[CFO_TRACK_MAX_USER]; 3062 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 3063 s32 cfo_avg_pre; 3064 s32 cfo_avg[CFO_TRACK_MAX_USER]; 3065 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 3066 u32 packet_count; 3067 u32 packet_count_pre; 3068 s32 residual_cfo_acc; 3069 u8 phy_cfotrk_state; 3070 u8 phy_cfotrk_cnt; 3071 bool divergence_lock_en; 3072 u8 x_cap_lb; 3073 u8 x_cap_ub; 3074 u8 lock_cnt; 3075 }; 3076 3077 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 3078 #define TSSI_TRIM_CH_GROUP_NUM 8 3079 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 3080 3081 #define TSSI_CCK_CH_GROUP_NUM 6 3082 #define TSSI_MCS_2G_CH_GROUP_NUM 5 3083 #define TSSI_MCS_5G_CH_GROUP_NUM 14 3084 #define TSSI_MCS_6G_CH_GROUP_NUM 32 3085 #define TSSI_MCS_CH_GROUP_NUM \ 3086 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 3087 3088 struct rtw89_tssi_info { 3089 u8 thermal[RF_PATH_MAX]; 3090 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 3091 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 3092 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 3093 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 3094 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 3095 s8 extra_ofst[RF_PATH_MAX]; 3096 bool tssi_tracking_check[RF_PATH_MAX]; 3097 u8 default_txagc_offset[RF_PATH_MAX]; 3098 u32 base_thermal[RF_PATH_MAX]; 3099 }; 3100 3101 struct rtw89_power_trim_info { 3102 bool pg_thermal_trim; 3103 bool pg_pa_bias_trim; 3104 u8 thermal_trim[RF_PATH_MAX]; 3105 u8 pa_bias_trim[RF_PATH_MAX]; 3106 }; 3107 3108 struct rtw89_regulatory { 3109 char alpha2[3]; 3110 u8 txpwr_regd[RTW89_BAND_MAX]; 3111 }; 3112 3113 enum rtw89_ifs_clm_application { 3114 RTW89_IFS_CLM_INIT = 0, 3115 RTW89_IFS_CLM_BACKGROUND = 1, 3116 RTW89_IFS_CLM_ACS = 2, 3117 RTW89_IFS_CLM_DIG = 3, 3118 RTW89_IFS_CLM_TDMA_DIG = 4, 3119 RTW89_IFS_CLM_DBG = 5, 3120 RTW89_IFS_CLM_DBG_MANUAL = 6 3121 }; 3122 3123 enum rtw89_env_racing_lv { 3124 RTW89_RAC_RELEASE = 0, 3125 RTW89_RAC_LV_1 = 1, 3126 RTW89_RAC_LV_2 = 2, 3127 RTW89_RAC_LV_3 = 3, 3128 RTW89_RAC_LV_4 = 4, 3129 RTW89_RAC_MAX_NUM = 5 3130 }; 3131 3132 struct rtw89_ccx_para_info { 3133 enum rtw89_env_racing_lv rac_lv; 3134 u16 mntr_time; 3135 u8 nhm_manual_th_ofst; 3136 u8 nhm_manual_th0; 3137 enum rtw89_ifs_clm_application ifs_clm_app; 3138 u32 ifs_clm_manual_th_times; 3139 u32 ifs_clm_manual_th0; 3140 u8 fahm_manual_th_ofst; 3141 u8 fahm_manual_th0; 3142 u8 fahm_numer_opt; 3143 u8 fahm_denom_opt; 3144 }; 3145 3146 enum rtw89_ccx_edcca_opt_sc_idx { 3147 RTW89_CCX_EDCCA_SEG0_P0 = 0, 3148 RTW89_CCX_EDCCA_SEG0_S1 = 1, 3149 RTW89_CCX_EDCCA_SEG0_S2 = 2, 3150 RTW89_CCX_EDCCA_SEG0_S3 = 3, 3151 RTW89_CCX_EDCCA_SEG1_P0 = 4, 3152 RTW89_CCX_EDCCA_SEG1_S1 = 5, 3153 RTW89_CCX_EDCCA_SEG1_S2 = 6, 3154 RTW89_CCX_EDCCA_SEG1_S3 = 7 3155 }; 3156 3157 enum rtw89_ccx_edcca_opt_bw_idx { 3158 RTW89_CCX_EDCCA_BW20_0 = 0, 3159 RTW89_CCX_EDCCA_BW20_1 = 1, 3160 RTW89_CCX_EDCCA_BW20_2 = 2, 3161 RTW89_CCX_EDCCA_BW20_3 = 3, 3162 RTW89_CCX_EDCCA_BW20_4 = 4, 3163 RTW89_CCX_EDCCA_BW20_5 = 5, 3164 RTW89_CCX_EDCCA_BW20_6 = 6, 3165 RTW89_CCX_EDCCA_BW20_7 = 7 3166 }; 3167 3168 #define RTW89_NHM_TH_NUM 11 3169 #define RTW89_FAHM_TH_NUM 11 3170 #define RTW89_NHM_RPT_NUM 12 3171 #define RTW89_FAHM_RPT_NUM 12 3172 #define RTW89_IFS_CLM_NUM 4 3173 struct rtw89_env_monitor_info { 3174 u32 ccx_trigger_time; 3175 u64 start_time; 3176 u8 ccx_rpt_stamp; 3177 u8 ccx_watchdog_result; 3178 bool ccx_ongoing; 3179 u8 ccx_rac_lv; 3180 bool ccx_manual_ctrl; 3181 u8 ccx_pre_rssi; 3182 u16 clm_mntr_time; 3183 u16 nhm_mntr_time; 3184 u16 ifs_clm_mntr_time; 3185 enum rtw89_ifs_clm_application ifs_clm_app; 3186 u16 fahm_mntr_time; 3187 u16 edcca_clm_mntr_time; 3188 u16 ccx_period; 3189 u8 ccx_unit_idx; 3190 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; 3191 u8 nhm_th[RTW89_NHM_TH_NUM]; 3192 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 3193 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 3194 u8 fahm_numer_opt; 3195 u8 fahm_denom_opt; 3196 u8 fahm_th[RTW89_FAHM_TH_NUM]; 3197 u16 clm_result; 3198 u16 nhm_result[RTW89_NHM_RPT_NUM]; 3199 u8 nhm_wgt[RTW89_NHM_RPT_NUM]; 3200 u16 nhm_tx_cnt; 3201 u16 nhm_cca_cnt; 3202 u16 nhm_idle_cnt; 3203 u16 ifs_clm_tx; 3204 u16 ifs_clm_edcca_excl_cca; 3205 u16 ifs_clm_ofdmfa; 3206 u16 ifs_clm_ofdmcca_excl_fa; 3207 u16 ifs_clm_cckfa; 3208 u16 ifs_clm_cckcca_excl_fa; 3209 u16 ifs_clm_total_ifs; 3210 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 3211 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 3212 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 3213 u16 fahm_result[RTW89_FAHM_RPT_NUM]; 3214 u16 fahm_denom_result; 3215 u16 edcca_clm_result; 3216 u8 clm_ratio; 3217 u8 nhm_rpt[RTW89_NHM_RPT_NUM]; 3218 u8 nhm_tx_ratio; 3219 u8 nhm_cca_ratio; 3220 u8 nhm_idle_ratio; 3221 u8 nhm_ratio; 3222 u16 nhm_result_sum; 3223 u8 nhm_pwr; 3224 u8 ifs_clm_tx_ratio; 3225 u8 ifs_clm_edcca_excl_cca_ratio; 3226 u8 ifs_clm_cck_fa_ratio; 3227 u8 ifs_clm_ofdm_fa_ratio; 3228 u8 ifs_clm_cck_cca_excl_fa_ratio; 3229 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 3230 u16 ifs_clm_cck_fa_permil; 3231 u16 ifs_clm_ofdm_fa_permil; 3232 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 3233 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 3234 u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; 3235 u16 fahm_result_sum; 3236 u8 fahm_ratio; 3237 u8 fahm_denom_ratio; 3238 u8 fahm_pwr; 3239 u8 edcca_clm_ratio; 3240 }; 3241 3242 enum rtw89_ser_rcvy_step { 3243 RTW89_SER_DRV_STOP_TX, 3244 RTW89_SER_DRV_STOP_RX, 3245 RTW89_SER_DRV_STOP_RUN, 3246 RTW89_SER_HAL_STOP_DMA, 3247 RTW89_NUM_OF_SER_FLAGS 3248 }; 3249 3250 struct rtw89_ser { 3251 u8 state; 3252 u8 alarm_event; 3253 3254 struct work_struct ser_hdl_work; 3255 struct delayed_work ser_alarm_work; 3256 const struct state_ent *st_tbl; 3257 const struct event_ent *ev_tbl; 3258 struct list_head msg_q; 3259 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 3260 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 3261 }; 3262 3263 enum rtw89_mac_ax_ps_mode { 3264 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 3265 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 3266 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 3267 RTW89_MAC_AX_PS_MODE_MAX = 3, 3268 }; 3269 3270 enum rtw89_last_rpwm_mode { 3271 RTW89_LAST_RPWM_PS = 0x0, 3272 RTW89_LAST_RPWM_ACTIVE = 0x6, 3273 }; 3274 3275 struct rtw89_lps_parm { 3276 u8 macid; 3277 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 3278 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 3279 }; 3280 3281 struct rtw89_ppdu_sts_info { 3282 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 3283 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 3284 }; 3285 3286 struct rtw89_early_h2c { 3287 struct list_head list; 3288 u8 *h2c; 3289 u16 h2c_len; 3290 }; 3291 3292 struct rtw89_hw_scan_info { 3293 struct ieee80211_vif *scanning_vif; 3294 struct list_head pkt_list[NUM_NL80211_BANDS]; 3295 u8 op_pri_ch; 3296 u8 op_chan; 3297 u8 op_bw; 3298 u8 op_band; 3299 }; 3300 3301 enum rtw89_phy_bb_gain_band { 3302 RTW89_BB_GAIN_BAND_2G = 0, 3303 RTW89_BB_GAIN_BAND_5G_L = 1, 3304 RTW89_BB_GAIN_BAND_5G_M = 2, 3305 RTW89_BB_GAIN_BAND_5G_H = 3, 3306 RTW89_BB_GAIN_BAND_6G_L = 4, 3307 RTW89_BB_GAIN_BAND_6G_M = 5, 3308 RTW89_BB_GAIN_BAND_6G_H = 6, 3309 RTW89_BB_GAIN_BAND_6G_UH = 7, 3310 3311 RTW89_BB_GAIN_BAND_NR, 3312 }; 3313 3314 enum rtw89_phy_bb_rxsc_num { 3315 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 3316 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 3317 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 3318 }; 3319 3320 struct rtw89_phy_bb_gain_info { 3321 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3322 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 3323 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3324 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3325 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3326 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 3327 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 3328 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3329 [RTW89_BB_RXSC_NUM_40]; 3330 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3331 [RTW89_BB_RXSC_NUM_80]; 3332 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3333 [RTW89_BB_RXSC_NUM_160]; 3334 }; 3335 3336 struct rtw89_phy_efuse_gain { 3337 bool offset_valid; 3338 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 3339 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 3340 }; 3341 3342 struct rtw89_dev { 3343 struct ieee80211_hw *hw; 3344 struct device *dev; 3345 const struct ieee80211_ops *ops; 3346 3347 bool dbcc_en; 3348 struct rtw89_hw_scan_info scan_info; 3349 const struct rtw89_chip_info *chip; 3350 const struct rtw89_pci_info *pci_info; 3351 struct rtw89_hal hal; 3352 struct rtw89_mac_info mac; 3353 struct rtw89_fw_info fw; 3354 struct rtw89_hci_info hci; 3355 struct rtw89_efuse efuse; 3356 struct rtw89_traffic_stats stats; 3357 3358 /* ensures exclusive access from mac80211 callbacks */ 3359 struct mutex mutex; 3360 struct list_head rtwvifs_list; 3361 /* used to protect rf read write */ 3362 struct mutex rf_mutex; 3363 struct workqueue_struct *txq_wq; 3364 struct work_struct txq_work; 3365 struct delayed_work txq_reinvoke_work; 3366 /* used to protect ba_list and forbid_ba_list */ 3367 spinlock_t ba_lock; 3368 /* txqs to setup ba session */ 3369 struct list_head ba_list; 3370 /* txqs to forbid ba session */ 3371 struct list_head forbid_ba_list; 3372 struct work_struct ba_work; 3373 /* used to protect rpwm */ 3374 spinlock_t rpwm_lock; 3375 3376 struct rtw89_cam_info cam_info; 3377 3378 struct sk_buff_head c2h_queue; 3379 struct work_struct c2h_work; 3380 struct work_struct ips_work; 3381 3382 struct list_head early_h2c_list; 3383 3384 struct rtw89_ser ser; 3385 3386 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 3387 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 3388 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 3389 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 3390 3391 struct rtw89_phy_stat phystat; 3392 struct rtw89_dack_info dack; 3393 struct rtw89_iqk_info iqk; 3394 struct rtw89_dpk_info dpk; 3395 struct rtw89_mcc_info mcc; 3396 struct rtw89_lck_info lck; 3397 struct rtw89_rx_dck_info rx_dck; 3398 bool is_tssi_mode[RF_PATH_MAX]; 3399 bool is_bt_iqk_timeout; 3400 3401 struct rtw89_fem_info fem; 3402 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; 3403 struct rtw89_tssi_info tssi; 3404 struct rtw89_power_trim_info pwr_trim; 3405 3406 struct rtw89_cfo_tracking_info cfo_tracking; 3407 struct rtw89_env_monitor_info env_monitor; 3408 struct rtw89_dig_info dig; 3409 struct rtw89_phy_ch_info ch_info; 3410 struct rtw89_phy_bb_gain_info bb_gain; 3411 struct rtw89_phy_efuse_gain efuse_gain; 3412 3413 struct delayed_work track_work; 3414 struct delayed_work coex_act1_work; 3415 struct delayed_work coex_bt_devinfo_work; 3416 struct delayed_work coex_rfk_chk_work; 3417 struct delayed_work cfo_track_work; 3418 struct delayed_work forbid_ba_work; 3419 struct rtw89_ppdu_sts_info ppdu_sts; 3420 u8 total_sta_assoc; 3421 bool scanning; 3422 3423 const struct rtw89_regulatory *regd; 3424 struct rtw89_sar_info sar; 3425 3426 struct rtw89_btc btc; 3427 enum rtw89_ps_mode ps_mode; 3428 bool lps_enabled; 3429 3430 /* napi structure */ 3431 struct net_device netdev; 3432 struct napi_struct napi; 3433 int napi_budget_countdown; 3434 3435 /* HCI related data, keep last */ 3436 u8 priv[] __aligned(sizeof(void *)); 3437 }; 3438 3439 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 3440 struct rtw89_core_tx_request *tx_req) 3441 { 3442 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 3443 } 3444 3445 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 3446 { 3447 rtwdev->hci.ops->reset(rtwdev); 3448 } 3449 3450 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 3451 { 3452 return rtwdev->hci.ops->start(rtwdev); 3453 } 3454 3455 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 3456 { 3457 rtwdev->hci.ops->stop(rtwdev); 3458 } 3459 3460 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 3461 { 3462 return rtwdev->hci.ops->deinit(rtwdev); 3463 } 3464 3465 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 3466 { 3467 rtwdev->hci.ops->pause(rtwdev, pause); 3468 } 3469 3470 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 3471 { 3472 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 3473 } 3474 3475 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 3476 { 3477 rtwdev->hci.ops->recalc_int_mit(rtwdev); 3478 } 3479 3480 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 3481 { 3482 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 3483 } 3484 3485 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 3486 { 3487 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 3488 } 3489 3490 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 3491 bool drop) 3492 { 3493 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3494 return; 3495 3496 if (rtwdev->hci.ops->flush_queues) 3497 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 3498 } 3499 3500 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 3501 { 3502 if (rtwdev->hci.ops->recovery_start) 3503 rtwdev->hci.ops->recovery_start(rtwdev); 3504 } 3505 3506 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 3507 { 3508 if (rtwdev->hci.ops->recovery_complete) 3509 rtwdev->hci.ops->recovery_complete(rtwdev); 3510 } 3511 3512 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 3513 { 3514 return rtwdev->hci.ops->read8(rtwdev, addr); 3515 } 3516 3517 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 3518 { 3519 return rtwdev->hci.ops->read16(rtwdev, addr); 3520 } 3521 3522 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 3523 { 3524 return rtwdev->hci.ops->read32(rtwdev, addr); 3525 } 3526 3527 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 3528 { 3529 rtwdev->hci.ops->write8(rtwdev, addr, data); 3530 } 3531 3532 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 3533 { 3534 rtwdev->hci.ops->write16(rtwdev, addr, data); 3535 } 3536 3537 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 3538 { 3539 rtwdev->hci.ops->write32(rtwdev, addr, data); 3540 } 3541 3542 static inline void 3543 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3544 { 3545 u8 val; 3546 3547 val = rtw89_read8(rtwdev, addr); 3548 rtw89_write8(rtwdev, addr, val | bit); 3549 } 3550 3551 static inline void 3552 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3553 { 3554 u16 val; 3555 3556 val = rtw89_read16(rtwdev, addr); 3557 rtw89_write16(rtwdev, addr, val | bit); 3558 } 3559 3560 static inline void 3561 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3562 { 3563 u32 val; 3564 3565 val = rtw89_read32(rtwdev, addr); 3566 rtw89_write32(rtwdev, addr, val | bit); 3567 } 3568 3569 static inline void 3570 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3571 { 3572 u8 val; 3573 3574 val = rtw89_read8(rtwdev, addr); 3575 rtw89_write8(rtwdev, addr, val & ~bit); 3576 } 3577 3578 static inline void 3579 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3580 { 3581 u16 val; 3582 3583 val = rtw89_read16(rtwdev, addr); 3584 rtw89_write16(rtwdev, addr, val & ~bit); 3585 } 3586 3587 static inline void 3588 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3589 { 3590 u32 val; 3591 3592 val = rtw89_read32(rtwdev, addr); 3593 rtw89_write32(rtwdev, addr, val & ~bit); 3594 } 3595 3596 static inline u32 3597 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3598 { 3599 u32 shift = __ffs(mask); 3600 u32 orig; 3601 u32 ret; 3602 3603 orig = rtw89_read32(rtwdev, addr); 3604 ret = (orig & mask) >> shift; 3605 3606 return ret; 3607 } 3608 3609 static inline u16 3610 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3611 { 3612 u32 shift = __ffs(mask); 3613 u32 orig; 3614 u32 ret; 3615 3616 orig = rtw89_read16(rtwdev, addr); 3617 ret = (orig & mask) >> shift; 3618 3619 return ret; 3620 } 3621 3622 static inline u8 3623 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3624 { 3625 u32 shift = __ffs(mask); 3626 u32 orig; 3627 u32 ret; 3628 3629 orig = rtw89_read8(rtwdev, addr); 3630 ret = (orig & mask) >> shift; 3631 3632 return ret; 3633 } 3634 3635 static inline void 3636 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 3637 { 3638 u32 shift = __ffs(mask); 3639 u32 orig; 3640 u32 set; 3641 3642 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 3643 3644 orig = rtw89_read32(rtwdev, addr); 3645 set = (orig & ~mask) | ((data << shift) & mask); 3646 rtw89_write32(rtwdev, addr, set); 3647 } 3648 3649 static inline void 3650 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 3651 { 3652 u32 shift; 3653 u16 orig, set; 3654 3655 mask &= 0xffff; 3656 shift = __ffs(mask); 3657 3658 orig = rtw89_read16(rtwdev, addr); 3659 set = (orig & ~mask) | ((data << shift) & mask); 3660 rtw89_write16(rtwdev, addr, set); 3661 } 3662 3663 static inline void 3664 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 3665 { 3666 u32 shift; 3667 u8 orig, set; 3668 3669 mask &= 0xff; 3670 shift = __ffs(mask); 3671 3672 orig = rtw89_read8(rtwdev, addr); 3673 set = (orig & ~mask) | ((data << shift) & mask); 3674 rtw89_write8(rtwdev, addr, set); 3675 } 3676 3677 static inline u32 3678 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3679 u32 addr, u32 mask) 3680 { 3681 u32 val; 3682 3683 mutex_lock(&rtwdev->rf_mutex); 3684 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 3685 mutex_unlock(&rtwdev->rf_mutex); 3686 3687 return val; 3688 } 3689 3690 static inline void 3691 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3692 u32 addr, u32 mask, u32 data) 3693 { 3694 mutex_lock(&rtwdev->rf_mutex); 3695 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 3696 mutex_unlock(&rtwdev->rf_mutex); 3697 } 3698 3699 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 3700 { 3701 void *p = rtwtxq; 3702 3703 return container_of(p, struct ieee80211_txq, drv_priv); 3704 } 3705 3706 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 3707 struct ieee80211_txq *txq) 3708 { 3709 struct rtw89_txq *rtwtxq; 3710 3711 if (!txq) 3712 return; 3713 3714 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3715 INIT_LIST_HEAD(&rtwtxq->list); 3716 } 3717 3718 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 3719 { 3720 void *p = rtwvif; 3721 3722 return container_of(p, struct ieee80211_vif, drv_priv); 3723 } 3724 3725 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 3726 { 3727 void *p = rtwsta; 3728 3729 return container_of(p, struct ieee80211_sta, drv_priv); 3730 } 3731 3732 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 3733 { 3734 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 3735 } 3736 3737 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 3738 { 3739 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 3740 } 3741 3742 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 3743 { 3744 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 3745 return RATE_INFO_BW_160; 3746 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 3747 return RATE_INFO_BW_80; 3748 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 3749 return RATE_INFO_BW_40; 3750 else 3751 return RATE_INFO_BW_20; 3752 } 3753 3754 static inline 3755 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 3756 { 3757 switch (hw_band) { 3758 default: 3759 case RTW89_BAND_2G: 3760 return NL80211_BAND_2GHZ; 3761 case RTW89_BAND_5G: 3762 return NL80211_BAND_5GHZ; 3763 case RTW89_BAND_6G: 3764 return NL80211_BAND_6GHZ; 3765 } 3766 } 3767 3768 static inline 3769 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 3770 { 3771 switch (width) { 3772 default: 3773 WARN(1, "Not support bandwidth %d\n", width); 3774 fallthrough; 3775 case NL80211_CHAN_WIDTH_20_NOHT: 3776 case NL80211_CHAN_WIDTH_20: 3777 return RTW89_CHANNEL_WIDTH_20; 3778 case NL80211_CHAN_WIDTH_40: 3779 return RTW89_CHANNEL_WIDTH_40; 3780 case NL80211_CHAN_WIDTH_80: 3781 return RTW89_CHANNEL_WIDTH_80; 3782 case NL80211_CHAN_WIDTH_160: 3783 return RTW89_CHANNEL_WIDTH_160; 3784 } 3785 } 3786 3787 static inline 3788 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 3789 struct rtw89_sta *rtwsta) 3790 { 3791 if (rtwsta) { 3792 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 3793 3794 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 3795 return &rtwsta->addr_cam; 3796 } 3797 return &rtwvif->addr_cam; 3798 } 3799 3800 static inline 3801 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 3802 struct rtw89_sta *rtwsta) 3803 { 3804 if (rtwsta) { 3805 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 3806 3807 if (sta->tdls) 3808 return &rtwsta->bssid_cam; 3809 } 3810 return &rtwvif->bssid_cam; 3811 } 3812 3813 static inline 3814 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 3815 struct rtw89_channel_help_params *p, 3816 const struct rtw89_chan *chan, 3817 enum rtw89_mac_idx mac_idx, 3818 enum rtw89_phy_idx phy_idx) 3819 { 3820 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 3821 mac_idx, phy_idx); 3822 } 3823 3824 static inline 3825 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 3826 struct rtw89_channel_help_params *p, 3827 const struct rtw89_chan *chan, 3828 enum rtw89_mac_idx mac_idx, 3829 enum rtw89_phy_idx phy_idx) 3830 { 3831 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 3832 mac_idx, phy_idx); 3833 } 3834 3835 static inline 3836 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 3837 enum rtw89_sub_entity_idx idx) 3838 { 3839 struct rtw89_hal *hal = &rtwdev->hal; 3840 3841 return &hal->chandef[idx]; 3842 } 3843 3844 static inline 3845 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 3846 enum rtw89_sub_entity_idx idx) 3847 { 3848 struct rtw89_hal *hal = &rtwdev->hal; 3849 3850 return &hal->chan[idx]; 3851 } 3852 3853 static inline 3854 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 3855 enum rtw89_sub_entity_idx idx) 3856 { 3857 struct rtw89_hal *hal = &rtwdev->hal; 3858 3859 return &hal->chan_rcd[idx]; 3860 } 3861 3862 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 3863 { 3864 const struct rtw89_chip_info *chip = rtwdev->chip; 3865 3866 if (chip->ops->fem_setup) 3867 chip->ops->fem_setup(rtwdev); 3868 } 3869 3870 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 3871 { 3872 const struct rtw89_chip_info *chip = rtwdev->chip; 3873 3874 if (chip->ops->bb_sethw) 3875 chip->ops->bb_sethw(rtwdev); 3876 } 3877 3878 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 3879 { 3880 const struct rtw89_chip_info *chip = rtwdev->chip; 3881 3882 if (chip->ops->rfk_init) 3883 chip->ops->rfk_init(rtwdev); 3884 } 3885 3886 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 3887 { 3888 const struct rtw89_chip_info *chip = rtwdev->chip; 3889 3890 if (chip->ops->rfk_channel) 3891 chip->ops->rfk_channel(rtwdev); 3892 } 3893 3894 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 3895 enum rtw89_phy_idx phy_idx) 3896 { 3897 const struct rtw89_chip_info *chip = rtwdev->chip; 3898 3899 if (chip->ops->rfk_band_changed) 3900 chip->ops->rfk_band_changed(rtwdev, phy_idx); 3901 } 3902 3903 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 3904 { 3905 const struct rtw89_chip_info *chip = rtwdev->chip; 3906 3907 if (chip->ops->rfk_scan) 3908 chip->ops->rfk_scan(rtwdev, start); 3909 } 3910 3911 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 3912 { 3913 const struct rtw89_chip_info *chip = rtwdev->chip; 3914 3915 if (chip->ops->rfk_track) 3916 chip->ops->rfk_track(rtwdev); 3917 } 3918 3919 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 3920 { 3921 const struct rtw89_chip_info *chip = rtwdev->chip; 3922 3923 if (chip->ops->set_txpwr_ctrl) 3924 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 3925 } 3926 3927 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 3928 { 3929 const struct rtw89_chip_info *chip = rtwdev->chip; 3930 3931 if (chip->ops->power_trim) 3932 chip->ops->power_trim(rtwdev); 3933 } 3934 3935 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 3936 enum rtw89_phy_idx phy_idx) 3937 { 3938 const struct rtw89_chip_info *chip = rtwdev->chip; 3939 3940 if (chip->ops->init_txpwr_unit) 3941 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 3942 } 3943 3944 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 3945 enum rtw89_rf_path rf_path) 3946 { 3947 const struct rtw89_chip_info *chip = rtwdev->chip; 3948 3949 if (!chip->ops->get_thermal) 3950 return 0x10; 3951 3952 return chip->ops->get_thermal(rtwdev, rf_path); 3953 } 3954 3955 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 3956 struct rtw89_rx_phy_ppdu *phy_ppdu, 3957 struct ieee80211_rx_status *status) 3958 { 3959 const struct rtw89_chip_info *chip = rtwdev->chip; 3960 3961 if (chip->ops->query_ppdu) 3962 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 3963 } 3964 3965 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 3966 bool bt_en) 3967 { 3968 const struct rtw89_chip_info *chip = rtwdev->chip; 3969 3970 if (chip->ops->bb_ctrl_btc_preagc) 3971 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 3972 } 3973 3974 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 3975 { 3976 const struct rtw89_chip_info *chip = rtwdev->chip; 3977 3978 if (chip->ops->cfg_txrx_path) 3979 chip->ops->cfg_txrx_path(rtwdev); 3980 } 3981 3982 static inline 3983 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 3984 struct ieee80211_vif *vif) 3985 { 3986 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3987 const struct rtw89_chip_info *chip = rtwdev->chip; 3988 3989 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 3990 return; 3991 3992 if (chip->ops->set_txpwr_ul_tb_offset) 3993 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 3994 } 3995 3996 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 3997 const struct rtw89_txpwr_table *tbl) 3998 { 3999 tbl->load(rtwdev, tbl); 4000 } 4001 4002 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 4003 { 4004 return rtwdev->regd->txpwr_regd[band]; 4005 } 4006 4007 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 4008 { 4009 const struct rtw89_chip_info *chip = rtwdev->chip; 4010 4011 if (chip->ops->ctrl_btg) 4012 chip->ops->ctrl_btg(rtwdev, btg); 4013 } 4014 4015 static inline 4016 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 4017 struct rtw89_tx_desc_info *desc_info, 4018 void *txdesc) 4019 { 4020 const struct rtw89_chip_info *chip = rtwdev->chip; 4021 4022 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 4023 } 4024 4025 static inline 4026 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 4027 struct rtw89_tx_desc_info *desc_info, 4028 void *txdesc) 4029 { 4030 const struct rtw89_chip_info *chip = rtwdev->chip; 4031 4032 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 4033 } 4034 4035 static inline 4036 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4037 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4038 { 4039 const struct rtw89_chip_info *chip = rtwdev->chip; 4040 4041 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 4042 } 4043 4044 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4045 { 4046 const struct rtw89_chip_info *chip = rtwdev->chip; 4047 4048 chip->ops->cfg_ctrl_path(rtwdev, wl); 4049 } 4050 4051 static inline 4052 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 4053 u32 *tx_en, enum rtw89_sch_tx_sel sel) 4054 { 4055 const struct rtw89_chip_info *chip = rtwdev->chip; 4056 4057 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 4058 } 4059 4060 static inline 4061 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 4062 { 4063 const struct rtw89_chip_info *chip = rtwdev->chip; 4064 4065 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 4066 } 4067 4068 static inline 4069 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 4070 struct rtw89_vif *rtwvif, 4071 struct rtw89_sta *rtwsta) 4072 { 4073 const struct rtw89_chip_info *chip = rtwdev->chip; 4074 4075 if (!chip->ops->h2c_dctl_sec_cam) 4076 return 0; 4077 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 4078 } 4079 4080 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 4081 { 4082 __le16 fc = hdr->frame_control; 4083 4084 if (ieee80211_has_tods(fc)) 4085 return hdr->addr1; 4086 else if (ieee80211_has_fromds(fc)) 4087 return hdr->addr2; 4088 else 4089 return hdr->addr3; 4090 } 4091 4092 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 4093 { 4094 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 4095 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 4096 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 4097 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 4098 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 4099 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 4100 return true; 4101 return false; 4102 } 4103 4104 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 4105 enum rtw89_fw_type type) 4106 { 4107 struct rtw89_fw_info *fw_info = &rtwdev->fw; 4108 4109 if (type == RTW89_FW_WOWLAN) 4110 return &fw_info->wowlan; 4111 return &fw_info->normal; 4112 } 4113 4114 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4115 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 4116 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 4117 struct sk_buff *skb, bool fwdl); 4118 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 4119 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 4120 struct rtw89_tx_desc_info *desc_info, 4121 void *txdesc); 4122 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 4123 struct rtw89_tx_desc_info *desc_info, 4124 void *txdesc); 4125 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 4126 struct rtw89_tx_desc_info *desc_info, 4127 void *txdesc); 4128 void rtw89_core_rx(struct rtw89_dev *rtwdev, 4129 struct rtw89_rx_desc_info *desc_info, 4130 struct sk_buff *skb); 4131 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 4132 struct rtw89_rx_desc_info *desc_info, 4133 u8 *data, u32 data_offset); 4134 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 4135 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 4136 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 4137 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 4138 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 4139 struct ieee80211_vif *vif, 4140 struct ieee80211_sta *sta); 4141 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 4142 struct ieee80211_vif *vif, 4143 struct ieee80211_sta *sta); 4144 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 4145 struct ieee80211_vif *vif, 4146 struct ieee80211_sta *sta); 4147 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 4148 struct ieee80211_vif *vif, 4149 struct ieee80211_sta *sta); 4150 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 4151 struct ieee80211_vif *vif, 4152 struct ieee80211_sta *sta); 4153 int rtw89_core_init(struct rtw89_dev *rtwdev); 4154 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 4155 int rtw89_core_register(struct rtw89_dev *rtwdev); 4156 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 4157 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4158 u32 bus_data_size, 4159 const struct rtw89_chip_info *chip); 4160 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 4161 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 4162 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 4163 void rtw89_set_channel(struct rtw89_dev *rtwdev); 4164 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 4165 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 4166 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 4167 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 4168 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4169 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 4170 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4171 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 4172 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 4173 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 4174 int rtw89_regd_init(struct rtw89_dev *rtwdev, 4175 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 4176 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 4177 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 4178 struct rtw89_traffic_stats *stats); 4179 int rtw89_core_start(struct rtw89_dev *rtwdev); 4180 void rtw89_core_stop(struct rtw89_dev *rtwdev); 4181 void rtw89_core_update_beacon_work(struct work_struct *work); 4182 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4183 const u8 *mac_addr, bool hw_scan); 4184 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4185 struct ieee80211_vif *vif, bool hw_scan); 4186 4187 #if defined(__linux__) 4188 #define rtw89_static_assert(_x) static_assert(_x) 4189 #elif defined(__FreeBSD__) 4190 #define rtw89_static_assert(_x) _Static_assert(_x, "bad array size") 4191 #endif 4192 4193 #endif
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