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sys/contrib/dev/rtw89/mac.h
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1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_MAC_H__ 6 #define __RTW89_MAC_H__ 7 8 #include "core.h" 9 10 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000 11 #define ADDR_CAM_ENT_SIZE 0x40 12 #define BSSID_CAM_ENT_SIZE 0x08 13 #define HFC_PAGE_UNIT 64 14 #define RPWM_TRY_CNT 3 15 16 enum rtw89_mac_hwmod_sel { 17 RTW89_DMAC_SEL = 0, 18 RTW89_CMAC_SEL = 1, 19 20 RTW89_MAC_INVALID, 21 }; 22 23 enum rtw89_mac_fwd_target { 24 RTW89_FWD_DONT_CARE = 0, 25 RTW89_FWD_TO_HOST = 1, 26 RTW89_FWD_TO_WLAN_CPU = 2 27 }; 28 29 enum rtw89_mac_wd_dma_intvl { 30 RTW89_MAC_WD_DMA_INTVL_0S, 31 RTW89_MAC_WD_DMA_INTVL_256NS, 32 RTW89_MAC_WD_DMA_INTVL_512NS, 33 RTW89_MAC_WD_DMA_INTVL_768NS, 34 RTW89_MAC_WD_DMA_INTVL_1US, 35 RTW89_MAC_WD_DMA_INTVL_1_5US, 36 RTW89_MAC_WD_DMA_INTVL_2US, 37 RTW89_MAC_WD_DMA_INTVL_4US, 38 RTW89_MAC_WD_DMA_INTVL_8US, 39 RTW89_MAC_WD_DMA_INTVL_16US, 40 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE 41 }; 42 43 enum rtw89_mac_multi_tag_num { 44 RTW89_MAC_TAG_NUM_1, 45 RTW89_MAC_TAG_NUM_2, 46 RTW89_MAC_TAG_NUM_3, 47 RTW89_MAC_TAG_NUM_4, 48 RTW89_MAC_TAG_NUM_5, 49 RTW89_MAC_TAG_NUM_6, 50 RTW89_MAC_TAG_NUM_7, 51 RTW89_MAC_TAG_NUM_8, 52 RTW89_MAC_TAG_NUM_DEF = 0xFE 53 }; 54 55 enum rtw89_mac_lbc_tmr { 56 RTW89_MAC_LBC_TMR_8US = 0, 57 RTW89_MAC_LBC_TMR_16US, 58 RTW89_MAC_LBC_TMR_32US, 59 RTW89_MAC_LBC_TMR_64US, 60 RTW89_MAC_LBC_TMR_128US, 61 RTW89_MAC_LBC_TMR_256US, 62 RTW89_MAC_LBC_TMR_512US, 63 RTW89_MAC_LBC_TMR_1MS, 64 RTW89_MAC_LBC_TMR_2MS, 65 RTW89_MAC_LBC_TMR_4MS, 66 RTW89_MAC_LBC_TMR_8MS, 67 RTW89_MAC_LBC_TMR_DEF = 0xFE 68 }; 69 70 enum rtw89_mac_cpuio_op_cmd_type { 71 CPUIO_OP_CMD_GET_1ST_PID = 0, 72 CPUIO_OP_CMD_GET_NEXT_PID = 1, 73 CPUIO_OP_CMD_ENQ_TO_TAIL = 4, 74 CPUIO_OP_CMD_ENQ_TO_HEAD = 5, 75 CPUIO_OP_CMD_DEQ = 8, 76 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, 77 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 78 }; 79 80 enum rtw89_mac_wde_dle_port_id { 81 WDE_DLE_PORT_ID_DISPATCH = 0, 82 WDE_DLE_PORT_ID_PKTIN = 1, 83 WDE_DLE_PORT_ID_CMAC0 = 3, 84 WDE_DLE_PORT_ID_CMAC1 = 4, 85 WDE_DLE_PORT_ID_CPU_IO = 6, 86 WDE_DLE_PORT_ID_WDRLS = 7, 87 WDE_DLE_PORT_ID_END = 8 88 }; 89 90 enum rtw89_mac_wde_dle_queid_wdrls { 91 WDE_DLE_QUEID_TXOK = 0, 92 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1, 93 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2, 94 WDE_DLE_QUEID_DROP_MACID_DROP = 3, 95 WDE_DLE_QUEID_NO_REPORT = 4 96 }; 97 98 enum rtw89_mac_ple_dle_port_id { 99 PLE_DLE_PORT_ID_DISPATCH = 0, 100 PLE_DLE_PORT_ID_MPDU = 1, 101 PLE_DLE_PORT_ID_SEC = 2, 102 PLE_DLE_PORT_ID_CMAC0 = 3, 103 PLE_DLE_PORT_ID_CMAC1 = 4, 104 PLE_DLE_PORT_ID_WDRLS = 5, 105 PLE_DLE_PORT_ID_CPU_IO = 6, 106 PLE_DLE_PORT_ID_PLRLS = 7, 107 PLE_DLE_PORT_ID_END = 8 108 }; 109 110 enum rtw89_mac_ple_dle_queid_plrls { 111 PLE_DLE_QUEID_NO_REPORT = 0x0 112 }; 113 114 enum rtw89_machdr_frame_type { 115 RTW89_MGNT = 0, 116 RTW89_CTRL = 1, 117 RTW89_DATA = 2, 118 }; 119 120 enum rtw89_mac_dle_dfi_type { 121 DLE_DFI_TYPE_FREEPG = 0, 122 DLE_DFI_TYPE_QUOTA = 1, 123 DLE_DFI_TYPE_PAGELLT = 2, 124 DLE_DFI_TYPE_PKTINFO = 3, 125 DLE_DFI_TYPE_PREPKTLLT = 4, 126 DLE_DFI_TYPE_NXTPKTLLT = 5, 127 DLE_DFI_TYPE_QLNKTBL = 6, 128 DLE_DFI_TYPE_QEMPTY = 7, 129 }; 130 131 enum rtw89_mac_dle_wde_quota_id { 132 WDE_QTAID_HOST_IF = 0, 133 WDE_QTAID_WLAN_CPU = 1, 134 WDE_QTAID_DATA_CPU = 2, 135 WDE_QTAID_PKTIN = 3, 136 WDE_QTAID_CPUIO = 4, 137 }; 138 139 enum rtw89_mac_dle_ple_quota_id { 140 PLE_QTAID_B0_TXPL = 0, 141 PLE_QTAID_B1_TXPL = 1, 142 PLE_QTAID_C2H = 2, 143 PLE_QTAID_H2C = 3, 144 PLE_QTAID_WLAN_CPU = 4, 145 PLE_QTAID_MPDU = 5, 146 PLE_QTAID_CMAC0_RX = 6, 147 PLE_QTAID_CMAC1_RX = 7, 148 PLE_QTAID_CMAC1_BBRPT = 8, 149 PLE_QTAID_WDRLS = 9, 150 PLE_QTAID_CPUIO = 10, 151 }; 152 153 enum rtw89_mac_dle_ctrl_type { 154 DLE_CTRL_TYPE_WDE = 0, 155 DLE_CTRL_TYPE_PLE = 1, 156 DLE_CTRL_TYPE_NUM = 2, 157 }; 158 159 enum rtw89_mac_ax_l0_to_l1_event { 160 MAC_AX_L0_TO_L1_CHIF_IDLE = 0, 161 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1, 162 MAC_AX_L0_TO_L1_RLS_PKID = 2, 163 MAC_AX_L0_TO_L1_PTCL_IDLE = 3, 164 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4, 165 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5, 166 MAC_AX_L0_TO_L1_PCIE_STUCK = 6, 167 MAC_AX_L0_TO_L1_EVENT_MAX = 15, 168 }; 169 170 enum rtw89_mac_dbg_port_sel { 171 /* CMAC 0 related */ 172 RTW89_DBG_PORT_SEL_PTCL_C0 = 0, 173 RTW89_DBG_PORT_SEL_SCH_C0, 174 RTW89_DBG_PORT_SEL_TMAC_C0, 175 RTW89_DBG_PORT_SEL_RMAC_C0, 176 RTW89_DBG_PORT_SEL_RMACST_C0, 177 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0, 178 RTW89_DBG_PORT_SEL_TRXPTCL_C0, 179 RTW89_DBG_PORT_SEL_TX_INFOL_C0, 180 RTW89_DBG_PORT_SEL_TX_INFOH_C0, 181 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0, 182 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0, 183 /* CMAC 1 related */ 184 RTW89_DBG_PORT_SEL_PTCL_C1, 185 RTW89_DBG_PORT_SEL_SCH_C1, 186 RTW89_DBG_PORT_SEL_TMAC_C1, 187 RTW89_DBG_PORT_SEL_RMAC_C1, 188 RTW89_DBG_PORT_SEL_RMACST_C1, 189 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1, 190 RTW89_DBG_PORT_SEL_TRXPTCL_C1, 191 RTW89_DBG_PORT_SEL_TX_INFOL_C1, 192 RTW89_DBG_PORT_SEL_TX_INFOH_C1, 193 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1, 194 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1, 195 /* DLE related */ 196 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG, 197 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA, 198 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT, 199 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO, 200 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT, 201 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT, 202 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL, 203 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY, 204 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG, 205 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA, 206 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT, 207 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO, 208 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT, 209 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT, 210 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL, 211 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY, 212 RTW89_DBG_PORT_SEL_PKTINFO, 213 /* PCIE related */ 214 RTW89_DBG_PORT_SEL_PCIE_TXDMA, 215 RTW89_DBG_PORT_SEL_PCIE_RXDMA, 216 RTW89_DBG_PORT_SEL_PCIE_CVT, 217 RTW89_DBG_PORT_SEL_PCIE_CXPL, 218 RTW89_DBG_PORT_SEL_PCIE_IO, 219 RTW89_DBG_PORT_SEL_PCIE_MISC, 220 RTW89_DBG_PORT_SEL_PCIE_MISC2, 221 222 /* keep last */ 223 RTW89_DBG_PORT_SEL_LAST, 224 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST, 225 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST, 226 }; 227 228 /* SRAM mem dump */ 229 #define R_AX_INDIR_ACCESS_ENTRY 0x40000 230 231 #define AXIDMA_BASE_ADDR 0x18006000 232 #define STA_SCHED_BASE_ADDR 0x18808000 233 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 234 #define SECURITY_CAM_BASE_ADDR 0x18814000 235 #define WOW_CAM_BASE_ADDR 0x18815000 236 #define CMAC_TBL_BASE_ADDR 0x18840000 237 #define ADDR_CAM_BASE_ADDR 0x18850000 238 #define BSSID_CAM_BASE_ADDR 0x18853000 239 #define BA_CAM_BASE_ADDR 0x18854000 240 #define BCN_IE_CAM0_BASE_ADDR 0x18855000 241 #define SHARED_BUF_BASE_ADDR 0x18700000 242 #define DMAC_TBL_BASE_ADDR 0x18800000 243 #define SHCUT_MACHDR_BASE_ADDR 0x18800800 244 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000 245 #define TXD_FIFO_0_BASE_ADDR 0x18856200 246 #define TXD_FIFO_1_BASE_ADDR 0x188A1080 247 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000 248 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 249 #define CPU_LOCAL_BASE_ADDR 0x18003000 250 251 #define CCTL_INFO_SIZE 32 252 253 enum rtw89_mac_mem_sel { 254 RTW89_MAC_MEM_AXIDMA, 255 RTW89_MAC_MEM_SHARED_BUF, 256 RTW89_MAC_MEM_DMAC_TBL, 257 RTW89_MAC_MEM_SHCUT_MACHDR, 258 RTW89_MAC_MEM_STA_SCHED, 259 RTW89_MAC_MEM_RXPLD_FLTR_CAM, 260 RTW89_MAC_MEM_SECURITY_CAM, 261 RTW89_MAC_MEM_WOW_CAM, 262 RTW89_MAC_MEM_CMAC_TBL, 263 RTW89_MAC_MEM_ADDR_CAM, 264 RTW89_MAC_MEM_BA_CAM, 265 RTW89_MAC_MEM_BCN_IE_CAM0, 266 RTW89_MAC_MEM_BCN_IE_CAM1, 267 RTW89_MAC_MEM_TXD_FIFO_0, 268 RTW89_MAC_MEM_TXD_FIFO_1, 269 RTW89_MAC_MEM_TXDATA_FIFO_0, 270 RTW89_MAC_MEM_TXDATA_FIFO_1, 271 RTW89_MAC_MEM_CPU_LOCAL, 272 RTW89_MAC_MEM_BSSID_CAM, 273 274 /* keep last */ 275 RTW89_MAC_MEM_NUM, 276 }; 277 278 extern const u32 rtw89_mac_mem_base_addrs[]; 279 280 enum rtw89_rpwm_req_pwr_state { 281 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, 282 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, 283 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, 284 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, 285 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, 286 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5, 287 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6, 288 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, 289 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX, 290 }; 291 292 struct rtw89_pwr_cfg { 293 u16 addr; 294 u8 cv_msk; 295 u8 intf_msk; 296 u8 base:4; 297 u8 cmd:4; 298 u8 msk; 299 u8 val; 300 }; 301 302 enum rtw89_mac_c2h_ofld_func { 303 RTW89_MAC_C2H_FUNC_EFUSE_DUMP, 304 RTW89_MAC_C2H_FUNC_READ_RSP, 305 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP, 306 RTW89_MAC_C2H_FUNC_BCN_RESEND, 307 RTW89_MAC_C2H_FUNC_MACID_PAUSE, 308 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9, 309 RTW89_MAC_C2H_FUNC_OFLD_MAX, 310 }; 311 312 enum rtw89_mac_c2h_info_func { 313 RTW89_MAC_C2H_FUNC_REC_ACK, 314 RTW89_MAC_C2H_FUNC_DONE_ACK, 315 RTW89_MAC_C2H_FUNC_C2H_LOG, 316 RTW89_MAC_C2H_FUNC_BCN_CNT, 317 RTW89_MAC_C2H_FUNC_INFO_MAX, 318 }; 319 320 enum rtw89_mac_c2h_class { 321 RTW89_MAC_C2H_CLASS_INFO, 322 RTW89_MAC_C2H_CLASS_OFLD, 323 RTW89_MAC_C2H_CLASS_TWT, 324 RTW89_MAC_C2H_CLASS_WOW, 325 RTW89_MAC_C2H_CLASS_MCC, 326 RTW89_MAC_C2H_CLASS_FWDBG, 327 RTW89_MAC_C2H_CLASS_MAX, 328 }; 329 330 struct rtw89_mac_ax_coex { 331 #define RTW89_MAC_AX_COEX_RTK_MODE 0 332 #define RTW89_MAC_AX_COEX_CSR_MODE 1 333 u8 pta_mode; 334 #define RTW89_MAC_AX_COEX_INNER 0 335 #define RTW89_MAC_AX_COEX_OUTPUT 1 336 #define RTW89_MAC_AX_COEX_INPUT 2 337 u8 direction; 338 }; 339 340 struct rtw89_mac_ax_plt { 341 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0) 342 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1) 343 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2) 344 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3) 345 u8 band; 346 u8 tx; 347 u8 rx; 348 }; 349 350 enum rtw89_mac_bf_rrsc_rate { 351 RTW89_MAC_BF_RRSC_6M = 0, 352 RTW89_MAC_BF_RRSC_9M = 1, 353 RTW89_MAC_BF_RRSC_12M, 354 RTW89_MAC_BF_RRSC_18M, 355 RTW89_MAC_BF_RRSC_24M, 356 RTW89_MAC_BF_RRSC_36M, 357 RTW89_MAC_BF_RRSC_48M, 358 RTW89_MAC_BF_RRSC_54M, 359 RTW89_MAC_BF_RRSC_HT_MSC0, 360 RTW89_MAC_BF_RRSC_HT_MSC1, 361 RTW89_MAC_BF_RRSC_HT_MSC2, 362 RTW89_MAC_BF_RRSC_HT_MSC3, 363 RTW89_MAC_BF_RRSC_HT_MSC4, 364 RTW89_MAC_BF_RRSC_HT_MSC5, 365 RTW89_MAC_BF_RRSC_HT_MSC6, 366 RTW89_MAC_BF_RRSC_HT_MSC7, 367 RTW89_MAC_BF_RRSC_VHT_MSC0, 368 RTW89_MAC_BF_RRSC_VHT_MSC1, 369 RTW89_MAC_BF_RRSC_VHT_MSC2, 370 RTW89_MAC_BF_RRSC_VHT_MSC3, 371 RTW89_MAC_BF_RRSC_VHT_MSC4, 372 RTW89_MAC_BF_RRSC_VHT_MSC5, 373 RTW89_MAC_BF_RRSC_VHT_MSC6, 374 RTW89_MAC_BF_RRSC_VHT_MSC7, 375 RTW89_MAC_BF_RRSC_HE_MSC0, 376 RTW89_MAC_BF_RRSC_HE_MSC1, 377 RTW89_MAC_BF_RRSC_HE_MSC2, 378 RTW89_MAC_BF_RRSC_HE_MSC3, 379 RTW89_MAC_BF_RRSC_HE_MSC4, 380 RTW89_MAC_BF_RRSC_HE_MSC5, 381 RTW89_MAC_BF_RRSC_HE_MSC6, 382 RTW89_MAC_BF_RRSC_HE_MSC7 = 31, 383 RTW89_MAC_BF_RRSC_MAX = 32 384 }; 385 386 #define RTW89_R32_EA 0xEAEAEAEA 387 #define RTW89_R32_DEAD 0xDEADBEEF 388 #define MAC_REG_POOL_COUNT 10 389 #define ACCESS_CMAC(_addr) \ 390 ({typeof(_addr) __addr = (_addr); \ 391 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) 392 393 #define PTCL_IDLE_POLL_CNT 10000 394 #define SW_CVR_DUR_US 8 395 #define SW_CVR_CNT 8 396 397 #define DLE_BOUND_UNIT (8 * 1024) 398 #define DLE_WAIT_CNT 2000 399 #define TRXCFG_WAIT_CNT 2000 400 401 #define RTW89_WDE_PG_64 64 402 #define RTW89_WDE_PG_128 128 403 #define RTW89_WDE_PG_256 256 404 405 #define S_AX_WDE_PAGE_SEL_64 0 406 #define S_AX_WDE_PAGE_SEL_128 1 407 #define S_AX_WDE_PAGE_SEL_256 2 408 409 #define RTW89_PLE_PG_64 64 410 #define RTW89_PLE_PG_128 128 411 #define RTW89_PLE_PG_256 256 412 413 #define S_AX_PLE_PAGE_SEL_64 0 414 #define S_AX_PLE_PAGE_SEL_128 1 415 #define S_AX_PLE_PAGE_SEL_256 2 416 417 #define SDIO_LOCAL_BASE_ADDR 0x80000000 418 419 #define PWR_CMD_WRITE 0 420 #define PWR_CMD_POLL 1 421 #define PWR_CMD_DELAY 2 422 #define PWR_CMD_END 3 423 424 #define PWR_INTF_MSK_SDIO BIT(0) 425 #define PWR_INTF_MSK_USB BIT(1) 426 #define PWR_INTF_MSK_PCIE BIT(2) 427 #define PWR_INTF_MSK_ALL 0x7 428 429 #define PWR_BASE_MAC 0 430 #define PWR_BASE_USB 1 431 #define PWR_BASE_PCIE 2 432 #define PWR_BASE_SDIO 3 433 434 #define PWR_CV_MSK_A BIT(0) 435 #define PWR_CV_MSK_B BIT(1) 436 #define PWR_CV_MSK_C BIT(2) 437 #define PWR_CV_MSK_D BIT(3) 438 #define PWR_CV_MSK_E BIT(4) 439 #define PWR_CV_MSK_F BIT(5) 440 #define PWR_CV_MSK_G BIT(6) 441 #define PWR_CV_MSK_TEST BIT(7) 442 #define PWR_CV_MSK_ALL 0xFF 443 444 #define PWR_DELAY_US 0 445 #define PWR_DELAY_MS 1 446 447 /* STA scheduler */ 448 #define SS_MACID_SH 8 449 #define SS_TX_LEN_MSK 0x1FFFFF 450 #define SS_CTRL1_R_TX_LEN 5 451 #define SS_CTRL1_R_NEXT_LINK 20 452 #define SS_LINK_SIZE 256 453 454 /* MAC debug port */ 455 #define TMAC_DBG_SEL_C0 0xA5 456 #define RMAC_DBG_SEL_C0 0xA6 457 #define TRXPTCL_DBG_SEL_C0 0xA7 458 #define TMAC_DBG_SEL_C1 0xB5 459 #define RMAC_DBG_SEL_C1 0xB6 460 #define TRXPTCL_DBG_SEL_C1 0xB7 461 #define FW_PROG_CNTR_DBG_SEL 0xF2 462 #define PCIE_TXDMA_DBG_SEL 0x30 463 #define PCIE_RXDMA_DBG_SEL 0x31 464 #define PCIE_CVT_DBG_SEL 0x32 465 #define PCIE_CXPL_DBG_SEL 0x33 466 #define PCIE_IO_DBG_SEL 0x37 467 #define PCIE_MISC_DBG_SEL 0x38 468 #define PCIE_MISC2_DBG_SEL 0x00 469 #define MAC_DBG_SEL 1 470 #define RMAC_CMAC_DBG_SEL 1 471 472 /* TRXPTCL dbg port sel */ 473 #define TRXPTRL_DBG_SEL_TMAC 0 474 #define TRXPTRL_DBG_SEL_RMAC 1 475 476 struct rtw89_cpuio_ctrl { 477 u16 pkt_num; 478 u16 start_pktid; 479 u16 end_pktid; 480 u8 cmd_type; 481 u8 macid; 482 u8 src_pid; 483 u8 src_qid; 484 u8 dst_pid; 485 u8 dst_qid; 486 u16 pktid; 487 }; 488 489 struct rtw89_mac_dbg_port_info { 490 u32 sel_addr; 491 u8 sel_byte; 492 u32 sel_msk; 493 u32 srt; 494 u32 end; 495 u32 rd_addr; 496 u8 rd_byte; 497 u32 rd_msk; 498 }; 499 500 #define QLNKTBL_ADDR_INFO_SEL BIT(0) 501 #define QLNKTBL_ADDR_INFO_SEL_0 0 502 #define QLNKTBL_ADDR_INFO_SEL_1 1 503 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1) 504 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0) 505 506 struct rtw89_mac_dle_dfi_ctrl { 507 enum rtw89_mac_dle_ctrl_type type; 508 u32 target; 509 u32 addr; 510 u32 out_data; 511 }; 512 513 struct rtw89_mac_dle_dfi_quota { 514 enum rtw89_mac_dle_ctrl_type dle_type; 515 u32 qtaid; 516 u16 rsv_pgnum; 517 u16 use_pgnum; 518 }; 519 520 struct rtw89_mac_dle_dfi_qempty { 521 enum rtw89_mac_dle_ctrl_type dle_type; 522 u32 grpsel; 523 u32 qempty; 524 }; 525 526 enum rtw89_mac_error_scenario { 527 RTW89_WCPU_CPU_EXCEPTION = 2, 528 RTW89_WCPU_ASSERTION = 3, 529 }; 530 531 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28) 532 533 /* Define DBG and recovery enum */ 534 enum mac_ax_err_info { 535 /* Get error info */ 536 537 /* L0 */ 538 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, 539 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, 540 MAC_AX_ERR_L0_RESET_DONE = 0x0003, 541 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, 542 543 /* L1 */ 544 MAC_AX_ERR_L1_ERR_DMAC = 0x1000, 545 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, 546 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, 547 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, 548 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, 549 550 /* L2 */ 551 /* address hole (master) */ 552 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, 553 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, 554 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, 555 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, 556 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, 557 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, 558 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, 559 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, 560 561 /* AHB bridge timeout (master) */ 562 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, 563 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, 564 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, 565 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, 566 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, 567 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, 568 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, 569 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, 570 571 /* APB_SA bridge timeout (master + slave) */ 572 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, 573 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, 574 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, 575 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, 576 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, 577 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, 578 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, 579 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, 580 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, 581 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, 582 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, 583 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, 584 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, 585 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, 586 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, 587 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, 588 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, 589 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, 590 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, 591 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, 592 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, 593 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, 594 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, 595 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, 596 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, 597 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, 598 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, 599 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, 600 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, 601 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, 602 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, 603 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, 604 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, 605 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, 606 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, 607 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, 608 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, 609 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, 610 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, 611 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, 612 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, 613 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, 614 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, 615 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, 616 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, 617 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, 618 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, 619 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, 620 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, 621 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, 622 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, 623 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, 624 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, 625 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, 626 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, 627 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, 628 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, 629 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, 630 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, 631 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, 632 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, 633 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, 634 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, 635 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, 636 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, 637 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, 638 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, 639 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, 640 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, 641 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, 642 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, 643 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, 644 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, 645 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, 646 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, 647 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, 648 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, 649 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, 650 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, 651 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, 652 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, 653 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, 654 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, 655 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, 656 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, 657 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, 658 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, 659 660 /* APB_BBRF bridge timeout (master) */ 661 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, 662 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, 663 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, 664 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, 665 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, 666 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, 667 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, 668 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, 669 MAC_AX_ERR_L2_RESET_DONE = 0x2400, 670 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599, 671 MAC_AX_ERR_CPU_EXCEPTION = 0x3000, 672 MAC_AX_ERR_ASSERTION = 0x4000, 673 MAC_AX_GET_ERR_MAX, 674 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, 675 676 /* set error info */ 677 MAC_AX_ERR_L1_DISABLE_EN = 0x0001, 678 MAC_AX_ERR_L1_RCVY_EN = 0x0002, 679 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, 680 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, 681 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, 682 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, 683 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, 684 MAC_AX_ERR_L0_RCVY_EN = 0x0013, 685 MAC_AX_SET_ERR_MAX, 686 }; 687 688 struct rtw89_mac_size_set { 689 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie; 690 const struct rtw89_dle_size wde_size0; 691 const struct rtw89_dle_size wde_size4; 692 const struct rtw89_dle_size wde_size18; 693 const struct rtw89_dle_size wde_size19; 694 const struct rtw89_dle_size ple_size0; 695 const struct rtw89_dle_size ple_size4; 696 const struct rtw89_dle_size ple_size18; 697 const struct rtw89_dle_size ple_size19; 698 const struct rtw89_wde_quota wde_qt0; 699 const struct rtw89_wde_quota wde_qt4; 700 const struct rtw89_wde_quota wde_qt17; 701 const struct rtw89_wde_quota wde_qt18; 702 const struct rtw89_ple_quota ple_qt4; 703 const struct rtw89_ple_quota ple_qt5; 704 const struct rtw89_ple_quota ple_qt13; 705 const struct rtw89_ple_quota ple_qt44; 706 const struct rtw89_ple_quota ple_qt45; 707 const struct rtw89_ple_quota ple_qt46; 708 const struct rtw89_ple_quota ple_qt47; 709 }; 710 711 extern const struct rtw89_mac_size_set rtw89_mac_size; 712 713 static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band) 714 { 715 return band == 0 ? reg_base : (reg_base + 0x2000); 716 } 717 718 static inline u32 rtw89_mac_reg_by_port(u32 base, u8 port, u8 mac_idx) 719 { 720 return rtw89_mac_reg_by_idx(base + port * 0x40, mac_idx); 721 } 722 723 static inline u32 724 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 725 u32 base, u32 mask) 726 { 727 u32 reg; 728 729 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 730 return rtw89_read32_mask(rtwdev, reg, mask); 731 } 732 733 static inline void 734 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, 735 u32 data) 736 { 737 u32 reg; 738 739 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 740 rtw89_write32(rtwdev, reg, data); 741 } 742 743 static inline void 744 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 745 u32 base, u32 mask, u32 data) 746 { 747 u32 reg; 748 749 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 750 rtw89_write32_mask(rtwdev, reg, mask, data); 751 } 752 753 static inline void 754 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 755 u32 base, u32 mask, u16 data) 756 { 757 u32 reg; 758 759 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 760 rtw89_write16_mask(rtwdev, reg, mask, data); 761 } 762 763 static inline void 764 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 765 u32 base, u32 bit) 766 { 767 u32 reg; 768 769 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 770 rtw89_write32_clr(rtwdev, reg, bit); 771 } 772 773 static inline void 774 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 775 u32 base, u16 bit) 776 { 777 u32 reg; 778 779 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 780 rtw89_write16_clr(rtwdev, reg, bit); 781 } 782 783 static inline void 784 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 785 u32 base, u32 bit) 786 { 787 u32 reg; 788 789 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 790 rtw89_write32_set(rtwdev, reg, bit); 791 } 792 793 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); 794 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev); 795 int rtw89_mac_init(struct rtw89_dev *rtwdev); 796 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, 797 enum rtw89_mac_hwmod_sel sel); 798 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); 799 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); 800 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 801 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 802 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 803 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); 804 void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); 805 806 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev) 807 { 808 const struct rtw89_chip_info *chip = rtwdev->chip; 809 810 return chip->ops->enable_bb_rf(rtwdev); 811 } 812 813 static inline void rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev) 814 { 815 const struct rtw89_chip_info *chip = rtwdev->chip; 816 817 chip->ops->disable_bb_rf(rtwdev); 818 } 819 820 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); 821 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); 822 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 823 u32 len, u8 class, u8 func); 824 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); 825 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 826 u32 *tx_en, enum rtw89_sch_tx_sel sel); 827 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 828 u32 *tx_en, enum rtw89_sch_tx_sel sel); 829 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 830 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 831 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable); 832 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx); 833 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); 834 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); 835 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 836 const struct rtw89_mac_ax_coex *coex); 837 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 838 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 839 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 840 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 841 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); 842 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band); 843 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); 844 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); 845 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); 846 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); 847 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); 848 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 849 enum rtw89_phy_idx phy_idx, 850 u32 reg_base, u32 *cr); 851 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); 852 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); 853 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 854 struct ieee80211_sta *sta); 855 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 856 struct ieee80211_sta *sta); 857 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 858 struct ieee80211_bss_conf *conf); 859 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 860 struct ieee80211_sta *sta, bool disconnect); 861 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); 862 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 863 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 864 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 865 struct rtw89_vif *rtwvif, bool en); 866 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause); 867 868 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 869 { 870 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags)) 871 return; 872 873 _rtw89_mac_bf_monitor_track(rtwdev); 874 } 875 876 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, 877 enum rtw89_phy_idx phy_idx, 878 u32 reg_base, u32 *val) 879 { 880 u32 cr; 881 882 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 883 return -EINVAL; 884 885 *val = rtw89_read32(rtwdev, cr); 886 return 0; 887 } 888 889 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, 890 enum rtw89_phy_idx phy_idx, 891 u32 reg_base, u32 val) 892 { 893 u32 cr; 894 895 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 896 return -EINVAL; 897 898 rtw89_write32(rtwdev, cr, val); 899 return 0; 900 } 901 902 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, 903 enum rtw89_phy_idx phy_idx, 904 u32 reg_base, u32 mask, u32 val) 905 { 906 u32 cr; 907 908 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 909 return -EINVAL; 910 911 rtw89_write32_mask(rtwdev, cr, mask, val); 912 return 0; 913 } 914 915 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 916 bool resume, u32 tx_time); 917 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 918 u32 *tx_time); 919 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 920 struct rtw89_sta *rtwsta, 921 bool resume, u8 tx_retry); 922 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 923 struct rtw89_sta *rtwsta, u8 *tx_retry); 924 925 enum rtw89_mac_xtal_si_offset { 926 XTAL0 = 0x0, 927 XTAL3 = 0x3, 928 XTAL_SI_XTAL_SC_XI = 0x04, 929 #define XTAL_SC_XI_MASK GENMASK(7, 0) 930 XTAL_SI_XTAL_SC_XO = 0x05, 931 #define XTAL_SC_XO_MASK GENMASK(7, 0) 932 XTAL_SI_PWR_CUT = 0x10, 933 #define XTAL_SI_SMALL_PWR_CUT BIT(0) 934 #define XTAL_SI_BIG_PWR_CUT BIT(1) 935 XTAL_SI_XTAL_XMD_2 = 0x24, 936 #define XTAL_SI_LDO_LPS GENMASK(6, 4) 937 XTAL_SI_XTAL_XMD_4 = 0x26, 938 #define XTAL_SI_LPS_CAP GENMASK(3, 0) 939 XTAL_SI_CV = 0x41, 940 XTAL_SI_LOW_ADDR = 0x62, 941 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0) 942 XTAL_SI_CTRL = 0x63, 943 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6) 944 #define XTAL_SI_RDY BIT(5) 945 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0) 946 XTAL_SI_READ_VAL = 0x7A, 947 XTAL_SI_WL_RFC_S0 = 0x80, 948 #define XTAL_SI_RF00 BIT(0) 949 XTAL_SI_WL_RFC_S1 = 0x81, 950 #define XTAL_SI_RF10 BIT(0) 951 XTAL_SI_ANAPAR_WL = 0x90, 952 #define XTAL_SI_SRAM2RFC BIT(7) 953 #define XTAL_SI_GND_SHDN_WL BIT(6) 954 #define XTAL_SI_SHDN_WL BIT(5) 955 #define XTAL_SI_RFC2RF BIT(4) 956 #define XTAL_SI_OFF_EI BIT(3) 957 #define XTAL_SI_OFF_WEI BIT(2) 958 #define XTAL_SI_PON_EI BIT(1) 959 #define XTAL_SI_PON_WEI BIT(0) 960 XTAL_SI_SRAM_CTRL = 0xA1, 961 #define FULL_BIT_MASK GENMASK(7, 0) 962 }; 963 964 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask); 965 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val); 966 967 #endif
Cache object: 39079492918d29c3063cb2c46ccd9ecb
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