Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/contrib/dev/rtw89/rtw8852a.c
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1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852a.h" 11 #include "rtw8852a_rfk.h" 12 #include "rtw8852a_table.h" 13 #include "txrx.h" 14 15 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = { 16 {128, 1896, grp_0}, /* ACH 0 */ 17 {128, 1896, grp_0}, /* ACH 1 */ 18 {128, 1896, grp_0}, /* ACH 2 */ 19 {128, 1896, grp_0}, /* ACH 3 */ 20 {128, 1896, grp_1}, /* ACH 4 */ 21 {128, 1896, grp_1}, /* ACH 5 */ 22 {128, 1896, grp_1}, /* ACH 6 */ 23 {128, 1896, grp_1}, /* ACH 7 */ 24 {32, 1896, grp_0}, /* B0MGQ */ 25 {128, 1896, grp_0}, /* B0HIQ */ 26 {32, 1896, grp_1}, /* B1MGQ */ 27 {128, 1896, grp_1}, /* B1HIQ */ 28 {40, 0, 0} /* FWCMDQ */ 29 }; 30 31 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = { 32 1896, /* Group 0 */ 33 1896, /* Group 1 */ 34 3792, /* Public Max */ 35 0 /* WP threshold */ 36 }; 37 38 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = { 39 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie, 40 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 41 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 42 RTW89_HCIFC_POH}, 43 [RTW89_QTA_INVALID] = {NULL}, 44 }; 45 46 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = { 47 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0, 48 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 49 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 50 &rtw89_mac_size.ple_qt5}, 51 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4, 52 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4, 53 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 54 &rtw89_mac_size.ple_qt13}, 55 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 56 NULL}, 57 }; 58 59 static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = { 60 {0x44AC, 0x00000000}, 61 {0x44B0, 0x00000000}, 62 {0x44B4, 0x00000000}, 63 {0x44B8, 0x00000000}, 64 {0x44BC, 0x00000000}, 65 {0x44C0, 0x00000000}, 66 {0x44C4, 0x00000000}, 67 {0x44C8, 0x00000000}, 68 {0x44CC, 0x00000000}, 69 {0x44D0, 0x00000000}, 70 {0x44D4, 0x00000000}, 71 {0x44D8, 0x00000000}, 72 {0x44DC, 0x00000000}, 73 {0x44E0, 0x00000000}, 74 {0x44E4, 0x00000000}, 75 {0x44E8, 0x00000000}, 76 {0x44EC, 0x00000000}, 77 {0x44F0, 0x00000000}, 78 {0x44F4, 0x00000000}, 79 {0x44F8, 0x00000000}, 80 {0x44FC, 0x00000000}, 81 {0x4500, 0x00000000}, 82 {0x4504, 0x00000000}, 83 {0x4508, 0x00000000}, 84 {0x450C, 0x00000000}, 85 {0x4510, 0x00000000}, 86 {0x4514, 0x00000000}, 87 {0x4518, 0x00000000}, 88 {0x451C, 0x00000000}, 89 {0x4520, 0x00000000}, 90 {0x4524, 0x00000000}, 91 {0x4528, 0x00000000}, 92 {0x452C, 0x00000000}, 93 {0x4530, 0x4E1F3E81}, 94 {0x4534, 0x00000000}, 95 {0x4538, 0x0000005A}, 96 {0x453C, 0x00000000}, 97 {0x4540, 0x00000000}, 98 {0x4544, 0x00000000}, 99 {0x4548, 0x00000000}, 100 {0x454C, 0x00000000}, 101 {0x4550, 0x00000000}, 102 {0x4554, 0x00000000}, 103 {0x4558, 0x00000000}, 104 {0x455C, 0x00000000}, 105 {0x4560, 0x4060001A}, 106 {0x4564, 0x40000000}, 107 {0x4568, 0x00000000}, 108 {0x456C, 0x00000000}, 109 {0x4570, 0x04000007}, 110 {0x4574, 0x0000DC87}, 111 {0x4578, 0x00000BAB}, 112 {0x457C, 0x03E00000}, 113 {0x4580, 0x00000048}, 114 {0x4584, 0x00000000}, 115 {0x4588, 0x000003E8}, 116 {0x458C, 0x30000000}, 117 {0x4590, 0x00000000}, 118 {0x4594, 0x10000000}, 119 {0x4598, 0x00000001}, 120 {0x459C, 0x00030000}, 121 {0x45A0, 0x01000000}, 122 {0x45A4, 0x03000200}, 123 {0x45A8, 0xC00001C0}, 124 {0x45AC, 0x78018000}, 125 {0x45B0, 0x80000000}, 126 {0x45B4, 0x01C80600}, 127 {0x45B8, 0x00000002}, 128 {0x4594, 0x10000000} 129 }; 130 131 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = { 132 {0x4624, GENMASK(20, 14), 0x40}, 133 {0x46f8, GENMASK(20, 14), 0x40}, 134 {0x4674, GENMASK(20, 19), 0x2}, 135 {0x4748, GENMASK(20, 19), 0x2}, 136 {0x4650, GENMASK(14, 10), 0x18}, 137 {0x4724, GENMASK(14, 10), 0x18}, 138 {0x4688, GENMASK(1, 0), 0x3}, 139 {0x475c, GENMASK(1, 0), 0x3}, 140 }; 141 142 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs); 143 144 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = { 145 {0x4624, GENMASK(20, 14), 0x1a}, 146 {0x46f8, GENMASK(20, 14), 0x1a}, 147 {0x4674, GENMASK(20, 19), 0x1}, 148 {0x4748, GENMASK(20, 19), 0x1}, 149 {0x4650, GENMASK(14, 10), 0x12}, 150 {0x4724, GENMASK(14, 10), 0x12}, 151 {0x4688, GENMASK(1, 0), 0x0}, 152 {0x475c, GENMASK(1, 0), 0x0}, 153 }; 154 155 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs); 156 157 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = { 158 {0x00C6, 159 PWR_CV_MSK_B, 160 PWR_INTF_MSK_PCIE, 161 PWR_BASE_MAC, 162 PWR_CMD_WRITE, BIT(6), BIT(6)}, 163 {0x1086, 164 PWR_CV_MSK_ALL, 165 PWR_INTF_MSK_SDIO, 166 PWR_BASE_MAC, 167 PWR_CMD_WRITE, BIT(0), 0}, 168 {0x1086, 169 PWR_CV_MSK_ALL, 170 PWR_INTF_MSK_SDIO, 171 PWR_BASE_MAC, 172 PWR_CMD_POLL, BIT(1), BIT(1)}, 173 {0x0005, 174 PWR_CV_MSK_ALL, 175 PWR_INTF_MSK_ALL, 176 PWR_BASE_MAC, 177 PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, 178 {0x0005, 179 PWR_CV_MSK_ALL, 180 PWR_INTF_MSK_ALL, 181 PWR_BASE_MAC, 182 PWR_CMD_WRITE, BIT(7), 0}, 183 {0x0005, 184 PWR_CV_MSK_ALL, 185 PWR_INTF_MSK_ALL, 186 PWR_BASE_MAC, 187 PWR_CMD_WRITE, BIT(2), 0}, 188 {0x0006, 189 PWR_CV_MSK_ALL, 190 PWR_INTF_MSK_ALL, 191 PWR_BASE_MAC, 192 PWR_CMD_POLL, BIT(1), BIT(1)}, 193 {0x0006, 194 PWR_CV_MSK_ALL, 195 PWR_INTF_MSK_ALL, 196 PWR_BASE_MAC, 197 PWR_CMD_WRITE, BIT(0), BIT(0)}, 198 {0x0005, 199 PWR_CV_MSK_ALL, 200 PWR_INTF_MSK_ALL, 201 PWR_BASE_MAC, 202 PWR_CMD_WRITE, BIT(0), BIT(0)}, 203 {0x0005, 204 PWR_CV_MSK_ALL, 205 PWR_INTF_MSK_ALL, 206 PWR_BASE_MAC, 207 PWR_CMD_POLL, BIT(0), 0}, 208 {0x106D, 209 PWR_CV_MSK_B | PWR_CV_MSK_C, 210 PWR_INTF_MSK_USB, 211 PWR_BASE_MAC, 212 PWR_CMD_WRITE, BIT(6), 0}, 213 {0x0088, 214 PWR_CV_MSK_ALL, 215 PWR_INTF_MSK_ALL, 216 PWR_BASE_MAC, 217 PWR_CMD_WRITE, BIT(0), BIT(0)}, 218 {0x0088, 219 PWR_CV_MSK_ALL, 220 PWR_INTF_MSK_ALL, 221 PWR_BASE_MAC, 222 PWR_CMD_WRITE, BIT(0), 0}, 223 {0x0088, 224 PWR_CV_MSK_ALL, 225 PWR_INTF_MSK_ALL, 226 PWR_BASE_MAC, 227 PWR_CMD_WRITE, BIT(0), BIT(0)}, 228 {0x0088, 229 PWR_CV_MSK_ALL, 230 PWR_INTF_MSK_ALL, 231 PWR_BASE_MAC, 232 PWR_CMD_WRITE, BIT(0), 0}, 233 {0x0088, 234 PWR_CV_MSK_ALL, 235 PWR_INTF_MSK_ALL, 236 PWR_BASE_MAC, 237 PWR_CMD_WRITE, BIT(0), BIT(0)}, 238 {0x0083, 239 PWR_CV_MSK_ALL, 240 PWR_INTF_MSK_ALL, 241 PWR_BASE_MAC, 242 PWR_CMD_WRITE, BIT(6), 0}, 243 {0x0080, 244 PWR_CV_MSK_ALL, 245 PWR_INTF_MSK_ALL, 246 PWR_BASE_MAC, 247 PWR_CMD_WRITE, BIT(5), BIT(5)}, 248 {0x0024, 249 PWR_CV_MSK_ALL, 250 PWR_INTF_MSK_ALL, 251 PWR_BASE_MAC, 252 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}, 253 {0x02A0, 254 PWR_CV_MSK_ALL, 255 PWR_INTF_MSK_ALL, 256 PWR_BASE_MAC, 257 PWR_CMD_WRITE, BIT(1), BIT(1)}, 258 {0x02A2, 259 PWR_CV_MSK_ALL, 260 PWR_INTF_MSK_ALL, 261 PWR_BASE_MAC, 262 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0}, 263 {0x0071, 264 PWR_CV_MSK_ALL, 265 PWR_INTF_MSK_PCIE, 266 PWR_BASE_MAC, 267 PWR_CMD_WRITE, BIT(4), 0}, 268 {0x0010, 269 PWR_CV_MSK_A, 270 PWR_INTF_MSK_PCIE, 271 PWR_BASE_MAC, 272 PWR_CMD_WRITE, BIT(2), BIT(2)}, 273 {0x02A0, 274 PWR_CV_MSK_A, 275 PWR_INTF_MSK_ALL, 276 PWR_BASE_MAC, 277 PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 278 {0xFFFF, 279 PWR_CV_MSK_ALL, 280 PWR_INTF_MSK_ALL, 281 0, 282 PWR_CMD_END, 0, 0}, 283 }; 284 285 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = { 286 {0x02F0, 287 PWR_CV_MSK_ALL, 288 PWR_INTF_MSK_ALL, 289 PWR_BASE_MAC, 290 PWR_CMD_WRITE, 0xFF, 0}, 291 {0x02F1, 292 PWR_CV_MSK_ALL, 293 PWR_INTF_MSK_ALL, 294 PWR_BASE_MAC, 295 PWR_CMD_WRITE, 0xFF, 0}, 296 {0x0006, 297 PWR_CV_MSK_ALL, 298 PWR_INTF_MSK_ALL, 299 PWR_BASE_MAC, 300 PWR_CMD_WRITE, BIT(0), BIT(0)}, 301 {0x0002, 302 PWR_CV_MSK_ALL, 303 PWR_INTF_MSK_ALL, 304 PWR_BASE_MAC, 305 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 306 {0x0082, 307 PWR_CV_MSK_ALL, 308 PWR_INTF_MSK_ALL, 309 PWR_BASE_MAC, 310 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 311 {0x106D, 312 PWR_CV_MSK_B | PWR_CV_MSK_C, 313 PWR_INTF_MSK_USB, 314 PWR_BASE_MAC, 315 PWR_CMD_WRITE, BIT(6), BIT(6)}, 316 {0x0005, 317 PWR_CV_MSK_ALL, 318 PWR_INTF_MSK_ALL, 319 PWR_BASE_MAC, 320 PWR_CMD_WRITE, BIT(1), BIT(1)}, 321 {0x0005, 322 PWR_CV_MSK_ALL, 323 PWR_INTF_MSK_ALL, 324 PWR_BASE_MAC, 325 PWR_CMD_POLL, BIT(1), 0}, 326 {0x0091, 327 PWR_CV_MSK_ALL, 328 PWR_INTF_MSK_PCIE, 329 PWR_BASE_MAC, 330 PWR_CMD_WRITE, BIT(0), 0}, 331 {0x0005, 332 PWR_CV_MSK_ALL, 333 PWR_INTF_MSK_PCIE, 334 PWR_BASE_MAC, 335 PWR_CMD_WRITE, BIT(2), BIT(2)}, 336 {0x0007, 337 PWR_CV_MSK_ALL, 338 PWR_INTF_MSK_USB, 339 PWR_BASE_MAC, 340 PWR_CMD_WRITE, BIT(4), 0}, 341 {0x0007, 342 PWR_CV_MSK_ALL, 343 PWR_INTF_MSK_SDIO, 344 PWR_BASE_MAC, 345 PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, 346 {0x0005, 347 PWR_CV_MSK_ALL, 348 PWR_INTF_MSK_SDIO, 349 PWR_BASE_MAC, 350 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 351 {0x0005, 352 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F | 353 PWR_CV_MSK_G, 354 PWR_INTF_MSK_USB, 355 PWR_BASE_MAC, 356 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 357 {0x1086, 358 PWR_CV_MSK_ALL, 359 PWR_INTF_MSK_SDIO, 360 PWR_BASE_MAC, 361 PWR_CMD_WRITE, BIT(0), BIT(0)}, 362 {0x1086, 363 PWR_CV_MSK_ALL, 364 PWR_INTF_MSK_SDIO, 365 PWR_BASE_MAC, 366 PWR_CMD_POLL, BIT(1), 0}, 367 {0xFFFF, 368 PWR_CV_MSK_ALL, 369 PWR_INTF_MSK_ALL, 370 0, 371 PWR_CMD_END, 0, 0}, 372 }; 373 374 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = { 375 rtw8852a_pwron, NULL 376 }; 377 378 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = { 379 rtw8852a_pwroff, NULL 380 }; 381 382 static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = { 383 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 384 R_AX_H2CREG_DATA3 385 }; 386 387 static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = { 388 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 389 R_AX_C2HREG_DATA3 390 }; 391 392 static const struct rtw89_page_regs rtw8852a_page_regs = { 393 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 394 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 395 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 396 .ach_page_info = R_AX_ACH0_PAGE_INFO, 397 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 398 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 399 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 400 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 401 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 402 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 403 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 404 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 405 }; 406 407 static const struct rtw89_reg_def rtw8852a_dcfo_comp = { 408 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 409 }; 410 411 static const struct rtw89_imr_info rtw8852a_imr_info = { 412 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 413 .wsec_imr_reg = R_AX_SEC_DEBUG, 414 .wsec_imr_set = B_AX_IMR_ERROR, 415 .mpdu_tx_imr_set = 0, 416 .mpdu_rx_imr_set = 0, 417 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 418 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 419 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 420 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 421 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 422 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 423 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 424 .wde_imr_clr = B_AX_WDE_IMR_CLR, 425 .wde_imr_set = B_AX_WDE_IMR_SET, 426 .ple_imr_clr = B_AX_PLE_IMR_CLR, 427 .ple_imr_set = B_AX_PLE_IMR_SET, 428 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 429 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 430 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 431 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 432 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 433 .other_disp_imr_set = 0, 434 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 435 .bbrpt_err_imr_set = 0, 436 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 437 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR, 438 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 439 .cdma_imr_0_reg = R_AX_DLE_CTRL, 440 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 441 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 442 .cdma_imr_1_reg = 0, 443 .cdma_imr_1_clr = 0, 444 .cdma_imr_1_set = 0, 445 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 446 .phy_intf_imr_clr = 0, 447 .phy_intf_imr_set = 0, 448 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 449 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 450 .rmac_imr_set = B_AX_RMAC_IMR_SET, 451 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 452 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 453 .tmac_imr_set = B_AX_TMAC_IMR_SET, 454 }; 455 456 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, 457 struct rtw8852a_efuse *map) 458 { 459 ether_addr_copy(efuse->addr, map->e.mac_addr); 460 efuse->rfe_type = map->rfe_type; 461 efuse->xtal_cap = map->xtal_k; 462 } 463 464 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 465 struct rtw8852a_efuse *map) 466 { 467 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 468 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 469 u8 i, j; 470 471 tssi->thermal[RF_PATH_A] = map->path_a_therm; 472 tssi->thermal[RF_PATH_B] = map->path_b_therm; 473 474 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 475 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 476 sizeof(ofst[i]->cck_tssi)); 477 478 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 479 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 480 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 481 i, j, tssi->tssi_cck[i][j]); 482 483 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 484 sizeof(ofst[i]->bw40_tssi)); 485 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 486 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 487 488 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 489 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 490 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 491 i, j, tssi->tssi_mcs[i][j]); 492 } 493 } 494 495 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) 496 { 497 struct rtw89_efuse *efuse = &rtwdev->efuse; 498 struct rtw8852a_efuse *map; 499 500 map = (struct rtw8852a_efuse *)log_map; 501 502 efuse->country_code[0] = map->country_code[0]; 503 efuse->country_code[1] = map->country_code[1]; 504 rtw8852a_efuse_parsing_tssi(rtwdev, map); 505 506 switch (rtwdev->hci.type) { 507 case RTW89_HCI_TYPE_PCIE: 508 rtw8852ae_efuse_parsing(efuse, map); 509 break; 510 default: 511 return -ENOTSUPP; 512 } 513 514 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 515 516 return 0; 517 } 518 519 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 520 { 521 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 522 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB}; 523 u32 addr = rtwdev->chip->phycap_addr; 524 bool pg = false; 525 u32 ofst; 526 u8 i, j; 527 528 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 529 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 530 /* addrs are in decreasing order */ 531 ofst = tssi_trim_addr[i] - addr - j; 532 tssi->tssi_trim[i][j] = phycap_map[ofst]; 533 534 if (phycap_map[ofst] != 0xff) 535 pg = true; 536 } 537 } 538 539 if (!pg) { 540 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 541 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 542 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 543 } 544 545 for (i = 0; i < RF_PATH_NUM_8852A; i++) 546 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 547 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 548 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 549 i, j, tssi->tssi_trim[i][j], 550 tssi_trim_addr[i] - j); 551 } 552 553 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 554 u8 *phycap_map) 555 { 556 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 557 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC}; 558 u32 addr = rtwdev->chip->phycap_addr; 559 u8 i; 560 561 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 562 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 563 564 rtw89_debug(rtwdev, RTW89_DBG_RFK, 565 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 566 i, info->thermal_trim[i]); 567 568 if (info->thermal_trim[i] != 0xff) 569 info->pg_thermal_trim = true; 570 } 571 } 572 573 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev) 574 { 575 #define __thm_setting(raw) \ 576 ({ \ 577 u8 __v = (raw); \ 578 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 579 }) 580 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 581 u8 i, val; 582 583 if (!info->pg_thermal_trim) { 584 rtw89_debug(rtwdev, RTW89_DBG_RFK, 585 "[THERMAL][TRIM] no PG, do nothing\n"); 586 587 return; 588 } 589 590 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 591 val = __thm_setting(info->thermal_trim[i]); 592 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 593 594 rtw89_debug(rtwdev, RTW89_DBG_RFK, 595 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 596 i, val); 597 } 598 #undef __thm_setting 599 } 600 601 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 602 u8 *phycap_map) 603 { 604 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 605 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB}; 606 u32 addr = rtwdev->chip->phycap_addr; 607 u8 i; 608 609 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 610 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 611 612 rtw89_debug(rtwdev, RTW89_DBG_RFK, 613 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 614 i, info->pa_bias_trim[i]); 615 616 if (info->pa_bias_trim[i] != 0xff) 617 info->pg_pa_bias_trim = true; 618 } 619 } 620 621 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev) 622 { 623 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 624 u8 pabias_2g, pabias_5g; 625 u8 i; 626 627 if (!info->pg_pa_bias_trim) { 628 rtw89_debug(rtwdev, RTW89_DBG_RFK, 629 "[PA_BIAS][TRIM] no PG, do nothing\n"); 630 631 return; 632 } 633 634 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 635 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 636 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 637 638 rtw89_debug(rtwdev, RTW89_DBG_RFK, 639 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 640 i, pabias_2g, pabias_5g); 641 642 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 643 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 644 } 645 } 646 647 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 648 { 649 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map); 650 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map); 651 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 652 653 return 0; 654 } 655 656 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev) 657 { 658 rtw8852a_thermal_trim(rtwdev); 659 rtw8852a_pa_bias_trim(rtwdev); 660 } 661 662 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, 663 const struct rtw89_chan *chan, 664 u8 mac_idx) 665 { 666 u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); 667 u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, 668 mac_idx); 669 u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); 670 u8 txsc20 = 0, txsc40 = 0; 671 672 switch (chan->band_width) { 673 case RTW89_CHANNEL_WIDTH_80: 674 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 675 RTW89_CHANNEL_WIDTH_40); 676 fallthrough; 677 case RTW89_CHANNEL_WIDTH_40: 678 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 679 RTW89_CHANNEL_WIDTH_20); 680 break; 681 default: 682 break; 683 } 684 685 switch (chan->band_width) { 686 case RTW89_CHANNEL_WIDTH_80: 687 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 688 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 689 break; 690 case RTW89_CHANNEL_WIDTH_40: 691 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 692 rtw89_write32(rtwdev, sub_carr, txsc20); 693 break; 694 case RTW89_CHANNEL_WIDTH_20: 695 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 696 rtw89_write32(rtwdev, sub_carr, 0); 697 break; 698 default: 699 break; 700 } 701 702 if (chan->channel > 14) 703 rtw89_write8_set(rtwdev, chk_rate, 704 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 705 else 706 rtw89_write8_clr(rtwdev, chk_rate, 707 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 708 } 709 710 static const u32 rtw8852a_sco_barker_threshold[14] = { 711 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 712 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 713 }; 714 715 static const u32 rtw8852a_sco_cck_threshold[14] = { 716 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 717 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 718 }; 719 720 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 721 u8 primary_ch, enum rtw89_bandwidth bw) 722 { 723 u8 ch_element; 724 725 if (bw == RTW89_CHANNEL_WIDTH_20) { 726 ch_element = central_ch - 1; 727 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 728 if (primary_ch == 1) 729 ch_element = central_ch - 1 + 2; 730 else 731 ch_element = central_ch - 1 - 2; 732 } else { 733 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 734 return -EINVAL; 735 } 736 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 737 rtw8852a_sco_barker_threshold[ch_element]); 738 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 739 rtw8852a_sco_cck_threshold[ch_element]); 740 741 return 0; 742 } 743 744 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch, 745 u8 path) 746 { 747 u32 val; 748 749 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 750 if (val == INV_RF_DATA) { 751 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 752 return; 753 } 754 val &= ~0x303ff; 755 val |= central_ch; 756 if (central_ch > 14) 757 val |= (BIT(16) | BIT(8)); 758 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 759 } 760 761 static u8 rtw8852a_sco_mapping(u8 central_ch) 762 { 763 if (central_ch == 1) 764 return 109; 765 else if (central_ch >= 2 && central_ch <= 6) 766 return 108; 767 else if (central_ch >= 7 && central_ch <= 10) 768 return 107; 769 else if (central_ch >= 11 && central_ch <= 14) 770 return 106; 771 else if (central_ch == 36 || central_ch == 38) 772 return 51; 773 else if (central_ch >= 40 && central_ch <= 58) 774 return 50; 775 else if (central_ch >= 60 && central_ch <= 64) 776 return 49; 777 else if (central_ch == 100 || central_ch == 102) 778 return 48; 779 else if (central_ch >= 104 && central_ch <= 126) 780 return 47; 781 else if (central_ch >= 128 && central_ch <= 151) 782 return 46; 783 else if (central_ch >= 153 && central_ch <= 177) 784 return 45; 785 else 786 return 0; 787 } 788 789 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, 790 enum rtw89_phy_idx phy_idx) 791 { 792 u8 sco_comp; 793 bool is_2g = central_ch <= 14; 794 795 if (phy_idx == RTW89_PHY_0) { 796 /* Path A */ 797 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A); 798 if (is_2g) 799 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 800 B_PATH0_TIA_ERR_G1_SEL, 1, 801 phy_idx); 802 else 803 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 804 B_PATH0_TIA_ERR_G1_SEL, 0, 805 phy_idx); 806 807 /* Path B */ 808 if (!rtwdev->dbcc_en) { 809 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 810 if (is_2g) 811 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 812 B_P1_MODE_SEL, 813 1, phy_idx); 814 else 815 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 816 B_P1_MODE_SEL, 817 0, phy_idx); 818 } else { 819 if (is_2g) 820 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, 821 B_2P4G_BAND_SEL); 822 else 823 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, 824 B_2P4G_BAND_SEL); 825 } 826 /* SCO compensate FC setting */ 827 sco_comp = rtw8852a_sco_mapping(central_ch); 828 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 829 sco_comp, phy_idx); 830 } else { 831 /* Path B */ 832 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 833 if (is_2g) 834 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 835 B_P1_MODE_SEL, 836 1, phy_idx); 837 else 838 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 839 B_P1_MODE_SEL, 840 0, phy_idx); 841 /* SCO compensate FC setting */ 842 sco_comp = rtw8852a_sco_mapping(central_ch); 843 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 844 sco_comp, phy_idx); 845 } 846 847 /* Band edge */ 848 if (is_2g) 849 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1, 850 phy_idx); 851 else 852 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0, 853 phy_idx); 854 855 /* CCK parameters */ 856 if (central_ch == 14) { 857 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 858 0x3b13ff); 859 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 860 0x1c42de); 861 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 862 0xfdb0ad); 863 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 864 0xf60f6e); 865 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 866 0xfd8f92); 867 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 868 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 869 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 870 0xfff00a); 871 } else { 872 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 873 0x3d23ff); 874 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 875 0x29b354); 876 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 877 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 878 0xfdb053); 879 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 880 0xf86f9a); 881 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 882 0xfaef92); 883 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 884 0xfe5fcc); 885 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 886 0xffdff5); 887 } 888 } 889 890 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 891 { 892 u32 val = 0; 893 u32 adc_sel[2] = {0x12d0, 0x32d0}; 894 u32 wbadc_sel[2] = {0x12ec, 0x32ec}; 895 896 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 897 if (val == INV_RF_DATA) { 898 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 899 return; 900 } 901 val &= ~(BIT(11) | BIT(10)); 902 switch (bw) { 903 case RTW89_CHANNEL_WIDTH_5: 904 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 905 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 906 val |= (BIT(11) | BIT(10)); 907 break; 908 case RTW89_CHANNEL_WIDTH_10: 909 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 910 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 911 val |= (BIT(11) | BIT(10)); 912 break; 913 case RTW89_CHANNEL_WIDTH_20: 914 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 915 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 916 val |= (BIT(11) | BIT(10)); 917 break; 918 case RTW89_CHANNEL_WIDTH_40: 919 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 920 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 921 val |= BIT(11); 922 break; 923 case RTW89_CHANNEL_WIDTH_80: 924 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 925 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 926 val |= BIT(10); 927 break; 928 default: 929 rtw89_warn(rtwdev, "Fail to set ADC\n"); 930 } 931 932 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 933 } 934 935 static void 936 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 937 enum rtw89_phy_idx phy_idx) 938 { 939 /* Switch bandwidth */ 940 switch (bw) { 941 case RTW89_CHANNEL_WIDTH_5: 942 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 943 phy_idx); 944 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1, 945 phy_idx); 946 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 947 0x0, phy_idx); 948 break; 949 case RTW89_CHANNEL_WIDTH_10: 950 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 951 phy_idx); 952 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2, 953 phy_idx); 954 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 955 0x0, phy_idx); 956 break; 957 case RTW89_CHANNEL_WIDTH_20: 958 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 959 phy_idx); 960 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 961 phy_idx); 962 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 963 0x0, phy_idx); 964 break; 965 case RTW89_CHANNEL_WIDTH_40: 966 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 967 phy_idx); 968 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 969 phy_idx); 970 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 971 pri_ch, 972 phy_idx); 973 if (pri_ch == RTW89_SC_20_UPPER) 974 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 975 else 976 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 977 break; 978 case RTW89_CHANNEL_WIDTH_80: 979 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 980 phy_idx); 981 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 982 phy_idx); 983 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 984 pri_ch, 985 phy_idx); 986 break; 987 default: 988 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 989 pri_ch); 990 } 991 992 if (phy_idx == RTW89_PHY_0) { 993 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A); 994 if (!rtwdev->dbcc_en) 995 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 996 } else { 997 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 998 } 999 } 1000 1001 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch) 1002 { 1003 if (central_ch == 153) { 1004 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1005 0x210); 1006 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1007 0x210); 1008 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x7c0); 1009 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1010 B_P0_NBIIDX_NOTCH_EN, 0x1); 1011 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1012 B_P1_NBIIDX_NOTCH_EN, 0x1); 1013 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1014 0x1); 1015 } else if (central_ch == 151) { 1016 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1017 0x210); 1018 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1019 0x210); 1020 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x40); 1021 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1022 B_P0_NBIIDX_NOTCH_EN, 0x1); 1023 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1024 B_P1_NBIIDX_NOTCH_EN, 0x1); 1025 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1026 0x1); 1027 } else if (central_ch == 155) { 1028 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1029 0x2d0); 1030 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1031 0x2d0); 1032 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x740); 1033 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1034 B_P0_NBIIDX_NOTCH_EN, 0x1); 1035 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1036 B_P1_NBIIDX_NOTCH_EN, 0x1); 1037 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1038 0x1); 1039 } else { 1040 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1041 B_P0_NBIIDX_NOTCH_EN, 0x0); 1042 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1043 B_P1_NBIIDX_NOTCH_EN, 0x0); 1044 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1045 0x0); 1046 } 1047 } 1048 1049 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev, 1050 enum rtw89_phy_idx phy_idx) 1051 { 1052 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1053 phy_idx); 1054 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1055 phy_idx); 1056 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1057 phy_idx); 1058 } 1059 1060 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev, 1061 enum rtw89_phy_idx phy_idx, bool en) 1062 { 1063 if (en) 1064 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1065 1, 1066 phy_idx); 1067 else 1068 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1069 0, 1070 phy_idx); 1071 } 1072 1073 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev, 1074 enum rtw89_phy_idx phy_idx) 1075 { 1076 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1077 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1078 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1079 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1080 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1081 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1082 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1083 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1084 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1085 } 1086 1087 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1088 enum rtw89_phy_idx phy_idx) 1089 { 1090 u32 addr; 1091 1092 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1093 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1094 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1095 } 1096 1097 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) 1098 { 1099 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1100 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1101 1102 if (rtwdev->hal.cv <= CHIP_CCV) { 1103 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG); 1104 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000); 1105 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F); 1106 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF); 1107 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST); 1108 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1109 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1110 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME); 1111 } 1112 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f); 1113 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c); 1114 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1115 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1); 1116 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK); 1117 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK); 1118 1119 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1120 } 1121 1122 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev, 1123 enum rtw89_phy_idx phy_idx) 1124 { 1125 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1126 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1127 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1128 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1129 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1130 udelay(1); 1131 } 1132 1133 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, 1134 const struct rtw89_chan *chan, 1135 enum rtw89_phy_idx phy_idx) 1136 { 1137 bool cck_en = chan->channel <= 14; 1138 u8 pri_ch_idx = chan->pri_ch_idx; 1139 1140 if (cck_en) 1141 rtw8852a_ctrl_sco_cck(rtwdev, chan->channel, 1142 chan->primary_channel, 1143 chan->band_width); 1144 1145 rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx); 1146 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1147 if (cck_en) { 1148 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1149 } else { 1150 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1151 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); 1152 } 1153 rtw8852a_spur_elimination(rtwdev, chan->channel); 1154 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, 1155 chan->primary_channel); 1156 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1157 } 1158 1159 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev, 1160 const struct rtw89_chan *chan, 1161 enum rtw89_mac_idx mac_idx, 1162 enum rtw89_phy_idx phy_idx) 1163 { 1164 rtw8852a_set_channel_mac(rtwdev, chan, mac_idx); 1165 rtw8852a_set_channel_bb(rtwdev, chan, phy_idx); 1166 } 1167 1168 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en) 1169 { 1170 if (en) 1171 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1172 else 1173 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1174 } 1175 1176 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1177 enum rtw89_rf_path path) 1178 { 1179 static const u32 tssi_trk[2] = {0x5818, 0x7818}; 1180 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc}; 1181 1182 if (en) { 1183 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0); 1184 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); 1185 } else { 1186 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1); 1187 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); 1188 } 1189 } 1190 1191 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1192 u8 phy_idx) 1193 { 1194 if (!rtwdev->dbcc_en) { 1195 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1196 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1197 } else { 1198 if (phy_idx == RTW89_PHY_0) 1199 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1200 else 1201 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1202 } 1203 } 1204 1205 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en) 1206 { 1207 if (en) 1208 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1209 0x0); 1210 else 1211 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1212 0xf); 1213 } 1214 1215 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1216 struct rtw89_channel_help_params *p, 1217 const struct rtw89_chan *chan, 1218 enum rtw89_mac_idx mac_idx, 1219 enum rtw89_phy_idx phy_idx) 1220 { 1221 if (enter) { 1222 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1223 RTW89_SCH_TX_SEL_ALL); 1224 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1225 rtw8852a_dfs_en(rtwdev, false); 1226 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1227 rtw8852a_adc_en(rtwdev, false); 1228 fsleep(40); 1229 rtw8852a_bb_reset_en(rtwdev, phy_idx, false); 1230 } else { 1231 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1232 rtw8852a_adc_en(rtwdev, true); 1233 rtw8852a_dfs_en(rtwdev, true); 1234 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1235 rtw8852a_bb_reset_en(rtwdev, phy_idx, true); 1236 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1237 } 1238 } 1239 1240 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev) 1241 { 1242 struct rtw89_efuse *efuse = &rtwdev->efuse; 1243 1244 switch (efuse->rfe_type) { 1245 case 11: 1246 case 12: 1247 case 17: 1248 case 18: 1249 case 51: 1250 case 53: 1251 rtwdev->fem.epa_2g = true; 1252 rtwdev->fem.elna_2g = true; 1253 fallthrough; 1254 case 9: 1255 case 10: 1256 case 15: 1257 case 16: 1258 rtwdev->fem.epa_5g = true; 1259 rtwdev->fem.elna_5g = true; 1260 break; 1261 default: 1262 break; 1263 } 1264 } 1265 1266 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev) 1267 { 1268 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1269 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1270 1271 rtw8852a_rck(rtwdev); 1272 rtw8852a_dack(rtwdev); 1273 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true); 1274 } 1275 1276 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev) 1277 { 1278 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1279 1280 rtw8852a_rx_dck(rtwdev, phy_idx, true); 1281 rtw8852a_iqk(rtwdev, phy_idx); 1282 rtw8852a_tssi(rtwdev, phy_idx); 1283 rtw8852a_dpk(rtwdev, phy_idx); 1284 } 1285 1286 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev, 1287 enum rtw89_phy_idx phy_idx) 1288 { 1289 rtw8852a_tssi_scan(rtwdev, phy_idx); 1290 } 1291 1292 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1293 { 1294 rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1295 } 1296 1297 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev) 1298 { 1299 rtw8852a_dpk_track(rtwdev); 1300 rtw8852a_iqk_track(rtwdev); 1301 rtw8852a_tssi_track(rtwdev); 1302 } 1303 1304 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1305 enum rtw89_phy_idx phy_idx, s16 ref) 1306 { 1307 s8 ofst_int = 0; 1308 u8 base_cw_0db = 0x27; 1309 u16 tssi_16dbm_cw = 0x12c; 1310 s16 pwr_s10_3 = 0; 1311 s16 rf_pwr_cw = 0; 1312 u16 bb_pwr_cw = 0; 1313 u32 pwr_cw = 0; 1314 u32 tssi_ofst_cw = 0; 1315 1316 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1317 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1318 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1319 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1320 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1321 1322 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1323 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1324 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1325 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1326 1327 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1328 } 1329 1330 static 1331 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1332 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1333 { 1334 s8 val_1t = 0; 1335 s8 val_2t = 0; 1336 u32 reg; 1337 1338 if (pw_ofst < -16 || pw_ofst > 15) { 1339 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n", 1340 pw_ofst); 1341 return; 1342 } 1343 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx); 1344 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1345 val_1t = pw_ofst; 1346 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); 1347 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); 1348 val_2t = max(val_1t - 3, -16); 1349 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); 1350 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); 1351 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", 1352 val_1t, val_2t); 1353 } 1354 1355 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev, 1356 enum rtw89_phy_idx phy_idx) 1357 { 1358 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800}; 1359 const u32 mask = 0x7FFFFFF; 1360 const u8 ofst_ofdm = 0x4; 1361 const u8 ofst_cck = 0x8; 1362 s16 ref_ofdm = 0; 1363 s16 ref_cck = 0; 1364 u32 val; 1365 u8 i; 1366 1367 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1368 1369 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1370 GENMASK(27, 10), 0x0); 1371 1372 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1373 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1374 1375 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1376 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1377 phy_idx); 1378 1379 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1380 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1381 1382 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1383 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1384 phy_idx); 1385 } 1386 1387 static void rtw8852a_set_txpwr_byrate(struct rtw89_dev *rtwdev, 1388 const struct rtw89_chan *chan, 1389 enum rtw89_phy_idx phy_idx) 1390 { 1391 u8 band = chan->band_type; 1392 u8 ch = chan->channel; 1393 static const u8 rs[] = { 1394 RTW89_RS_CCK, 1395 RTW89_RS_OFDM, 1396 RTW89_RS_MCS, 1397 RTW89_RS_HEDCM, 1398 }; 1399 s8 tmp; 1400 u8 i, j; 1401 u32 val, shf, addr = R_AX_PWR_BY_RATE; 1402 struct rtw89_rate_desc cur; 1403 1404 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1405 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 1406 1407 for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) { 1408 for (i = 0; i < ARRAY_SIZE(rs); i++) { 1409 if (cur.nss >= rtw89_rs_nss_max[rs[i]]) 1410 continue; 1411 1412 val = 0; 1413 cur.rs = rs[i]; 1414 1415 for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) { 1416 cur.idx = j; 1417 shf = (j % 4) * 8; 1418 tmp = rtw89_phy_read_txpwr_byrate(rtwdev, band, 1419 &cur); 1420 val |= (tmp << shf); 1421 1422 if ((j + 1) % 4) 1423 continue; 1424 1425 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1426 val = 0; 1427 addr += 4; 1428 } 1429 } 1430 } 1431 } 1432 1433 static void rtw8852a_set_txpwr_offset(struct rtw89_dev *rtwdev, 1434 const struct rtw89_chan *chan, 1435 enum rtw89_phy_idx phy_idx) 1436 { 1437 u8 band = chan->band_type; 1438 struct rtw89_rate_desc desc = { 1439 .nss = RTW89_NSS_1, 1440 .rs = RTW89_RS_OFFSET, 1441 }; 1442 u32 val = 0; 1443 s8 v; 1444 1445 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 1446 1447 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) { 1448 v = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc); 1449 val |= ((v & 0xf) << (4 * desc.idx)); 1450 } 1451 1452 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 1453 GENMASK(19, 0), val); 1454 } 1455 1456 static void rtw8852a_set_txpwr_limit(struct rtw89_dev *rtwdev, 1457 const struct rtw89_chan *chan, 1458 enum rtw89_phy_idx phy_idx) 1459 { 1460 #define __MAC_TXPWR_LMT_PAGE_SIZE 40 1461 u8 ch = chan->channel; 1462 u8 bw = chan->band_width; 1463 struct rtw89_txpwr_limit lmt[NTX_NUM_8852A]; 1464 u32 addr, val; 1465 const s8 *ptr; 1466 u8 i, j; 1467 1468 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1469 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 1470 1471 for (i = 0; i < NTX_NUM_8852A; i++) { 1472 rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt[i], i); 1473 1474 for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) { 1475 addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i; 1476 ptr = (s8 *)&lmt[i] + j; 1477 1478 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 1479 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 1480 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 1481 FIELD_PREP(GENMASK(31, 24), ptr[3]); 1482 1483 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1484 } 1485 } 1486 #undef __MAC_TXPWR_LMT_PAGE_SIZE 1487 } 1488 1489 static void rtw8852a_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1490 const struct rtw89_chan *chan, 1491 enum rtw89_phy_idx phy_idx) 1492 { 1493 #define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24 1494 u8 ch = chan->channel; 1495 u8 bw = chan->band_width; 1496 struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852A]; 1497 u32 addr, val; 1498 const s8 *ptr; 1499 u8 i, j; 1500 1501 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1502 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 1503 1504 for (i = 0; i < NTX_NUM_8852A; i++) { 1505 rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru[i], i); 1506 1507 for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) { 1508 addr = R_AX_PWR_RU_LMT + j + 1509 __MAC_TXPWR_LMT_RU_PAGE_SIZE * i; 1510 ptr = (s8 *)&lmt_ru[i] + j; 1511 1512 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 1513 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 1514 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 1515 FIELD_PREP(GENMASK(31, 24), ptr[3]); 1516 1517 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1518 } 1519 } 1520 1521 #undef __MAC_TXPWR_LMT_RU_PAGE_SIZE 1522 } 1523 1524 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev, 1525 const struct rtw89_chan *chan, 1526 enum rtw89_phy_idx phy_idx) 1527 { 1528 rtw8852a_set_txpwr_byrate(rtwdev, chan, phy_idx); 1529 rtw8852a_set_txpwr_offset(rtwdev, chan, phy_idx); 1530 rtw8852a_set_txpwr_limit(rtwdev, chan, phy_idx); 1531 rtw8852a_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1532 } 1533 1534 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1535 enum rtw89_phy_idx phy_idx) 1536 { 1537 rtw8852a_set_txpwr_ref(rtwdev, phy_idx); 1538 } 1539 1540 static int 1541 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1542 { 1543 int ret; 1544 1545 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1546 if (ret) 1547 return ret; 1548 1549 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004); 1550 if (ret) 1551 return ret; 1552 1553 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1554 if (ret) 1555 return ret; 1556 1557 return 0; 1558 } 1559 1560 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1561 { 1562 u8 i = 0; 1563 u32 addr, val; 1564 1565 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) { 1566 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr; 1567 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data; 1568 rtw89_phy_write32(rtwdev, addr, val); 1569 } 1570 } 1571 1572 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev, 1573 struct rtw8852a_bb_pmac_info *tx_info, 1574 enum rtw89_phy_idx idx) 1575 { 1576 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1577 if (tx_info->mode == CONT_TX) 1578 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, 1579 idx); 1580 else if (tx_info->mode == PKTS_TX) 1581 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, 1582 idx); 1583 } 1584 1585 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev, 1586 struct rtw8852a_bb_pmac_info *tx_info, 1587 enum rtw89_phy_idx idx) 1588 { 1589 enum rtw8852a_pmac_mode mode = tx_info->mode; 1590 u32 pkt_cnt = tx_info->tx_cnt; 1591 u16 period = tx_info->period; 1592 1593 if (mode == CONT_TX && !tx_info->is_cck) { 1594 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, 1595 idx); 1596 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1597 } else if (mode == PKTS_TX) { 1598 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, 1599 idx); 1600 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1601 B_PMAC_TX_PRD_MSK, period, idx); 1602 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1603 pkt_cnt, idx); 1604 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1605 } 1606 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1607 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1608 } 1609 1610 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1611 struct rtw8852a_bb_pmac_info *tx_info, 1612 enum rtw89_phy_idx idx) 1613 { 1614 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1615 1616 if (!tx_info->en_pmac_tx) { 1617 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx); 1618 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1619 if (chan->band_type == RTW89_BAND_2G) 1620 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1621 return; 1622 } 1623 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1624 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1625 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1626 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, 1627 idx); 1628 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1629 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1630 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1631 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1632 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx); 1633 } 1634 1635 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1636 u16 tx_cnt, u16 period, u16 tx_time, 1637 enum rtw89_phy_idx idx) 1638 { 1639 struct rtw8852a_bb_pmac_info tx_info = {0}; 1640 1641 tx_info.en_pmac_tx = enable; 1642 tx_info.is_cck = 0; 1643 tx_info.mode = PKTS_TX; 1644 tx_info.tx_cnt = tx_cnt; 1645 tx_info.period = period; 1646 tx_info.tx_time = tx_time; 1647 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx); 1648 } 1649 1650 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1651 enum rtw89_phy_idx idx) 1652 { 1653 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1654 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1655 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1656 } 1657 1658 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1659 { 1660 u32 rst_mask0 = 0; 1661 u32 rst_mask1 = 0; 1662 1663 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1664 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1); 1665 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1666 if (!rtwdev->dbcc_en) { 1667 if (tx_path == RF_PATH_A) { 1668 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1669 B_TXPATH_SEL_MSK, 1); 1670 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1671 B_TXNSS_MAP_MSK, 0); 1672 } else if (tx_path == RF_PATH_B) { 1673 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1674 B_TXPATH_SEL_MSK, 2); 1675 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1676 B_TXNSS_MAP_MSK, 0); 1677 } else if (tx_path == RF_PATH_AB) { 1678 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1679 B_TXPATH_SEL_MSK, 3); 1680 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1681 B_TXNSS_MAP_MSK, 4); 1682 } else { 1683 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1684 } 1685 } else { 1686 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1687 1); 1688 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2, 1689 RTW89_PHY_1); 1690 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 1691 0); 1692 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4, 1693 RTW89_PHY_1); 1694 } 1695 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1696 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1697 if (tx_path == RF_PATH_A) { 1698 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1699 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1700 } else { 1701 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1702 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1703 } 1704 } 1705 1706 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1707 enum rtw89_phy_idx idx, u8 mode) 1708 { 1709 if (mode != 0) 1710 return; 1711 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1712 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1713 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1714 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1715 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1716 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1717 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1718 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1719 } 1720 1721 static void rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) 1722 { 1723 rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852a_btc_preagc_en_defs_tbl : 1724 &rtw8852a_btc_preagc_dis_defs_tbl); 1725 } 1726 1727 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1728 { 1729 if (rtwdev->is_tssi_mode[rf_path]) { 1730 u32 addr = 0x1c10 + (rf_path << 13); 1731 1732 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 1733 } 1734 1735 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1736 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1737 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1738 1739 fsleep(200); 1740 1741 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1742 } 1743 1744 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) 1745 { 1746 struct rtw89_btc *btc = &rtwdev->btc; 1747 struct rtw89_btc_module *module = &btc->mdinfo; 1748 1749 module->rfe_type = rtwdev->efuse.rfe_type; 1750 module->cv = rtwdev->hal.cv; 1751 module->bt_solo = 0; 1752 module->switch_type = BTC_SWITCH_INTERNAL; 1753 1754 if (module->rfe_type > 0) 1755 module->ant.num = (module->rfe_type % 2 ? 2 : 3); 1756 else 1757 module->ant.num = 2; 1758 1759 module->ant.diversity = 0; 1760 module->ant.isolation = 10; 1761 1762 if (module->ant.num == 3) { 1763 module->ant.type = BTC_ANT_DEDICATED; 1764 module->bt_pos = BTC_BT_ALONE; 1765 } else { 1766 module->ant.type = BTC_ANT_SHARED; 1767 module->bt_pos = BTC_BT_BTG; 1768 } 1769 } 1770 1771 static 1772 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 1773 { 1774 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000); 1775 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group); 1776 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val); 1777 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0); 1778 } 1779 1780 static void rtw8852a_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 1781 { 1782 if (btg) { 1783 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1); 1784 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3); 1785 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1786 } else { 1787 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0); 1788 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0); 1789 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 1790 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 1791 } 1792 } 1793 1794 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) 1795 { 1796 struct rtw89_btc *btc = &rtwdev->btc; 1797 struct rtw89_btc_module *module = &btc->mdinfo; 1798 const struct rtw89_chip_info *chip = rtwdev->chip; 1799 const struct rtw89_mac_ax_coex coex_params = { 1800 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 1801 .direction = RTW89_MAC_AX_COEX_INNER, 1802 }; 1803 1804 /* PTA init */ 1805 rtw89_mac_coex_init(rtwdev, &coex_params); 1806 1807 /* set WL Tx response = Hi-Pri */ 1808 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 1809 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 1810 1811 /* set rf gnt debug off */ 1812 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0); 1813 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); 1814 1815 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 1816 if (module->ant.type == BTC_ANT_SHARED) { 1817 rtw8852a_set_trx_mask(rtwdev, 1818 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 1819 rtw8852a_set_trx_mask(rtwdev, 1820 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 1821 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 1822 rtw8852a_set_trx_mask(rtwdev, 1823 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 1824 rtw8852a_set_trx_mask(rtwdev, 1825 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 1826 } 1827 1828 /* set PTA break table */ 1829 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 1830 1831 /* enable BT counter 0xda40[16,2] = 2b'11 */ 1832 rtw89_write32_set(rtwdev, 1833 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 1834 btc->cx.wl.status.map.init_ok = true; 1835 } 1836 1837 static 1838 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 1839 { 1840 u32 bitmap = 0; 1841 u32 reg = 0; 1842 1843 switch (map) { 1844 case BTC_PRI_MASK_TX_RESP: 1845 reg = R_BTC_BT_COEX_MSK_TABLE; 1846 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 1847 break; 1848 case BTC_PRI_MASK_BEACON: 1849 reg = R_AX_WL_PRI_MSK; 1850 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 1851 break; 1852 default: 1853 return; 1854 } 1855 1856 if (state) 1857 rtw89_write32_set(rtwdev, reg, bitmap); 1858 else 1859 rtw89_write32_clr(rtwdev, reg, bitmap); 1860 } 1861 1862 static inline u32 __btc_ctrl_val_all_time(u32 ctrl) 1863 { 1864 return FIELD_GET(GENMASK(15, 0), ctrl); 1865 } 1866 1867 static inline u32 __btc_ctrl_rst_all_time(u32 cur) 1868 { 1869 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN; 1870 } 1871 1872 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val) 1873 { 1874 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1875 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1876 1877 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN; 1878 } 1879 1880 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl) 1881 { 1882 return FIELD_GET(GENMASK(31, 16), ctrl); 1883 } 1884 1885 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur) 1886 { 1887 return cur & ~B_AX_TXAGC_BT_EN; 1888 } 1889 1890 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val) 1891 { 1892 u32 ov = cur & ~B_AX_TXAGC_BT_MASK; 1893 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val); 1894 1895 return ov | iv | B_AX_TXAGC_BT_EN; 1896 } 1897 1898 static void 1899 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 1900 { 1901 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL; 1902 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL; 1903 1904 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0)) 1905 #define __handle(_case) \ 1906 do { \ 1907 const u32 _reg = __btc_cr_ ## _case; \ 1908 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ 1909 u32 _cur, _wrt; \ 1910 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1911 "btc ctrl %s: 0x%x\n", #_case, _val); \ 1912 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\ 1913 break; \ 1914 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1915 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ 1916 _wrt = __do_clr(_val) ? \ 1917 __btc_ctrl_rst_ ## _case(_cur) : \ 1918 __btc_ctrl_gen_ ## _case(_cur, _val); \ 1919 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\ 1920 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1921 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \ 1922 } while (0) 1923 1924 __handle(all_time); 1925 __handle(gnt_bt); 1926 1927 #undef __handle 1928 #undef __do_clr 1929 } 1930 1931 static 1932 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 1933 { 1934 return clamp_t(s8, val, -100, 0) + 100; 1935 } 1936 1937 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = { 1938 {255, 0, 0, 7}, /* 0 -> original */ 1939 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 1940 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1941 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1942 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1943 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1944 {6, 1, 0, 7}, 1945 {13, 1, 0, 7}, 1946 {13, 1, 0, 7} 1947 }; 1948 1949 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = { 1950 {255, 0, 0, 7}, /* 0 -> original */ 1951 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 1952 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1953 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1954 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1955 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1956 {255, 1, 0, 7}, 1957 {255, 1, 0, 7}, 1958 {255, 1, 0, 7} 1959 }; 1960 1961 static const 1962 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 1963 static const 1964 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 1965 1966 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = { 1967 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 1968 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 1969 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 1970 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 1971 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 1972 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 1973 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 1974 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 1975 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 1976 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 1977 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 1978 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), 1979 }; 1980 1981 static 1982 void rtw8852a_btc_bt_aci_imp(struct rtw89_dev *rtwdev) 1983 { 1984 struct rtw89_btc *btc = &rtwdev->btc; 1985 struct rtw89_btc_dm *dm = &btc->dm; 1986 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 1987 struct rtw89_btc_bt_link_info *b = &bt->link_info; 1988 1989 /* fix LNA2 = level-5 for BT ACI issue at BTG */ 1990 if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0) 1991 dm->trx_para_level = 1; 1992 } 1993 1994 static 1995 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 1996 { 1997 struct rtw89_btc *btc = &rtwdev->btc; 1998 struct rtw89_btc_cx *cx = &btc->cx; 1999 u32 val; 2000 2001 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH); 2002 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val); 2003 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val); 2004 2005 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW); 2006 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val); 2007 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val); 2008 2009 /* clock-gate off before reset counter*/ 2010 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 2011 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 2012 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 2013 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 2014 } 2015 2016 static 2017 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2018 { 2019 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2020 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2021 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1); 2022 2023 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2024 if (state) 2025 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2026 RFREG_MASK, 0xa2d7c); 2027 else 2028 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2029 RFREG_MASK, 0xa2020); 2030 2031 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2032 } 2033 2034 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2035 struct rtw89_rx_phy_ppdu *phy_ppdu, 2036 struct ieee80211_rx_status *status) 2037 { 2038 u16 chan = phy_ppdu->chan_idx; 2039 u8 band; 2040 2041 if (chan == 0) 2042 return; 2043 2044 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 2045 status->freq = ieee80211_channel_to_frequency(chan, band); 2046 status->band = band; 2047 } 2048 2049 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, 2050 struct rtw89_rx_phy_ppdu *phy_ppdu, 2051 struct ieee80211_rx_status *status) 2052 { 2053 u8 path; 2054 s8 *rx_power = phy_ppdu->rssi; 2055 2056 status->signal = max_t(s8, rx_power[RF_PATH_A], rx_power[RF_PATH_B]); 2057 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2058 status->chains |= BIT(path); 2059 status->chain_signal[path] = rx_power[path]; 2060 } 2061 if (phy_ppdu->valid) 2062 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2063 } 2064 2065 static const struct rtw89_chip_ops rtw8852a_chip_ops = { 2066 .enable_bb_rf = rtw89_mac_enable_bb_rf, 2067 .disable_bb_rf = rtw89_mac_disable_bb_rf, 2068 .bb_reset = rtw8852a_bb_reset, 2069 .bb_sethw = rtw8852a_bb_sethw, 2070 .read_rf = rtw89_phy_read_rf, 2071 .write_rf = rtw89_phy_write_rf, 2072 .set_channel = rtw8852a_set_channel, 2073 .set_channel_help = rtw8852a_set_channel_help, 2074 .read_efuse = rtw8852a_read_efuse, 2075 .read_phycap = rtw8852a_read_phycap, 2076 .fem_setup = rtw8852a_fem_setup, 2077 .rfk_init = rtw8852a_rfk_init, 2078 .rfk_channel = rtw8852a_rfk_channel, 2079 .rfk_band_changed = rtw8852a_rfk_band_changed, 2080 .rfk_scan = rtw8852a_rfk_scan, 2081 .rfk_track = rtw8852a_rfk_track, 2082 .power_trim = rtw8852a_power_trim, 2083 .set_txpwr = rtw8852a_set_txpwr, 2084 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl, 2085 .init_txpwr_unit = rtw8852a_init_txpwr_unit, 2086 .get_thermal = rtw8852a_get_thermal, 2087 .ctrl_btg = rtw8852a_ctrl_btg, 2088 .query_ppdu = rtw8852a_query_ppdu, 2089 .bb_ctrl_btc_preagc = rtw8852a_bb_ctrl_btc_preagc, 2090 .cfg_txrx_path = NULL, 2091 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, 2092 .pwr_on_func = NULL, 2093 .pwr_off_func = NULL, 2094 .fill_txdesc = rtw89_core_fill_txdesc, 2095 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2096 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2097 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2098 .stop_sch_tx = rtw89_mac_stop_sch_tx, 2099 .resume_sch_tx = rtw89_mac_resume_sch_tx, 2100 .h2c_dctl_sec_cam = NULL, 2101 2102 .btc_set_rfe = rtw8852a_btc_set_rfe, 2103 .btc_init_cfg = rtw8852a_btc_init_cfg, 2104 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri, 2105 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, 2106 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, 2107 .btc_bt_aci_imp = rtw8852a_btc_bt_aci_imp, 2108 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, 2109 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, 2110 .btc_set_policy = rtw89_btc_set_policy, 2111 }; 2112 2113 const struct rtw89_chip_info rtw8852a_chip_info = { 2114 .chip_id = RTL8852A, 2115 .ops = &rtw8852a_chip_ops, 2116 .fw_name = "rtw89/rtw8852a_fw.bin", 2117 .fifo_size = 458752, 2118 .max_amsdu_limit = 3500, 2119 .dis_2g_40m_ul_ofdma = true, 2120 .rsvd_ple_ofst = 0x6f800, 2121 .hfc_param_ini = rtw8852a_hfc_param_ini_pcie, 2122 .dle_mem = rtw8852a_dle_mem_pcie, 2123 .rf_base_addr = {0xc000, 0xd000}, 2124 .pwr_on_seq = pwr_on_seq_8852a, 2125 .pwr_off_seq = pwr_off_seq_8852a, 2126 .bb_table = &rtw89_8852a_phy_bb_table, 2127 .bb_gain_table = NULL, 2128 .rf_table = {&rtw89_8852a_phy_radioa_table, 2129 &rtw89_8852a_phy_radiob_table,}, 2130 .nctl_table = &rtw89_8852a_phy_nctl_table, 2131 .byr_table = &rtw89_8852a_byr_table, 2132 .txpwr_lmt_2g = &rtw89_8852a_txpwr_lmt_2g, 2133 .txpwr_lmt_5g = &rtw89_8852a_txpwr_lmt_5g, 2134 .txpwr_lmt_ru_2g = &rtw89_8852a_txpwr_lmt_ru_2g, 2135 .txpwr_lmt_ru_5g = &rtw89_8852a_txpwr_lmt_ru_5g, 2136 .txpwr_factor_rf = 2, 2137 .txpwr_factor_mac = 1, 2138 .dig_table = &rtw89_8852a_phy_dig_table, 2139 .tssi_dbw_table = NULL, 2140 .support_chanctx_num = 1, 2141 .support_bands = BIT(NL80211_BAND_2GHZ) | 2142 BIT(NL80211_BAND_5GHZ), 2143 .support_bw160 = false, 2144 .hw_sec_hdr = false, 2145 .rf_path_num = 2, 2146 .tx_nss = 2, 2147 .rx_nss = 2, 2148 .acam_num = 128, 2149 .bcam_num = 10, 2150 .scam_num = 128, 2151 .bacam_num = 2, 2152 .bacam_dynamic_num = 4, 2153 .bacam_v1 = false, 2154 .sec_ctrl_efuse_size = 4, 2155 .physical_efuse_size = 1216, 2156 .logical_efuse_size = 1536, 2157 .limit_efuse_size = 1152, 2158 .dav_phy_efuse_size = 0, 2159 .dav_log_efuse_size = 0, 2160 .phycap_addr = 0x580, 2161 .phycap_size = 128, 2162 .para_ver = 0x05050864, 2163 .wlcx_desired = 0x05050000, 2164 .btcx_desired = 0x5, 2165 .scbd = 0x1, 2166 .mailbox = 0x1, 2167 2168 .fcxbtcrpt_ver = 1, 2169 .fcxtdma_ver = 1, 2170 .fcxslots_ver = 1, 2171 .fcxcysta_ver = 2, 2172 .fcxstep_ver = 2, 2173 .fcxnullsta_ver = 1, 2174 .fcxmreg_ver = 1, 2175 .fcxgpiodbg_ver = 1, 2176 .fcxbtver_ver = 1, 2177 .fcxbtscan_ver = 1, 2178 .fcxbtafh_ver = 1, 2179 .fcxbtdevinfo_ver = 1, 2180 2181 .afh_guard_ch = 6, 2182 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres, 2183 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres, 2184 .rssi_tol = 2, 2185 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg), 2186 .mon_reg = rtw89_btc_8852a_mon_reg, 2187 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul), 2188 .rf_para_ulink = rtw89_btc_8852a_rf_ul, 2189 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl), 2190 .rf_para_dlink = rtw89_btc_8852a_rf_dl, 2191 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2192 BIT(RTW89_PS_MODE_CLK_GATED) | 2193 BIT(RTW89_PS_MODE_PWR_GATED), 2194 .low_power_hci_modes = 0, 2195 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 2196 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 2197 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 2198 .txwd_body_size = sizeof(struct rtw89_txwd_body), 2199 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 2200 .h2c_regs = rtw8852a_h2c_regs, 2201 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 2202 .c2h_regs = rtw8852a_c2h_regs, 2203 .page_regs = &rtw8852a_page_regs, 2204 .dcfo_comp = &rtw8852a_dcfo_comp, 2205 .dcfo_comp_sft = 3, 2206 .imr_info = &rtw8852a_imr_info 2207 }; 2208 EXPORT_SYMBOL(rtw8852a_chip_info); 2209 2210 MODULE_FIRMWARE("rtw89/rtw8852a_fw.bin"); 2211 MODULE_AUTHOR("Realtek Corporation"); 2212 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver"); 2213 MODULE_LICENSE("Dual BSD/GPL");
Cache object: 332254dcf420b3558856cc5437b8ddec
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