1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2022 Realtek Corporation
3 */
4
5 #ifndef __RTW89_8852C_H__
6 #define __RTW89_8852C_H__
7
8 #include "core.h"
9
10 #define RF_PATH_NUM_8852C 2
11 #define BB_PATH_NUM_8852C 2
12 #define NTX_NUM_8852C 2
13
14 struct rtw8852c_u_efuse {
15 u8 rsvd[0x38];
16 u8 mac_addr[ETH_ALEN];
17 };
18
19 struct rtw8852c_e_efuse {
20 u8 mac_addr[ETH_ALEN];
21 };
22
23 struct rtw8852c_tssi_offset {
24 u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
25 u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
26 u8 rsvd[7];
27 u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
28 } __packed;
29
30 struct rtw8852c_efuse {
31 u8 rsvd[0x210];
32 struct rtw8852c_tssi_offset path_a_tssi;
33 u8 rsvd1[10];
34 struct rtw8852c_tssi_offset path_b_tssi;
35 u8 rsvd2[94];
36 u8 channel_plan;
37 u8 xtal_k;
38 u8 rsvd3;
39 u8 iqk_lck;
40 u8 rsvd4[5];
41 u8 reg_setting:2;
42 u8 tx_diversity:1;
43 u8 rx_diversity:2;
44 u8 ac_mode:1;
45 u8 module_type:2;
46 u8 rsvd5;
47 u8 shared_ant:1;
48 u8 coex_type:3;
49 u8 ant_iso:1;
50 u8 radio_on_off:1;
51 u8 rsvd6:2;
52 u8 eeprom_version;
53 u8 customer_id;
54 u8 tx_bb_swing_2g;
55 u8 tx_bb_swing_5g;
56 u8 tx_cali_pwr_trk_mode;
57 u8 trx_path_selection;
58 u8 rfe_type;
59 u8 country_code[2];
60 u8 rsvd7[3];
61 u8 path_a_therm;
62 u8 path_b_therm;
63 u8 rsvd8[2];
64 u8 rx_gain_2g_ofdm;
65 u8 rsvd9;
66 u8 rx_gain_2g_cck;
67 u8 rsvd10;
68 u8 rx_gain_5g_low;
69 u8 rsvd11;
70 u8 rx_gain_5g_mid;
71 u8 rsvd12;
72 u8 rx_gain_5g_high;
73 u8 rsvd13[35];
74 u8 bw40_1s_tssi_6g_a[TSSI_MCS_6G_CH_GROUP_NUM];
75 u8 rsvd14[10];
76 u8 bw40_1s_tssi_6g_b[TSSI_MCS_6G_CH_GROUP_NUM];
77 u8 rsvd15[110];
78 u8 channel_plan_6g;
79 u8 rsvd16[71];
80 union {
81 struct rtw8852c_u_efuse u;
82 struct rtw8852c_e_efuse e;
83 };
84 } __packed;
85
86 extern const struct rtw89_chip_info rtw8852c_chip_info;
87
88 #endif
Cache object: ecc44bd40a8c41d88a1737c972b62c93
|