arm,coresight-cpu-debug.yaml

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    1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: CoreSight CPU Debug Component
    8 
    9 maintainers:
   10   - Mathieu Poirier <mathieu.poirier@linaro.org>
   11   - Mike Leach <mike.leach@linaro.org>
   12   - Leo Yan <leo.yan@linaro.org>
   13   - Suzuki K Poulose <suzuki.poulose@arm.com>
   14 
   15 description: |
   16   CoreSight CPU debug component are compliant with the ARMv8 architecture
   17   reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
   18   external debug module is mainly used for two modes: self-hosted debug and
   19   external debug, and it can be accessed from mmio region from Coresight and
   20   eventually the debug module connects with CPU for debugging. And the debug
   21   module provides sample-based profiling extension, which can be used to sample
   22   CPU program counter, secure state and exception level, etc; usually every CPU
   23   has one dedicated debug module to be connected.
   24 
   25 select:
   26   properties:
   27     compatible:
   28       contains:
   29         const: arm,coresight-cpu-debug
   30   required:
   31     - compatible
   32 
   33 allOf:
   34   - $ref: /schemas/arm/primecell.yaml#
   35 
   36 properties:
   37   compatible:
   38     items:
   39       - const: arm,coresight-cpu-debug
   40       - const: arm,primecell
   41 
   42   reg:
   43     maxItems: 1
   44 
   45   clocks:
   46     maxItems: 1
   47 
   48   clock-names:
   49     maxItems: 1
   50 
   51   cpu:
   52     description:
   53       A phandle to the cpu this debug component is bound to.
   54     $ref: /schemas/types.yaml#/definitions/phandle
   55 
   56   power-domains:
   57     maxItems: 1
   58     description:
   59       A phandle to the debug power domain if the debug logic has its own
   60       dedicated power domain. CPU idle states may also need to be separately
   61       constrained to keep CPU cores powered.
   62 
   63 required:
   64   - compatible
   65   - reg
   66   - clocks
   67   - clock-names
   68   - cpu
   69 
   70 unevaluatedProperties: false
   71 
   72 examples:
   73   - |
   74     debug@f6590000 {
   75         compatible = "arm,coresight-cpu-debug", "arm,primecell";
   76         reg = <0xf6590000 0x1000>;
   77         clocks = <&sys_ctrl 1>;
   78         clock-names = "apb_pclk";
   79         cpu = <&cpu0>;
   80     };
   81 ...

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/arm/arm,coresight-cpu-debug.yaml

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sys/contrib/device-tree/Bindings/arm/arm,coresight-cpu-debug.yaml