cpus.yaml

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    1 # SPDX-License-Identifier: GPL-2.0
    2 %YAML 1.2
    3 ---
    4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
    5 $schema: http://devicetree.org/meta-schemas/core.yaml#
    6 
    7 title: ARM CPUs bindings
    8 
    9 maintainers:
   10   - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
   11 
   12 description: |+
   13   The device tree allows to describe the layout of CPUs in a system through
   14   the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
   15   defining properties for every cpu.
   16 
   17   Bindings for CPU nodes follow the Devicetree Specification, available from:
   18 
   19   https://www.devicetree.org/specifications/
   20 
   21   with updates for 32-bit and 64-bit ARM systems provided in this document.
   22 
   23   ================================
   24   Convention used in this document
   25   ================================
   26 
   27   This document follows the conventions described in the Devicetree
   28   Specification, with the addition:
   29 
   30   - square brackets define bitfields, eg reg[7:0] value of the bitfield in
   31     the reg property contained in bits 7 down to 0
   32 
   33   =====================================
   34   cpus and cpu node bindings definition
   35   =====================================
   36 
   37   The ARM architecture, in accordance with the Devicetree Specification,
   38   requires the cpus and cpu nodes to be present and contain the properties
   39   described below.
   40 
   41 properties:
   42   reg:
   43     maxItems: 1
   44     description: |
   45       Usage and definition depend on ARM architecture version and
   46       configuration:
   47 
   48       On uniprocessor ARM architectures previous to v7
   49       this property is required and must be set to 0.
   50 
   51       On ARM 11 MPcore based systems this property is
   52         required and matches the CPUID[11:0] register bits.
   53 
   54         Bits [11:0] in the reg cell must be set to
   55         bits [11:0] in CPU ID register.
   56 
   57         All other bits in the reg cell must be set to 0.
   58 
   59       On 32-bit ARM v7 or later systems this property is
   60         required and matches the CPU MPIDR[23:0] register
   61         bits.
   62 
   63         Bits [23:0] in the reg cell must be set to
   64         bits [23:0] in MPIDR.
   65 
   66         All other bits in the reg cell must be set to 0.
   67 
   68       On ARM v8 64-bit systems this property is required
   69         and matches the MPIDR_EL1 register affinity bits.
   70 
   71         * If cpus node's #address-cells property is set to 2
   72 
   73           The first reg cell bits [7:0] must be set to
   74           bits [39:32] of MPIDR_EL1.
   75 
   76           The second reg cell bits [23:0] must be set to
   77           bits [23:0] of MPIDR_EL1.
   78 
   79         * If cpus node's #address-cells property is set to 1
   80 
   81           The reg cell bits [23:0] must be set to bits [23:0]
   82           of MPIDR_EL1.
   83 
   84       All other bits in the reg cells must be set to 0.
   85 
   86   compatible:
   87     enum:
   88       - apple,icestorm
   89       - apple,firestorm
   90       - arm,arm710t
   91       - arm,arm720t
   92       - arm,arm740t
   93       - arm,arm7ej-s
   94       - arm,arm7tdmi
   95       - arm,arm7tdmi-s
   96       - arm,arm9es
   97       - arm,arm9ej-s
   98       - arm,arm920t
   99       - arm,arm922t
  100       - arm,arm925
  101       - arm,arm926e-s
  102       - arm,arm926ej-s
  103       - arm,arm940t
  104       - arm,arm946e-s
  105       - arm,arm966e-s
  106       - arm,arm968e-s
  107       - arm,arm9tdmi
  108       - arm,arm1020e
  109       - arm,arm1020t
  110       - arm,arm1022e
  111       - arm,arm1026ej-s
  112       - arm,arm1136j-s
  113       - arm,arm1136jf-s
  114       - arm,arm1156t2-s
  115       - arm,arm1156t2f-s
  116       - arm,arm1176jzf
  117       - arm,arm1176jz-s
  118       - arm,arm1176jzf-s
  119       - arm,arm11mpcore
  120       - arm,armv8 # Only for s/w models
  121       - arm,cortex-a5
  122       - arm,cortex-a7
  123       - arm,cortex-a8
  124       - arm,cortex-a9
  125       - arm,cortex-a12
  126       - arm,cortex-a15
  127       - arm,cortex-a17
  128       - arm,cortex-a32
  129       - arm,cortex-a34
  130       - arm,cortex-a35
  131       - arm,cortex-a53
  132       - arm,cortex-a55
  133       - arm,cortex-a57
  134       - arm,cortex-a65
  135       - arm,cortex-a72
  136       - arm,cortex-a73
  137       - arm,cortex-a75
  138       - arm,cortex-a76
  139       - arm,cortex-a77
  140       - arm,cortex-a78
  141       - arm,cortex-a78ae
  142       - arm,cortex-a510
  143       - arm,cortex-a710
  144       - arm,cortex-m0
  145       - arm,cortex-m0+
  146       - arm,cortex-m1
  147       - arm,cortex-m3
  148       - arm,cortex-m4
  149       - arm,cortex-r4
  150       - arm,cortex-r5
  151       - arm,cortex-r7
  152       - arm,cortex-x1
  153       - arm,cortex-x2
  154       - arm,neoverse-e1
  155       - arm,neoverse-n1
  156       - arm,neoverse-n2
  157       - arm,neoverse-v1
  158       - brcm,brahma-b15
  159       - brcm,brahma-b53
  160       - brcm,vulcan
  161       - cavium,thunder
  162       - cavium,thunder2
  163       - faraday,fa526
  164       - intel,sa110
  165       - intel,sa1100
  166       - marvell,feroceon
  167       - marvell,mohawk
  168       - marvell,pj4a
  169       - marvell,pj4b
  170       - marvell,sheeva-v5
  171       - marvell,sheeva-v7
  172       - nvidia,tegra132-denver
  173       - nvidia,tegra186-denver
  174       - nvidia,tegra194-carmel
  175       - qcom,krait
  176       - qcom,kryo
  177       - qcom,kryo250
  178       - qcom,kryo260
  179       - qcom,kryo280
  180       - qcom,kryo385
  181       - qcom,kryo468
  182       - qcom,kryo485
  183       - qcom,kryo560
  184       - qcom,kryo570
  185       - qcom,kryo685
  186       - qcom,kryo780
  187       - qcom,scorpion
  188 
  189   enable-method:
  190     $ref: '/schemas/types.yaml#/definitions/string'
  191     oneOf:
  192       # On ARM v8 64-bit this property is required
  193       - enum:
  194           - psci
  195           - spin-table
  196       # On ARM 32-bit systems this property is optional
  197       - enum:
  198           - actions,s500-smp
  199           - allwinner,sun6i-a31
  200           - allwinner,sun8i-a23
  201           - allwinner,sun9i-a80-smp
  202           - allwinner,sun8i-a83t-smp
  203           - amlogic,meson8-smp
  204           - amlogic,meson8b-smp
  205           - arm,realview-smp
  206           - aspeed,ast2600-smp
  207           - brcm,bcm11351-cpu-method
  208           - brcm,bcm23550
  209           - brcm,bcm2836-smp
  210           - brcm,bcm63138
  211           - brcm,bcm-nsp-smp
  212           - brcm,brahma-b15
  213           - marvell,armada-375-smp
  214           - marvell,armada-380-smp
  215           - marvell,armada-390-smp
  216           - marvell,armada-xp-smp
  217           - marvell,98dx3236-smp
  218           - marvell,mmp3-smp
  219           - mediatek,mt6589-smp
  220           - mediatek,mt81xx-tz-smp
  221           - qcom,gcc-msm8660
  222           - qcom,kpss-acc-v1
  223           - qcom,kpss-acc-v2
  224           - qcom,msm8226-smp
  225           - qcom,msm8909-smp
  226           # Only valid on ARM 32-bit, see above for ARM v8 64-bit
  227           - qcom,msm8916-smp
  228           - renesas,apmu
  229           - renesas,r9a06g032-smp
  230           - rockchip,rk3036-smp
  231           - rockchip,rk3066-smp
  232           - socionext,milbeaut-m10v-smp
  233           - ste,dbx500-smp
  234           - ti,am3352
  235           - ti,am4372
  236 
  237   cpu-release-addr:
  238     oneOf:
  239       - $ref: '/schemas/types.yaml#/definitions/uint32'
  240       - $ref: '/schemas/types.yaml#/definitions/uint64'
  241     description:
  242       The DT specification defines this as 64-bit always, but some 32-bit Arm
  243       systems have used a 32-bit value which must be supported.
  244       Required for systems that have an "enable-method"
  245         property value of "spin-table".
  246 
  247   cpu-idle-states:
  248     $ref: '/schemas/types.yaml#/definitions/phandle-array'
  249     items:
  250       maxItems: 1
  251     description: |
  252       List of phandles to idle state nodes supported
  253       by this cpu (see ./idle-states.yaml).
  254 
  255   capacity-dmips-mhz:
  256     description:
  257       u32 value representing CPU capacity (see ./cpu-capacity.txt) in
  258       DMIPS/MHz, relative to highest capacity-dmips-mhz
  259       in the system.
  260 
  261   cci-control-port: true
  262 
  263   dynamic-power-coefficient:
  264     $ref: '/schemas/types.yaml#/definitions/uint32'
  265     description:
  266       A u32 value that represents the running time dynamic
  267       power coefficient in units of uW/MHz/V^2. The
  268       coefficient can either be calculated from power
  269       measurements or derived by analysis.
  270 
  271       The dynamic power consumption of the CPU  is
  272       proportional to the square of the Voltage (V) and
  273       the clock frequency (f). The coefficient is used to
  274       calculate the dynamic power as below -
  275 
  276       Pdyn = dynamic-power-coefficient * V^2 * f
  277 
  278       where voltage is in V, frequency is in MHz.
  279 
  280   performance-domains:
  281     maxItems: 1
  282     description:
  283       List of phandles and performance domain specifiers, as defined by
  284       bindings of the performance domain provider. See also
  285       dvfs/performance-domain.yaml.
  286 
  287   power-domains:
  288     description:
  289       List of phandles and PM domain specifiers, as defined by bindings of the
  290       PM domain provider (see also ../power_domain.txt).
  291 
  292   power-domain-names:
  293     description:
  294       A list of power domain name strings sorted in the same order as the
  295       power-domains property.
  296 
  297       For PSCI based platforms, the name corresponding to the index of the PSCI
  298       PM domain provider, must be "psci".
  299 
  300   qcom,saw:
  301     $ref: '/schemas/types.yaml#/definitions/phandle'
  302     description: |
  303       Specifies the SAW* node associated with this CPU.
  304 
  305       Required for systems that have an "enable-method" property
  306       value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
  307 
  308       * arm/msm/qcom,saw2.txt
  309 
  310   qcom,acc:
  311     $ref: '/schemas/types.yaml#/definitions/phandle'
  312     description: |
  313       Specifies the ACC* node associated with this CPU.
  314 
  315       Required for systems that have an "enable-method" property
  316       value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
  317       "qcom,msm8916-smp".
  318 
  319       * arm/msm/qcom,kpss-acc.txt
  320 
  321   rockchip,pmu:
  322     $ref: '/schemas/types.yaml#/definitions/phandle'
  323     description: |
  324       Specifies the syscon node controlling the cpu core power domains.
  325 
  326       Optional for systems that have an "enable-method"
  327       property value of "rockchip,rk3066-smp"
  328       While optional, it is the preferred way to get access to
  329       the cpu-core power-domains.
  330 
  331   secondary-boot-reg:
  332     $ref: '/schemas/types.yaml#/definitions/uint32'
  333     description: |
  334       Required for systems that have an "enable-method" property value of
  335       "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
  336 
  337       This includes the following SoCs: |
  338       BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
  339       BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
  340 
  341       The secondary-boot-reg property is a u32 value that specifies the
  342       physical address of the register used to request the ROM holding pen
  343       code release a secondary CPU. The value written to the register is
  344       formed by encoding the target CPU id into the low bits of the
  345       physical start address it should jump to.
  346 
  347 if:
  348   # If the enable-method property contains one of those values
  349   properties:
  350     enable-method:
  351       contains:
  352         enum:
  353           - brcm,bcm11351-cpu-method
  354           - brcm,bcm23550
  355           - brcm,bcm-nsp-smp
  356   # and if enable-method is present
  357   required:
  358     - enable-method
  359 
  360 then:
  361   required:
  362     - secondary-boot-reg
  363 
  364 required:
  365   - device_type
  366   - reg
  367   - compatible
  368 
  369 dependencies:
  370   rockchip,pmu: [enable-method]
  371 
  372 additionalProperties: true
  373 
  374 examples:
  375   - |
  376     cpus {
  377       #size-cells = <0>;
  378       #address-cells = <1>;
  379 
  380       cpu@0 {
  381         device_type = "cpu";
  382         compatible = "arm,cortex-a15";
  383         reg = <0x0>;
  384       };
  385 
  386       cpu@1 {
  387         device_type = "cpu";
  388         compatible = "arm,cortex-a15";
  389         reg = <0x1>;
  390       };
  391 
  392       cpu@100 {
  393         device_type = "cpu";
  394         compatible = "arm,cortex-a7";
  395         reg = <0x100>;
  396       };
  397 
  398       cpu@101 {
  399         device_type = "cpu";
  400         compatible = "arm,cortex-a7";
  401         reg = <0x101>;
  402       };
  403     };
  404 
  405   - |
  406     // Example 2 (Cortex-A8 uniprocessor 32-bit system):
  407     cpus {
  408       #size-cells = <0>;
  409       #address-cells = <1>;
  410 
  411       cpu@0 {
  412         device_type = "cpu";
  413         compatible = "arm,cortex-a8";
  414         reg = <0x0>;
  415       };
  416     };
  417 
  418   - |
  419     // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
  420     cpus {
  421       #size-cells = <0>;
  422       #address-cells = <1>;
  423 
  424       cpu@0 {
  425         device_type = "cpu";
  426         compatible = "arm,arm926ej-s";
  427         reg = <0x0>;
  428       };
  429     };
  430 
  431   - |
  432     //  Example 4 (ARM Cortex-A57 64-bit system):
  433     cpus {
  434       #size-cells = <0>;
  435       #address-cells = <2>;
  436 
  437       cpu@0 {
  438         device_type = "cpu";
  439         compatible = "arm,cortex-a57";
  440         reg = <0x0 0x0>;
  441         enable-method = "spin-table";
  442         cpu-release-addr = <0 0x20000000>;
  443       };
  444 
  445       cpu@1 {
  446         device_type = "cpu";
  447         compatible = "arm,cortex-a57";
  448         reg = <0x0 0x1>;
  449         enable-method = "spin-table";
  450         cpu-release-addr = <0 0x20000000>;
  451       };
  452 
  453       cpu@100 {
  454         device_type = "cpu";
  455         compatible = "arm,cortex-a57";
  456         reg = <0x0 0x100>;
  457         enable-method = "spin-table";
  458         cpu-release-addr = <0 0x20000000>;
  459       };
  460 
  461       cpu@101 {
  462         device_type = "cpu";
  463         compatible = "arm,cortex-a57";
  464         reg = <0x0 0x101>;
  465         enable-method = "spin-table";
  466         cpu-release-addr = <0 0x20000000>;
  467       };
  468 
  469       cpu@10000 {
  470         device_type = "cpu";
  471         compatible = "arm,cortex-a57";
  472         reg = <0x0 0x10000>;
  473         enable-method = "spin-table";
  474         cpu-release-addr = <0 0x20000000>;
  475       };
  476 
  477       cpu@10001 {
  478         device_type = "cpu";
  479         compatible = "arm,cortex-a57";
  480         reg = <0x0 0x10001>;
  481         enable-method = "spin-table";
  482         cpu-release-addr = <0 0x20000000>;
  483       };
  484 
  485       cpu@10100 {
  486         device_type = "cpu";
  487         compatible = "arm,cortex-a57";
  488         reg = <0x0 0x10100>;
  489         enable-method = "spin-table";
  490         cpu-release-addr = <0 0x20000000>;
  491       };
  492 
  493       cpu@10101 {
  494         device_type = "cpu";
  495         compatible = "arm,cortex-a57";
  496         reg = <0x0 0x10101>;
  497         enable-method = "spin-table";
  498         cpu-release-addr = <0 0x20000000>;
  499       };
  500 
  501       cpu@100000000 {
  502         device_type = "cpu";
  503         compatible = "arm,cortex-a57";
  504         reg = <0x1 0x0>;
  505         enable-method = "spin-table";
  506         cpu-release-addr = <0 0x20000000>;
  507       };
  508 
  509       cpu@100000001 {
  510         device_type = "cpu";
  511         compatible = "arm,cortex-a57";
  512         reg = <0x1 0x1>;
  513         enable-method = "spin-table";
  514         cpu-release-addr = <0 0x20000000>;
  515       };
  516 
  517       cpu@100000100 {
  518         device_type = "cpu";
  519         compatible = "arm,cortex-a57";
  520         reg = <0x1 0x100>;
  521         enable-method = "spin-table";
  522         cpu-release-addr = <0 0x20000000>;
  523       };
  524 
  525       cpu@100000101 {
  526         device_type = "cpu";
  527         compatible = "arm,cortex-a57";
  528         reg = <0x1 0x101>;
  529         enable-method = "spin-table";
  530         cpu-release-addr = <0 0x20000000>;
  531       };
  532 
  533       cpu@100010000 {
  534         device_type = "cpu";
  535         compatible = "arm,cortex-a57";
  536         reg = <0x1 0x10000>;
  537         enable-method = "spin-table";
  538         cpu-release-addr = <0 0x20000000>;
  539       };
  540 
  541       cpu@100010001 {
  542         device_type = "cpu";
  543         compatible = "arm,cortex-a57";
  544         reg = <0x1 0x10001>;
  545         enable-method = "spin-table";
  546         cpu-release-addr = <0 0x20000000>;
  547       };
  548 
  549       cpu@100010100 {
  550         device_type = "cpu";
  551         compatible = "arm,cortex-a57";
  552         reg = <0x1 0x10100>;
  553         enable-method = "spin-table";
  554         cpu-release-addr = <0 0x20000000>;
  555       };
  556 
  557       cpu@100010101 {
  558         device_type = "cpu";
  559         compatible = "arm,cortex-a57";
  560         reg = <0x1 0x10101>;
  561         enable-method = "spin-table";
  562         cpu-release-addr = <0 0x20000000>;
  563       };
  564     };
  565 ...
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/arm/cpus.yaml

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/Bindings/arm/cpus.yaml
