fsl,scu.txt

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    1 NXP i.MX System Controller Firmware (SCFW)
    2 --------------------------------------------------------------------
    3 
    4 The System Controller Firmware (SCFW) is a low-level system function
    5 which runs on a dedicated Cortex-M core to provide power, clock, and
    6 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
    7 (QM, QP), and i.MX8QX (QXP, DX).
    8 
    9 The AP communicates with the SC using a multi-ported MU module found
   10 in the LSIO subsystem. The current definition of this MU module provides
   11 5 remote AP connections to the SC to support up to 5 execution environments
   12 (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
   13 with the LSIO DSC IP bus. The SC firmware will communicate with this MU
   14 using the MSI bus.
   15 
   16 System Controller Device Node:
   17 ============================================================
   18 
   19 The scu node with the following properties shall be under the /firmware/ node.
   20 
   21 Required properties:
   22 -------------------
   23 - compatible:   should be "fsl,imx-scu".
   24 - mbox-names:   should include "tx0", "tx1", "tx2", "tx3",
   25                                "rx0", "rx1", "rx2", "rx3";
   26                 include "gip3" if want to support general MU interrupt.
   27 - mboxes:       List of phandle of 4 MU channels for tx, 4 MU channels for
   28                 rx, and 1 optional MU channel for general interrupt.
   29                 All MU channels must be in the same MU instance.
   30                 Cross instances are not allowed. The MU instance can only
   31                 be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
   32                 to make sure use the one which is not conflict with other
   33                 execution environments. e.g. ATF.
   34                 Note:
   35                 Channel 0 must be "tx0" or "rx0".
   36                 Channel 1 must be "tx1" or "rx1".
   37                 Channel 2 must be "tx2" or "rx2".
   38                 Channel 3 must be "tx3" or "rx3".
   39                 General interrupt rx channel must be "gip3".
   40                 e.g.
   41                 mboxes = <&lsio_mu1 0 0
   42                           &lsio_mu1 0 1
   43                           &lsio_mu1 0 2
   44                           &lsio_mu1 0 3
   45                           &lsio_mu1 1 0
   46                           &lsio_mu1 1 1
   47                           &lsio_mu1 1 2
   48                           &lsio_mu1 1 3
   49                           &lsio_mu1 3 3>;
   50                 See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
   51                 for detailed mailbox binding.
   52 
   53 Note: Each mu which supports general interrupt should have an alias correctly
   54 numbered in "aliases" node.
   55 e.g.
   56 aliases {
   57         mu1 = &lsio_mu1;
   58 };
   59 
   60 i.MX SCU Client Device Node:
   61 ============================================================
   62 
   63 Client nodes are maintained as children of the relevant IMX-SCU device node.
   64 
   65 Power domain bindings based on SCU Message Protocol
   66 ------------------------------------------------------------
   67 
   68 This binding for the SCU power domain providers uses the generic power
   69 domain binding[2].
   70 
   71 Required properties:
   72 - compatible:           Should be one of:
   73                           "fsl,imx8qm-scu-pd",
   74                           "fsl,imx8qxp-scu-pd"
   75                         followed by "fsl,scu-pd"
   76 
   77 - #power-domain-cells:  Must be 1. Contains the Resource ID used by
   78                         SCU commands.
   79                         See detailed Resource ID list from:
   80                         include/dt-bindings/firmware/imx/rsrc.h
   81 
   82 Clock bindings based on SCU Message Protocol
   83 ------------------------------------------------------------
   84 
   85 This binding uses the common clock binding[1].
   86 
   87 Required properties:
   88 - compatible:           Should be one of:
   89                           "fsl,imx8dxl-clk"
   90                           "fsl,imx8qm-clk"
   91                           "fsl,imx8qxp-clk"
   92                         followed by "fsl,scu-clk"
   93 - #clock-cells:         Should be 2.
   94                         Contains the Resource and Clock ID value.
   95 - clocks:               List of clock specifiers, must contain an entry for
   96                         each required entry in clock-names
   97 - clock-names:          Should include entries "xtal_32KHz", "xtal_24MHz"
   98 
   99 The clock consumer should specify the desired clock by having the clock
  100 ID in its "clocks" phandle cell.
  101 
  102 See the full list of clock IDs from:
  103 include/dt-bindings/clock/imx8qxp-clock.h
  104 
  105 Pinctrl bindings based on SCU Message Protocol
  106 ------------------------------------------------------------
  107 
  108 This binding uses the i.MX common pinctrl binding[3].
  109 
  110 Required properties:
  111 - compatible:           Should be one of:
  112                         "fsl,imx8qm-iomuxc",
  113                         "fsl,imx8qxp-iomuxc",
  114                         "fsl,imx8dxl-iomuxc".
  115 
  116 Required properties for Pinctrl sub nodes:
  117 - fsl,pins:             Each entry consists of 3 integers which represents
  118                         the mux and config setting for one pin. The first 2
  119                         integers <pin_id mux_mode> are specified using a
  120                         PIN_FUNC_ID macro, which can be found in
  121                         <dt-bindings/pinctrl/pads-imx8qm.h>,
  122                         <dt-bindings/pinctrl/pads-imx8qxp.h>,
  123                         <dt-bindings/pinctrl/pads-imx8dxl.h>.
  124                         The last integer CONFIG is the pad setting value like
  125                         pull-up on this pin.
  126 
  127                         Please refer to i.MX8QXP Reference Manual for detailed
  128                         CONFIG settings.
  129 
  130 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
  131 [2] Documentation/devicetree/bindings/power/power-domain.yaml
  132 [3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
  133 
  134 RTC bindings based on SCU Message Protocol
  135 ------------------------------------------------------------
  136 
  137 Required properties:
  138 - compatible: should be "fsl,imx8qxp-sc-rtc";
  139 
  140 OCOTP bindings based on SCU Message Protocol
  141 ------------------------------------------------------------
  142 Required properties:
  143 - compatible:           Should be one of:
  144                         "fsl,imx8qm-scu-ocotp",
  145                         "fsl,imx8qxp-scu-ocotp".
  146 - #address-cells:       Must be 1. Contains byte index
  147 - #size-cells:          Must be 1. Contains byte length
  148 
  149 Optional Child nodes:
  150 
  151 - Data cells of ocotp:
  152   Detailed bindings are described in bindings/nvmem/nvmem.txt
  153 
  154 Watchdog bindings based on SCU Message Protocol
  155 ------------------------------------------------------------
  156 
  157 Required properties:
  158 - compatible: should be:
  159               "fsl,imx8qxp-sc-wdt"
  160               followed by "fsl,imx-sc-wdt";
  161 Optional properties:
  162 - timeout-sec: contains the watchdog timeout in seconds.
  163 
  164 SCU key bindings based on SCU Message Protocol
  165 ------------------------------------------------------------
  166 
  167 Required properties:
  168 - compatible: should be:
  169               "fsl,imx8qxp-sc-key"
  170               followed by "fsl,imx-sc-key";
  171 - linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml
  172 
  173 Thermal bindings based on SCU Message Protocol
  174 ------------------------------------------------------------
  175 
  176 Required properties:
  177 - compatible:                   Should be :
  178                                   "fsl,imx8qxp-sc-thermal"
  179                                 followed by "fsl,imx-sc-thermal";
  180 
  181 - #thermal-sensor-cells:        See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml
  182                                 for a description.
  183 
  184 Example (imx8qxp):
  185 -------------
  186 aliases {
  187         mu1 = &lsio_mu1;
  188 };
  189 
  190 lsio_mu1: mailbox@5d1c0000 {
  191         ...
  192         #mbox-cells = <2>;
  193 };
  194 
  195 firmware {
  196         scu {
  197                 compatible = "fsl,imx-scu";
  198                 mbox-names = "tx0", "tx1", "tx2", "tx3",
  199                              "rx0", "rx1", "rx2", "rx3",
  200                              "gip3";
  201                 mboxes = <&lsio_mu1 0 0
  202                           &lsio_mu1 0 1
  203                           &lsio_mu1 0 2
  204                           &lsio_mu1 0 3
  205                           &lsio_mu1 1 0
  206                           &lsio_mu1 1 1
  207                           &lsio_mu1 1 2
  208                           &lsio_mu1 1 3
  209                           &lsio_mu1 3 3>;
  210 
  211                 clk: clk {
  212                         compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
  213                         #clock-cells = <2>;
  214                 };
  215 
  216                 iomuxc {
  217                         compatible = "fsl,imx8qxp-iomuxc";
  218 
  219                         pinctrl_lpuart0: lpuart0grp {
  220                                 fsl,pins = <
  221                                         SC_P_UART0_RX_ADMA_UART0_RX     0x06000020
  222                                         SC_P_UART0_TX_ADMA_UART0_TX     0x06000020
  223                                 >;
  224                         };
  225                         ...
  226                 };
  227 
  228                 ocotp: imx8qx-ocotp {
  229                         compatible = "fsl,imx8qxp-scu-ocotp";
  230                         #address-cells = <1>;
  231                         #size-cells = <1>;
  232 
  233                         fec_mac0: mac@2c4 {
  234                                 reg = <0x2c4 8>;
  235                         };
  236                 };
  237 
  238                 pd: imx8qx-pd {
  239                         compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
  240                         #power-domain-cells = <1>;
  241                 };
  242 
  243                 rtc: rtc {
  244                         compatible = "fsl,imx8qxp-sc-rtc";
  245                 };
  246 
  247                 scu_key: scu-key {
  248                         compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
  249                         linux,keycodes = <KEY_POWER>;
  250                 };
  251 
  252                 watchdog {
  253                         compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
  254                         timeout-sec = <60>;
  255                 };
  256 
  257                 tsens: thermal-sensor {
  258                         compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
  259                         #thermal-sensor-cells = <1>;
  260                 };
  261         };
  262 };
  263 
  264 serial@5a060000 {
  265         ...
  266         pinctrl-names = "default";
  267         pinctrl-0 = <&pinctrl_lpuart0>;
  268         clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
  269         clock-names = "ipg";
  270         power-domains = <&pd IMX_SC_R_UART_0>;
  271 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/Bindings/arm/freescale/fsl,scu.txt

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sys/contrib/device-tree/Bindings/arm/freescale/fsl,scu.txt